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-- Company: 
-- Engineer: 
-- 
-- Create Date: 13.04.2021 10:19:15
-- Design Name: 
-- Module Name: System - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity System is
    Port ( led : out STD_LOGIC_VECTOR (7 downto 0);
           flag : out STD_LOGIC_VECTOR (3 downto 0);
           sw : in STD_LOGIC_VECTOR (15 downto 0);
           btnC : in STD_LOGIC;
           btnL : in STD_LOGIC;
           btnR : in STD_LOGIC);
end System;

architecture Structural of System is
    component ALU
        Generic (Nb_bits : Natural);
        Port ( A : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
               B : in STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
               OP : in STD_LOGIC_VECTOR (1 downto 0);
               S : out STD_LOGIC_VECTOR (Nb_bits-1 downto 0);
               N : out STD_LOGIC;
               O : out STD_LOGIC;
               Z : out STD_LOGIC;
               C : out STD_LOGIC);
    end component;
    signal aux: STD_LOGIC_VECTOR (1 downto 0);
    signal aux4: STD_LOGIC;
    signal aux5: STD_LOGIC;
    signal aux6: STD_LOGIC;
    signal aux7: STD_LOGIC;
begin
    aux <= "01" when btnC = '1' else
           "10" when btnR = '1' else
           "11" when btnL = '1' else
           "00";
    flag <= aux4 & aux5 & aux6 & aux7;
    My_ALU: ALU generic map (Nb_bits => 8) port map(sw (15 downto 8), sw (7 downto 0), aux, led, aux4, aux5, aux6, aux7);
end Structural;