169 lines
4.9 KiB
VHDL
169 lines
4.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 28.06.2021 17:27:26
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-- Design Name:
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-- Module Name: ScreenSystem - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ScreenSystem is
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Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0);
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vgaBlue : out STD_LOGIC_VECTOR (3 downto 0);
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vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
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Hsync : out STD_LOGIC;
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Vsync : out STD_LOGIC;
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btnC : in STD_LOGIC;
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CLK : in STD_LOGIC
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);
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end ScreenSystem;
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architecture Behavioral of ScreenSystem is
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component VGAControler is
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Generic ( HEIGHT : Natural;
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WIDTH : Natural;
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X_PulseWidth : Natural;
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X_FrontPorch : Natural;
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X_BackPorch : Natural;
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Y_PulseWidth : Natural;
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Y_FrontPorch : Natural;
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Y_BackPorch : Natural
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);
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Port ( VGA_RED : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_BLUE : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
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VGA_HS : out STD_LOGIC;
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VGA_VS : out STD_LOGIC;
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X : out Natural;
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Y : out Natural;
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PIXEL_ON : in STD_LOGIC;
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC);
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end component;
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component clk_wiz_0
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port
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(-- Clock in ports
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clk_in1 : in std_logic;
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-- Clock out ports
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clk_out1 : out std_logic
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);
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end component;
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component Ecran is
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Generic ( HEIGHT : Natural;
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WIDTH : Natural
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);
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Port ( CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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Data_Av : in STD_LOGIC;
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Data_IN : in Natural;
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X : in Natural;
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Y : in Natural;
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OUT_ON : out STD_LOGIC);
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end component;
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signal my_X : Natural := 0;
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signal my_Y : Natural := 0;
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signal my_PIXEL_ON : STD_LOGIC := '0';
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signal compteur : natural := 0;
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signal my_CLK : STD_LOGIC := '0';
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signal RST : STD_LOGIC;
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begin
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instanceVGA : VGAControler
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-- generic map( HEIGHT => 480,
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-- WIDTH => 640,
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-- X_PulseWidth => 96,
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-- X_FrontPorch => 16,
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-- X_BackPorch => 48,
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-- Y_PulseWidth => 2,
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-- Y_FrontPorch => 10,
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-- Y_BackPorch => 33)
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generic map( HEIGHT => 1024,
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WIDTH => 1280,
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X_PulseWidth => 112,
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X_FrontPorch => 48,
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X_BackPorch => 248,
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Y_PulseWidth => 3,
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Y_FrontPorch => 1,
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Y_BackPorch => 38)
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port map( VGA_RED => vgaRed,
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VGA_BLUE => vgaBlue,
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VGA_GREEN => vgaGreen,
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VGA_HS => Hsync,
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VGA_VS => Vsync,
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X => my_X,
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Y => my_Y,
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PIXEL_ON => my_PIXEL_ON,
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CLK => my_CLK,
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RST => RST);
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clk_wiz_0_inst : clk_wiz_0
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port map (
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clk_in1 => CLK,
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clk_out1 => my_CLK
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);
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-- process
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-- begin
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-- wait until CLK'event and CLK = '1';
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-- compteur <= (compteur + 1) mod 4;
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-- if (compteur = 0) then
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-- my_CLK <= '1';
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-- elsif (compteur = 2) then
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-- my_CLK <= '0';
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-- end if;
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-- end process;
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instance_Ecran : Ecran
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generic map ( HEIGHT => 1024,
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WIDTH => 1280
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)
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port map ( CLK => CLK,
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RST => RST,
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Data_Av => '0',
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Data_IN => 0,
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X => my_X,
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Y => my_Y,
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OUT_ON => my_PIXEL_ON);
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-- Gestion du RST (inversion d'état)
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RST <= '1' when btnC = '0' else
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'0';
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end Behavioral;
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