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-- Company: 
-- Engineer: 
-- 
-- Create Date: 28.06.2021 17:27:26
-- Design Name: 
-- Module Name: ScreenSystem - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ScreenSystem is
  Port (  vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
          vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
          vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
          Hsync    : out STD_LOGIC;
          Vsync    : out STD_LOGIC;
          
          
          btnC : in STD_LOGIC;
          CLK       : in  STD_LOGIC
       );
end ScreenSystem;

architecture Behavioral of ScreenSystem is

    component VGAControler is
    Generic (  HEIGHT    : Natural;
               WIDTH     : Natural;
               X_PulseWidth : Natural;
               X_FrontPorch : Natural;
               X_BackPorch  : Natural;
               Y_PulseWidth : Natural;
               Y_FrontPorch : Natural;
               Y_BackPorch  : Natural              
    );
    Port (     VGA_RED   : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_BLUE  : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_GREEN : out STD_LOGIC_VECTOR (3 downto 0);
               VGA_HS    : out STD_LOGIC;
               VGA_VS    : out STD_LOGIC;
               
               X         : out Natural;
               Y         : out Natural;
               PIXEL_ON  : in STD_LOGIC;
               
               CLK       : in STD_LOGIC;
               RST       : in STD_LOGIC);
    end component; 
    
    component clk_wiz_0
    port
     (-- Clock in ports
      clk_in1           : in     std_logic;
      -- Clock out ports
      clk_out1          : out    std_logic
     );
    end component;
    
    component Ecran is
        Generic (  HEIGHT         : Natural;
                   WIDTH          : Natural        
        );
        Port (     CLK            : in STD_LOGIC;
                   RST            : in STD_LOGIC;
                   Data_Av        : in STD_LOGIC;
                   Data_IN        : in Natural;
                   X              : in Natural;
                   Y              : in Natural;
                   OUT_ON         : out STD_LOGIC);
    end component;
    
    signal my_X : Natural := 0;
    signal my_Y : Natural := 0;
    signal my_PIXEL_ON : STD_LOGIC := '0';
    
    signal compteur : natural := 0;
    signal my_CLK : STD_LOGIC := '0';
    signal RST : STD_LOGIC;

begin

    instanceVGA : VGAControler 
--    generic map(  HEIGHT => 480,
--                  WIDTH => 640,
--                  X_PulseWidth => 96,
--                  X_FrontPorch => 16,
--                  X_BackPorch  => 48,
--                  Y_PulseWidth => 2,
--                  Y_FrontPorch => 10,
--                  Y_BackPorch  => 33)
    generic map(  HEIGHT => 1024,
                  WIDTH => 1280,
                  X_PulseWidth => 112,
                  X_FrontPorch => 48,
                  X_BackPorch  => 248,
                  Y_PulseWidth => 3,
                  Y_FrontPorch => 1,
                  Y_BackPorch  => 38)
    port map(  VGA_RED   => vgaRed,
               VGA_BLUE  => vgaBlue,
               VGA_GREEN => vgaGreen,
               VGA_HS    => Hsync,
               VGA_VS    => Vsync,
                 
               X         => my_X,
               Y         => my_Y,
               PIXEL_ON  => my_PIXEL_ON,
                 
               CLK       => my_CLK,
               RST       => RST);
               
    
    clk_wiz_0_inst : clk_wiz_0
    port map (
              clk_in1 => CLK,
              clk_out1 => my_CLK
             );
          
--    process 
--    begin
--        wait until CLK'event and CLK = '1';
--        compteur <= (compteur + 1) mod 4;
--        if (compteur = 0) then
--            my_CLK <= '1';
--        elsif (compteur = 2) then
--            my_CLK <= '0';
--        end if;
--    end process;

    instance_Ecran : Ecran
    generic map (  HEIGHT => 1024,
                   WIDTH  => 1280        
    )
    port map (     CLK     => CLK,
                   RST     => RST,
                   Data_Av => '0',
                   Data_IN => 0,
                   X => my_X,
                   Y => my_Y,
                   OUT_ON => my_PIXEL_ON);

    -- Gestion du RST (inversion d'état)
    RST <= '1' when btnC = '0' else
           '0';

end Behavioral;