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Paul Faure 6 months ago
parent
commit
be099a88a7

+ 67
- 5
.gitignore View File

@@ -1,5 +1,67 @@
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-Compteur8BitsBasys3.ip_user_files/*
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-Compteur8BitsBasys3.cache/*
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-Compteur8BitsBasys3.hw/*
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-Compteur8BitsBasys3.runs/*
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-Compteur8BitsBasys3.sim/*
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+# Blacklist everything
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+/*
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+
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+# whitelist the necessary files and folders, this gets everything from inside them too
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+!.gitignore
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+!.gitmodules
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+!README.md
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+!hw_handoff/
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+!proj/
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+!repo/
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+!sdk/
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+!src/
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+
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+#Digilent Added ignore rules for Vivado projects
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+
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+# sdk exclusions
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+sdk/.metadata
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+sdk/**/*RemoteSystemsTempFiles
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+sdk/**/*Debug/*
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+sdk/**/*Release
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+sdk/**/*webtalk
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+sdk/.sdk
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+sdk/*.log
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+# ignore everything in the hw_platform
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+sdk/*hw_platform*/*
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+# except
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+!sdk/*hw_platform*/*.hdf
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+!sdk/*hw_platform*/.*project
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+# ignore everything in the BSP
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+sdk/*_bsp*/*
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+# except
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+!sdk/*_bsp*/system.mss
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+!sdk/*_bsp*/Makefile
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+!sdk/*_bsp*/.*project
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+# include the relevant elf files
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+!sdk/**/*Debug/*.elf
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+!sdk/**/*Debug/*.elf.size
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+
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+repo/**
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+# whitelist vivado-library if it exists
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+!repo/vivado-library
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+#do not white-list submodule contents
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+!repo/local
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+!repo/local/**
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+!repo/cache
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+repo/cache/**
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+
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+# Make sure we keep only xci files in ip src subfolder
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+src/ip/*/**
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+!src/ip/*/*.xci
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+!src/ip/*/*.prj
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+# Do not ignore anything in src/others
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+!src/others/*
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+# Do not ignore block diagram files
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+!src/bd/**
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+
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+
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+# ignore everything in project folder
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+proj/*
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+# except this file and project generators
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+!proj/create_project.tcl
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+!proj/cleanup.cmd
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+!proj/cleanup.sh
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+!proj/release.py
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+
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+# keep the empty folders
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+!**/.keep

+ 0
- 299
Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -1,299 +0,0 @@
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-## This file is a general .xdc for the Basys3 rev B board
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-## To use it in a project:
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-## - uncomment the lines corresponding to used pins
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-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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-
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-## Clock signal
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-set_property PACKAGE_PIN W5 [get_ports CLK]
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-set_property IOSTANDARD LVCMOS33 [get_ports CLK]
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-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
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-
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-## Switches
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-set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
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-set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
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-set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
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-set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
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-set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
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-set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
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-set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
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-set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
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-#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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-#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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-#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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-#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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-#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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-#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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-#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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-#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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-
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-
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-## LEDs
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-set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
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-set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
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-set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
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-set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
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-set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
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-set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
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-set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
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-set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
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-set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
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-#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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-#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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-#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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-#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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-#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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-#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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-#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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-#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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-#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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-
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-
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-##7 segment display
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-#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
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-#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
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-#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
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-#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
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-#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
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-#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
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-#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
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-
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-#set_property PACKAGE_PIN V7 [get_ports dp]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
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-
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-#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
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-#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
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-#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
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-#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
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-
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-
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-##Buttons
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-set_property PACKAGE_PIN U18 [get_ports btnC]
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-set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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-#set_property PACKAGE_PIN T18 [get_ports btnU]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
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-set_property PACKAGE_PIN W19 [get_ports btnL]
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-set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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-set_property PACKAGE_PIN T17 [get_ports btnR]
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-set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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-set_property PACKAGE_PIN U17 [get_ports btnD]
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-set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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-
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-
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-
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-##Pmod Header JA
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-##Sch name = JA1
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-#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
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-##Sch name = JA2
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-#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
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-##Sch name = JA3
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-#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
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-##Sch name = JA4
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-#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
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-##Sch name = JA7
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-#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
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-##Sch name = JA8
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-#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
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-##Sch name = JA9
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-#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
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-##Sch name = JA10
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-#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
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-
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-
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-
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-##Pmod Header JB
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-##Sch name = JB1
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-#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
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-##Sch name = JB2
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-#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
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-##Sch name = JB3
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-#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
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-##Sch name = JB4
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-#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
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-##Sch name = JB7
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-#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
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-##Sch name = JB8
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-#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
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-##Sch name = JB9
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-#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
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-##Sch name = JB10
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-#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
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-
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-
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-
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-##Pmod Header JC
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-##Sch name = JC1
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-#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
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-##Sch name = JC2
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-#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
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-##Sch name = JC3
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-#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
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-##Sch name = JC4
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-#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
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-##Sch name = JC7
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-#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
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-##Sch name = JC8
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-#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
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-##Sch name = JC9
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-#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
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-##Sch name = JC10
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-#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
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-
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-
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-##Pmod Header JXADC
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-##Sch name = XA1_P
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-#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
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-##Sch name = XA2_P
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-#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
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-##Sch name = XA3_P
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-#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
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-##Sch name = XA4_P
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-#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
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-##Sch name = XA1_N
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-#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
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-##Sch name = XA2_N
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-#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
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-##Sch name = XA3_N
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-#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
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-##Sch name = XA4_N
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-#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
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-
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-
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-
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-##VGA Connector
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-#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
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-#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
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-#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
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-#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
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-#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
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-#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
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-#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
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-#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
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-#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
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-#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
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-#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
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-#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
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-#set_property PACKAGE_PIN P19 [get_ports Hsync]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
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-#set_property PACKAGE_PIN R19 [get_ports Vsync]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
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-
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-
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-##USB-RS232 Interface
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-#set_property PACKAGE_PIN B18 [get_ports RsRx]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
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-#set_property PACKAGE_PIN A18 [get_ports RsTx]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
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-
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-
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-##USB HID (PS/2)
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-#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
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-	#set_property PULLUP true [get_ports PS2Clk]
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-#set_property PACKAGE_PIN B17 [get_ports PS2Data]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
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-	#set_property PULLUP true [get_ports PS2Data]
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-
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-
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-##Quad SPI Flash
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-##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
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-##STARTUPE2 primitive.
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-#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
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-#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
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-#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
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-#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
293
-#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
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-	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
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-
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-
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-## Configuration options, can be used for all designs
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-set_property CONFIG_VOLTAGE 3.3 [current_design]
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-set_property CFGBVS VCCO [current_design]

+ 0
- 31
Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd View File

@@ -1,53 +0,0 @@
1
-----------------------------------------------------------------------------------
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-----------------------------------------------------------------------------------
3
-
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-
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-library IEEE;
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-use IEEE.STD_LOGIC_1164.ALL;
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-
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---use IEEE.NUMERIC_STD.ALL;
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-
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---library UNISIM;
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---use UNISIM.VComponents.all;
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-
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-entity test_Compteur is
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-end test_Compteur;
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-
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-architecture Behavioral of test_Compteur is
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-    component Compteur is
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-        Port ( CK : in STD_LOGIC;
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-               RST : in STD_LOGIC;
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-               SENS : in STD_LOGIC;
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-               LOAD : in STD_LOGIC;
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-               EN : in STD_LOGIC;
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-               Din : in STD_LOGIC_VECTOR (7 downto 0);
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-               Dout : out STD_LOGIC_VECTOR (7 downto 0));
25
-    end component;
26
-     
27
-    signal CK          
28
-begin
29
-
30
-
31
-end Behavioral;

+ 0
- 33
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd View File

@@ -1,54 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity ClockDivider10 is
14
-    Port ( clk_in : in STD_LOGIC;
15
-           clk_out : out STD_LOGIC);
16
-end ClockDivider10;
17
-
18
-architecture Behavioral of ClockDivider10 is
19
-    subtype int10 is INTEGER range 0 to 10;
20
-    signal N : int10 := 0;
21
-    signal aux : STD_LOGIC;
22
-begin
23
-    process
24
-    begin
25
-        wait until clk_in'event and clk_in = '1';
26
-        N <= N + 1;
27
-        if N = 10 then
28
-            aux <= not aux;
29
-            N <= 0;
30
-        end if;
31
-    end process;
32
-    clk_out <= aux;
33
-end Behavioral;

+ 0
- 29
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd View File

@@ -1,50 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity ClockDivider1000 is
14
-    Port ( clk_in : in STD_LOGIC;
15
-           clk_out : out STD_LOGIC);
16
-end ClockDivider1000;
17
-
18
-architecture Structural of ClockDivider1000 is
19
-    component ClockDivider10
20
-        Port ( clk_in : in STD_LOGIC;
21
-               clk_out : out STD_LOGIC);
22
-    end component;
23
-    
24
-    signal aux1, aux2 : STD_LOGIC;
25
-begin
26
-    U1: ClockDivider10 port map(clk_in, aux1);
27
-    U2: ClockDivider10 port map(aux1, aux2);
28
-    U3: ClockDivider10 port map(aux2, clk_out);
29
-end Structural;

+ 0
- 42
Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd View File

@@ -1,64 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
8
-
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity Compteur is
14
-    Port ( CK : in STD_LOGIC;
15
-           RST : in STD_LOGIC;
16
-           SENS : in STD_LOGIC;
17
-           LOAD : in STD_LOGIC;
18
-           EN : in STD_LOGIC;
19
-           Din : in STD_LOGIC_VECTOR (7 downto 0);
20
-           Dout : out STD_LOGIC_VECTOR (7 downto 0));
21
-end Compteur;
22
-
23
-architecture Behavioral of Compteur is
24
-    signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
25
-begin
26
-    Dout <= aux;
27
-    process
28
-    begin
29
-        wait until CK'event and CK='1';
30
-        if RST = '0' then
31
-            aux <= (others => '0');
32
-        elsif LOAD = '1' then
33
-            aux <= Din;
34
-        elsif EN = '0' then
35
-            if SENS = '1' then
36
-                aux <= aux + 1;
37
-            else 
38
-                aux <= aux - 1;
39
-            end if;
40
-        end if;
41
-    end process;
42
-end Behavioral;

+ 0
- 45
Compteur8BitsBasys3.srcs/sources_1/new/System.vhd View File

@@ -1,66 +0,0 @@
1
-----------------------------------------------------------------------------------
2
-----------------------------------------------------------------------------------
3
-
4
-
5
-library IEEE;
6
-use IEEE.STD_LOGIC_1164.ALL;
7
-
8
---use IEEE.NUMERIC_STD.ALL;
9
-
10
---library UNISIM;
11
---use UNISIM.VComponents.all;
12
-
13
-entity System is
14
-    Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
15
-           btnL : in STD_LOGIC;
16
-           btnC : in STD_LOGIC;
17
-           btnR : in STD_LOGIC;
18
-           btnD : in STD_LOGIC;
19
-           LED : out STD_LOGIC_VECTOR (0 to 7);
20
-           CLK : in STD_LOGIC);
21
-end System;
22
-
23
-architecture Structural of System is
24
-
25
-    component ClockDivider1000
26
-        Port ( clk_in : in STD_LOGIC;
27
-               clk_out : out STD_LOGIC);
28
-    end component;
29
-    
30
-    component Compteur
31
-        Port ( CK : in STD_LOGIC;
32
-               RST : in STD_LOGIC;
33
-               SENS : in STD_LOGIC;
34
-               LOAD : in STD_LOGIC;
35
-               EN : in STD_LOGIC;
36
-               Din : in STD_LOGIC_VECTOR (7 downto 0);
37
-               Dout : out STD_LOGIC_VECTOR (7 downto 0));
38
-    end component;
39
-    
40
-    signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
41
-begin
42
-    DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
43
-    DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
44
-    CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
45
-end Structural;

+ 0
- 166
Compteur8BitsBasys3.xpr View File

@@ -1,166 +0,0 @@
1
-<?xml version="1.0" encoding="UTF-8"?>
2
-<!-- Product Version: Vivado v2016.4 (64-bit)              -->
3
-<!--                                                         -->
4
-<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5
-
6
-<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr">
7
-  <DefaultLaunch Dir="$PRUNDIR"/>
8
-  <Configuration>
9
-    <Option Name="Id" Val="b3843060a8224f8699d89033689dec00"/>
10
-    <Option Name="Part" Val="xc7a35tcpg236-1"/>
11
-    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12
-    <Option Name="CompiledLibDirXSim" Val=""/>
13
-    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14
-    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15
-    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
-    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17
-    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18
-    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
19
-    <Option Name="TargetLanguage" Val="VHDL"/>
20
-    <Option Name="SimulatorLanguage" Val="VHDL"/>
21
-    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
22
-    <Option Name="ActiveSimSet" Val="sim_1"/>
23
-    <Option Name="DefaultLib" Val="xil_defaultlib"/>
24
-    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
25
-    <Option Name="IPCachePermission" Val="read"/>
26
-    <Option Name="IPCachePermission" Val="write"/>
27
-    <Option Name="EnableCoreContainer" Val="FALSE"/>
28
-    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
29
-    <Option Name="IPUserFilesDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files"/>
30
-    <Option Name="IPStaticSourceDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files/ipstatic"/>
31
-    <Option Name="EnableBDX" Val="FALSE"/>
32
-    <Option Name="DSABoardId" Val="basys3"/>
33
-    <Option Name="DSANumComputeUnits" Val="16"/>
34
-    <Option Name="WTXSimLaunchSim" Val="0"/>
35
-    <Option Name="WTModelSimLaunchSim" Val="0"/>
36
-    <Option Name="WTQuestaLaunchSim" Val="0"/>
37
-    <Option Name="WTIesLaunchSim" Val="0"/>
38
-    <Option Name="WTVcsLaunchSim" Val="0"/>
39
-    <Option Name="WTRivieraLaunchSim" Val="0"/>
40
-    <Option Name="WTActivehdlLaunchSim" Val="0"/>
41
-    <Option Name="WTXSimExportSim" Val="0"/>
42
-    <Option Name="WTModelSimExportSim" Val="0"/>
43
-    <Option Name="WTQuestaExportSim" Val="0"/>
44
-    <Option Name="WTIesExportSim" Val="0"/>
45
-    <Option Name="WTVcsExportSim" Val="0"/>
46
-    <Option Name="WTRivieraExportSim" Val="0"/>
47
-    <Option Name="WTActivehdlExportSim" Val="0"/>
48
-    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
49
-    <Option Name="XSimRadix" Val="hex"/>
50
-    <Option Name="XSimTimeUnit" Val="ns"/>
51
-    <Option Name="XSimArrayDisplayLimit" Val="64"/>
52
-    <Option Name="XSimTraceLimit" Val="65536"/>
53
-  </Configuration>
54
-  <FileSets Version="1" Minor="31">
55
-    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
56
-      <Filter Type="Srcs"/>
57
-      <File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
58
-        <FileInfo>
59
-          <Attr Name="UsedIn" Val="synthesis"/>
60
-          <Attr Name="UsedIn" Val="simulation"/>
61
-        </FileInfo>
62
-      </File>
63
-      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
64
-        <FileInfo>
65
-          <Attr Name="UsedIn" Val="synthesis"/>
66
-          <Attr Name="UsedIn" Val="simulation"/>
67
-        </FileInfo>
68
-      </File>
69
-      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
70
-        <FileInfo>
71
-          <Attr Name="UsedIn" Val="synthesis"/>
72
-          <Attr Name="UsedIn" Val="simulation"/>
73
-        </FileInfo>
74
-      </File>
75
-      <File Path="$PSRCDIR/sources_1/new/System.vhd">
76
-        <FileInfo>
77
-          <Attr Name="UsedIn" Val="synthesis"/>
78
-          <Attr Name="UsedIn" Val="simulation"/>
79
-        </FileInfo>
80
-      </File>
81
-      <Config>
82
-        <Option Name="DesignMode" Val="RTL"/>
83
-        <Option Name="TopModule" Val="System"/>
84
-        <Option Name="TopAutoSet" Val="TRUE"/>
85
-      </Config>
86
-    </FileSet>
87
-    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
88
-      <Filter Type="Constrs"/>
89
-      <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
90
-        <FileInfo>
91
-          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
92
-          <Attr Name="ImportTime" Val="1614979917"/>
93
-          <Attr Name="UsedIn" Val="synthesis"/>
94
-          <Attr Name="UsedIn" Val="implementation"/>
95
-        </FileInfo>
96
-      </File>
97
-      <Config>
98
-        <Option Name="ConstrsType" Val="XDC"/>
99
-      </Config>
100
-    </FileSet>
101
-    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
102
-      <Filter Type="Srcs"/>
103
-      <File Path="$PSRCDIR/sim_1/new/test_Compteur.vhd">
104
-        <FileInfo>
105
-          <Attr Name="AutoDisabled" Val="1"/>
106
-          <Attr Name="UsedIn" Val="synthesis"/>
107
-          <Attr Name="UsedIn" Val="simulation"/>
108
-        </FileInfo>
109
-      </File>
110
-      <Config>
111
-        <Option Name="DesignMode" Val="RTL"/>
112
-        <Option Name="TopModule" Val="System"/>
113
-        <Option Name="TopLib" Val="xil_defaultlib"/>
114
-        <Option Name="TopAutoSet" Val="TRUE"/>
115
-        <Option Name="TransportPathDelay" Val="0"/>
116
-        <Option Name="TransportIntDelay" Val="0"/>
117
-        <Option Name="SimMode" Val="post-implementation"/>
118
-        <Option Name="SrcSet" Val="sources_1"/>
119
-      </Config>
120
-    </FileSet>
121
-  </FileSets>
122
-  <Simulators>
123
-    <Simulator Name="XSim">
124
-      <Option Name="Description" Val="Vivado Simulator"/>
125
-      <Option Name="CompiledLib" Val="0"/>
126
-    </Simulator>
127
-    <Simulator Name="ModelSim">
128
-      <Option Name="Description" Val="ModelSim Simulator"/>
129
-    </Simulator>
130
-    <Simulator Name="Questa">
131
-      <Option Name="Description" Val="Questa Advanced Simulator"/>
132
-    </Simulator>
133
-    <Simulator Name="Riviera">
134
-      <Option Name="Description" Val="Riviera-PRO Simulator"/>
135
-    </Simulator>
136
-    <Simulator Name="ActiveHDL">
137
-      <Option Name="Description" Val="Active-HDL Simulator"/>
138
-    </Simulator>
139
-  </Simulators>
140
-  <Runs Version="1" Minor="10">
141
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
142
-      <Strategy Version="1" Minor="2">
143
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
144
-        <Step Id="synth_design"/>
145
-      </Strategy>
146
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
147
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
148
-    </Run>
149
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
150
-      <Strategy Version="1" Minor="2">
151
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
152
-        <Step Id="init_design"/>
153
-        <Step Id="opt_design"/>
154
-        <Step Id="power_opt_design"/>
155
-        <Step Id="place_design"/>
156
-        <Step Id="post_place_power_opt_design"/>
157
-        <Step Id="phys_opt_design"/>
158
-        <Step Id="route_design"/>
159
-        <Step Id="post_route_phys_opt_design"/>
160
-        <Step Id="write_bitstream"/>
161
-      </Strategy>
162
-      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
163
-      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
164
-    </Run>
165
-  </Runs>
166
-</Project>

+ 5
- 0
README.md View File

@@ -0,0 +1,5 @@
1
+# Basys 3 GPIO <!-- Replace this line with the project name -->
2
+Created for Vivado 2016.4
3
+
4
+[Link to the project wiki](https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-general-io/start)
5
+

+ 0
- 0
hw_handoff/.keep View File


+ 22
- 0
proj/cleanup.cmd View File

@@ -0,0 +1,22 @@
1
+@echo off
2
+rem delete all files from subfolders
3
+for /d /r %%i in (*) do del /f /q %%i\*
4
+rem delete all subfolders
5
+for /d %%i in (*) do rd /S /Q %%i
6
+
7
+rem unmark read only from all files
8
+attrib -R .\* /S
9
+
10
+rem mark read only those we wish to keep
11
+attrib +R .\create_project.tcl
12
+attrib +R .\cleanup.sh
13
+attrib +R .\cleanup.cmd
14
+attrib +R .\release.py
15
+attrib +R .\.gitignore
16
+attrib +R .\_READ_ME_.txt
17
+
18
+rem delete all non read-only
19
+del /Q /A:-R .\*
20
+
21
+rem unmark read-only
22
+attrib -R .\*

+ 16
- 0
proj/cleanup.sh View File

@@ -0,0 +1,16 @@
1
+# This script is useful for cleaning up the 'project'
2
+# directory of a Digilent Vivado-project git repository
3
+###
4
+# Run the following command to change permissions of
5
+# this 'cleanup' file if needed:
6
+# chmod u+x cleanup.sh
7
+###
8
+# Remove directories/subdirectories
9
+find . -mindepth 1 -type d -exec rm -rf {} +
10
+# Remove any other files than:
11
+find . -type f ! -name 'cleanup.sh' \
12
+               ! -name 'cleanup.cmd' \
13
+               ! -name 'create_project.tcl' \
14
+               ! -name 'release.py' \
15
+               ! -name '.gitignore' \
16
+               -exec rm -rf {} +

+ 160
- 0
proj/create_project.tcl View File

@@ -0,0 +1,160 @@
1
+# Run this script to create the Vivado project files NEXT TO THIS script
2
+# If ::create_path global variable is set, the project is created under that path instead of the working dir
3
+
4
+# Project specific settings. These must be updated for each project.
5
+set proj_name "GPIO"
6
+
7
+if {[info exists ::create_path]} {
8
+	set dest_dir $::create_path
9
+} else {
10
+	set dest_dir [file normalize [file dirname [info script]]]
11
+}
12
+puts "INFO: Creating new project in $dest_dir"
13
+cd $dest_dir
14
+
15
+
16
+
17
+set part "xc7a35tcpg236-1"
18
+set brd_part "digilentinc.com:basys3:part0:1.1"
19
+
20
+# Set the reference directory for source file relative paths (by default the value is script directory path)
21
+set origin_dir ".."
22
+
23
+# Set the directory path for the original project from where this script was exported
24
+set orig_proj_dir "[file normalize "$origin_dir/proj"]"
25
+
26
+set src_dir $origin_dir/src
27
+set repo_dir $origin_dir/repo
28
+
29
+# # Set the board repo
30
+# # Uncomment if distributing board files with project in the "repo/board_files" folder.
31
+# # This is currently untested. It intends to also keep any existing board repo paths, since this is a global Vivado setting (not project specific.
32
+# # Ideally, if the project is closed, and then a new project is created (without closing Vivado), this should still be able to see a board repo specified in init.tcl.
33
+#set_param board.repoPaths "[file normalize "$repo_dir/board_files"]"
34
+
35
+# Create project
36
+create_project $proj_name $dest_dir
37
+
38
+# Set the directory path for the new project
39
+set proj_dir [get_property directory [current_project]]
40
+
41
+# Set project properties
42
+set obj [get_projects $proj_name]
43
+set_property "default_lib" "xil_defaultlib" $obj
44
+set_property "part" $part $obj
45
+set_property "board_part" $brd_part $obj
46
+set_property "simulator_language" "Mixed" $obj
47
+set_property "target_language" "VHDL" $obj
48
+
49
+# Uncomment the following 3 lines to greatly increase build speed while working with IP cores (and/or block diagrams)
50
+set_property "corecontainer.enable" "0" $obj
51
+set_property "ip_cache_permissions" "read write" $obj
52
+set_property "ip_output_repo" "[file normalize "$origin_dir/repo/cache"]" $obj
53
+
54
+# Create 'sources_1' fileset (if not found)
55
+if {[string equal [get_filesets -quiet sources_1] ""]} {
56
+  create_fileset -srcset sources_1
57
+}
58
+
59
+# Create 'constrs_1' fileset (if not found)
60
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
61
+  create_fileset -constrset constrs_1
62
+}
63
+
64
+# Set IP repository paths
65
+set obj [get_filesets sources_1]
66
+set_property "ip_repo_paths" "[file normalize $repo_dir]" $obj
67
+
68
+# Refresh IP Repositories
69
+update_ip_catalog -rebuild
70
+
71
+# Add conventional sources
72
+add_files -quiet $src_dir/hdl
73
+
74
+# Add IPs
75
+# TODO: handle IP containers files
76
+add_files -quiet [glob -nocomplain ../src/ip/*/*.xci]
77
+
78
+# Add constraints
79
+add_files -fileset constrs_1 -quiet $src_dir/constraints
80
+
81
+# Create 'synth_1' run (if not found)
82
+if {[string equal [get_runs -quiet synth_1] ""]} {
83
+  create_run -name synth_1 -part $part -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
84
+} else {
85
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
86
+  set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
87
+}
88
+set obj [get_runs synth_1]
89
+set_property "part" $part $obj
90
+set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
91
+set_property "steps.synth_design.args.directive" "RuntimeOptimized" $obj
92
+set_property "steps.synth_design.args.fsm_extraction" "off" $obj
93
+
94
+# set the current synth run
95
+current_run -synthesis [get_runs synth_1]
96
+
97
+# Create 'impl_1' run (if not found)
98
+if {[string equal [get_runs -quiet impl_1] ""]} {
99
+  create_run -name impl_1 -part $part -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
100
+} else {
101
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
102
+  set_property flow "Vivado Implementation 2015" [get_runs impl_1]
103
+}
104
+set obj [get_runs impl_1]
105
+set_property "part" $part $obj
106
+set_property "steps.opt_design.args.directive" "RuntimeOptimized" $obj
107
+set_property "steps.place_design.args.directive" "RuntimeOptimized" $obj
108
+set_property "steps.route_design.args.directive" "RuntimeOptimized" $obj
109
+
110
+# set the current impl run
111
+current_run -implementation [get_runs impl_1]
112
+
113
+puts "INFO: Project created:$proj_name"
114
+
115
+# Comment the rest of this script if there is no block design
116
+# Note that this script currently only supports a single block diagram
117
+
118
+# Uncomment this if building the block diagram from a tcl
119
+# Create block design
120
+# source $origin_dir/src/bd/system.tcl
121
+
122
+# Uncomment this block if importing an existing block diagram project
123
+# Import block design if it exists
124
+set bd_list [glob -nocomplain $src_dir/bd/*/*.bd]
125
+if {[llength $bd_list] != 0} {
126
+  add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
127
+  open_bd_design [glob -nocomplain $src_dir/bd/*/*.bd]
128
+  set design_name [get_bd_designs]
129
+  set file "$origin_dir/src/bd/$design_name/$design_name.bd"
130
+  set file [file normalize $file]
131
+  set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
132
+  if { ![get_property "is_locked" $file_obj] } {
133
+    set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
134
+  }
135
+ 
136
+  # Generate the wrapper 
137
+  set design_name [get_bd_designs]
138
+  add_files -norecurse [make_wrapper -files [get_files $design_name.bd] -top -force]
139
+
140
+  set obj [get_filesets sources_1]
141
+  set_property "top" "${design_name}_wrapper" $obj
142
+}
143
+
144
+set sdk_dir $origin_dir/sdk
145
+
146
+set hw_list [glob -nocomplain $sdk_dir/*hw_platform*]
147
+if {[llength $hw_list] != 0} {
148
+  foreach hw_plat $hw_list {
149
+	file delete -force $hw_plat
150
+  }
151
+}
152
+
153
+set sdk_list [glob -nocomplain $sdk_dir/*]
154
+set sdk_list [lsearch -inline -all -not -exact $sdk_list "../sdk/.keep"]
155
+if {[llength $sdk_list] != 0} {
156
+	exec xsct -eval "setws -switch ../sdk; importproject ../sdk"
157
+}
158
+# 
159
+# 
160
+# puts "INFO: Block design ready: $design_name.bd"

+ 0
- 0
repo/cache/.keep View File


+ 0
- 0
repo/local/.keep View File


+ 0
- 0
sdk/.keep View File


+ 0
- 0
src/bd/.keep View File


+ 0
- 0
src/constraints/.keep View File


+ 361
- 0
src/constraints/Basys3_Master.xdc View File

@@ -0,0 +1,361 @@
1
+## This file is a general .xdc for the Basys3 rev B board
2
+## To use it in a project:
3
+## - uncomment the lines corresponding to used pins
4
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5
+
6
+# Clock signal
7
+#Bank = 34, Pin name = ,					Sch name = CLK100MHZ
8
+set_property PACKAGE_PIN W5 [get_ports CLK]
9
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
10
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK]
11
+
12
+# Switches
13
+set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
14
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
15
+set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
16
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
17
+set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
18
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
19
+set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
20
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
21
+set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
22
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
23
+set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
24
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
25
+set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
26
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
27
+set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
28
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
29
+set_property PACKAGE_PIN V2 [get_ports {SW[8]}]
30
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[8]}]
31
+set_property PACKAGE_PIN T3 [get_ports {SW[9]}]
32
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[9]}]
33
+set_property PACKAGE_PIN T2 [get_ports {SW[10]}]
34
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[10]}]
35
+set_property PACKAGE_PIN R3 [get_ports {SW[11]}]
36
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[11]}]
37
+set_property PACKAGE_PIN W2 [get_ports {SW[12]}]
38
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[12]}]
39
+set_property PACKAGE_PIN U1 [get_ports {SW[13]}]
40
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[13]}]
41
+set_property PACKAGE_PIN T1 [get_ports {SW[14]}]
42
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[14]}]
43
+set_property PACKAGE_PIN R2 [get_ports {SW[15]}]
44
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[15]}]
45
+
46
+
47
+# LEDs
48
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
49
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
50
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
51
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
52
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
53
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
54
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
55
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
56
+set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
57
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
58
+set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
59
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
60
+set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
61
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
62
+set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
63
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
64
+set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
65
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}]
66
+set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
67
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}]
68
+set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
69
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}]
70
+set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
71
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}]
72
+set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
73
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}]
74
+set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
75
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}]
76
+set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
77
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}]
78
+set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
79
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}]
80
+
81
+
82
+#7 segment display
83
+#Bank = 34, Pin name = ,						Sch name = CA
84
+set_property PACKAGE_PIN W7 [get_ports {SSEG_CA[0]}]
85
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[0]}]
86
+#Bank = 34, Pin name = ,					Sch name = CB
87
+set_property PACKAGE_PIN W6 [get_ports {SSEG_CA[1]}]
88
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[1]}]
89
+#Bank = 34, Pin name = ,					Sch name = CC
90
+set_property PACKAGE_PIN U8 [get_ports {SSEG_CA[2]}]
91
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[2]}]
92
+#Bank = 34, Pin name = ,						Sch name = CD
93
+set_property PACKAGE_PIN V8 [get_ports {SSEG_CA[3]}]
94
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[3]}]
95
+#Bank = 34, Pin name = ,						Sch name = CE
96
+set_property PACKAGE_PIN U5 [get_ports {SSEG_CA[4]}]
97
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[4]}]
98
+#Bank = 34, Pin name = ,						Sch name = CF
99
+set_property PACKAGE_PIN V5 [get_ports {SSEG_CA[5]}]
100
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[5]}]
101
+#Bank = 34, Pin name = ,						Sch name = CG
102
+set_property PACKAGE_PIN U7 [get_ports {SSEG_CA[6]}]
103
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[6]}]
104
+
105
+#Bank = 34, Pin name = ,						Sch name = DP
106
+set_property PACKAGE_PIN V7 [get_ports {SSEG_CA[7]}]
107
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_CA[7]}]
108
+
109
+#Bank = 34, Pin name = ,						Sch name = AN0
110
+set_property PACKAGE_PIN U2 [get_ports {SSEG_AN[0]}]
111
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[0]}]
112
+#Bank = 34, Pin name = ,						Sch name = AN1
113
+set_property PACKAGE_PIN U4 [get_ports {SSEG_AN[1]}]
114
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[1]}]
115
+#Bank = 34, Pin name = ,						Sch name = AN2
116
+set_property PACKAGE_PIN V4 [get_ports {SSEG_AN[2]}]
117
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[2]}]
118
+#Bank = 34, Pin name = ,					Sch name = AN3
119
+set_property PACKAGE_PIN W4 [get_ports {SSEG_AN[3]}]
120
+set_property IOSTANDARD LVCMOS33 [get_ports {SSEG_AN[3]}]
121
+
122
+
123
+#Buttons
124
+#Bank = 14, Pin name = ,					Sch name = BTNC
125
+set_property PACKAGE_PIN U18 [get_ports {BTN[4]}]
126
+set_property IOSTANDARD LVCMOS33 [get_ports {BTN[4]}]
127
+#Bank = 14, Pin name = ,					Sch name = BTNU
128
+set_property PACKAGE_PIN T18 [get_ports {BTN[0]}]
129
+set_property IOSTANDARD LVCMOS33 [get_ports {BTN[0]}]
130
+#Bank = 14, Pin name = ,	Sch name = BTNL
131
+set_property PACKAGE_PIN W19 [get_ports {BTN[1]}]
132
+set_property IOSTANDARD LVCMOS33 [get_ports {BTN[1]}]
133
+#Bank = 14, Pin name = ,							Sch name = BTNR
134
+set_property PACKAGE_PIN T17 [get_ports {BTN[2]}]
135
+set_property IOSTANDARD LVCMOS33 [get_ports {BTN[2]}]
136
+#Bank = 14, Pin name = ,					Sch name = BTND
137
+set_property PACKAGE_PIN U17 [get_ports {BTN[3]}]
138
+set_property IOSTANDARD LVCMOS33 [get_ports {BTN[3]}]
139
+
140
+
141
+
142
+##Pmod Header JA
143
+##Bank = 15, Pin name = IO_L1N_T0_AD0N_15,					Sch name = JA1
144
+#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]
145
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
146
+##Bank = 15, Pin name = IO_L5N_T0_AD9N_15,					Sch name = JA2
147
+#set_property PACKAGE_PIN F14 [get_ports {JA[1]}]
148
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
149
+##Bank = 15, Pin name = IO_L16N_T2_A27_15,					Sch name = JA3
150
+#set_property PACKAGE_PIN D17 [get_ports {JA[2]}]
151
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
152
+##Bank = 15, Pin name = IO_L16P_T2_A28_15,					Sch name = JA4
153
+#set_property PACKAGE_PIN E17 [get_ports {JA[3]}]
154
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
155
+##Bank = 15, Pin name = IO_0_15,								Sch name = JA7
156
+#set_property PACKAGE_PIN G13 [get_ports {JA[4]}]
157
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
158
+##Bank = 15, Pin name = IO_L20N_T3_A19_15,					Sch name = JA8
159
+#set_property PACKAGE_PIN C17 [get_ports {JA[5]}]
160
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
161
+##Bank = 15, Pin name = IO_L21N_T3_A17_15,					Sch name = JA9
162
+#set_property PACKAGE_PIN D18 [get_ports {JA[6]}]
163
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
164
+##Bank = 15, Pin name = IO_L21P_T3_DQS_15,					Sch name = JA10
165
+#set_property PACKAGE_PIN E18 [get_ports {JA[7]}]
166
+#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
167
+
168
+
169
+
170
+##Pmod Header JB
171
+##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15,				Sch name = JB1
172
+#set_property PACKAGE_PIN G14 [get_ports {JB[0]}]
173
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
174
+##Bank = 14, Pin name = IO_L13P_T2_MRCC_14,					Sch name = JB2
175
+#set_property PACKAGE_PIN P15 [get_ports {JB[1]}]
176
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
177
+##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14,			Sch name = JB3
178
+#set_property PACKAGE_PIN V11 [get_ports {JB[2]}]
179
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
180
+##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14,				Sch name = JB4
181
+#set_property PACKAGE_PIN V15 [get_ports {JB[3]}]
182
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
183
+##Bank = 15, Pin name = IO_25_15,							Sch name = JB7
184
+#set_property PACKAGE_PIN K16 [get_ports {JB[4]}]
185
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
186
+##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14,			Sch name = JB8
187
+#set_property PACKAGE_PIN R16 [get_ports {JB[5]}]
188
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
189
+##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14,				Sch name = JB9
190
+#set_property PACKAGE_PIN T9 [get_ports {JB[6]}]
191
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
192
+##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14,			Sch name = JB10
193
+#set_property PACKAGE_PIN U11 [get_ports {JB[7]}]
194
+#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
195
+
196
+
197
+
198
+##Pmod Header JC
199
+##Bank = 35, Pin name = IO_L23P_T3_35,						Sch name = JC1
200
+#set_property PACKAGE_PIN K2 [get_ports {JC[0]}]
201
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
202
+##Bank = 35, Pin name = IO_L6P_T0_35,						Sch name = JC2
203
+#set_property PACKAGE_PIN E7 [get_ports {JC[1]}]
204
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
205
+##Bank = 35, Pin name = IO_L22P_T3_35,						Sch name = JC3
206
+#set_property PACKAGE_PIN J3 [get_ports {JC[2]}]
207
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
208
+##Bank = 35, Pin name = IO_L21P_T3_DQS_35,					Sch name = JC4
209
+#set_property PACKAGE_PIN J4 [get_ports {JC[3]}]
210
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
211
+##Bank = 35, Pin name = IO_L23N_T3_35,						Sch name = JC7
212
+#set_property PACKAGE_PIN K1 [get_ports {JC[4]}]
213
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
214
+##Bank = 35, Pin name = IO_L5P_T0_AD13P_35,					Sch name = JC8
215
+#set_property PACKAGE_PIN E6 [get_ports {JC[5]}]
216
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
217
+##Bank = 35, Pin name = IO_L22N_T3_35,						Sch name = JC9
218
+#set_property PACKAGE_PIN J2 [get_ports {JC[6]}]
219
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
220
+##Bank = 35, Pin name = IO_L19P_T3_35,						Sch name = JC10
221
+#set_property PACKAGE_PIN G6 [get_ports {JC[7]}]
222
+#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
223
+
224
+
225
+##Pmod Header JXADC
226
+##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15,				Sch name = XADC1_P -> XA1_P
227
+#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}]
228
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
229
+##Bank = 15, Pin name = IO_L8P_T1_AD10P_15,					Sch name = XADC2_P -> XA2_P
230
+#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}]
231
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
232
+##Bank = 15, Pin name = IO_L7P_T1_AD2P_15,					Sch name = XADC3_P -> XA3_P
233
+#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}]
234
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
235
+##Bank = 15, Pin name = IO_L10P_T1_AD11P_15,					Sch name = XADC4_P -> XA4_P
236
+#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}]
237
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
238
+##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15,				Sch name = XADC1_N -> XA1_N
239
+#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}]
240
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
241
+##Bank = 15, Pin name = IO_L8N_T1_AD10N_15,					Sch name = XADC2_N -> XA2_N
242
+#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}]
243
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
244
+##Bank = 15, Pin name = IO_L7N_T1_AD2N_15,					Sch name = XADC3_N -> XA3_N
245
+#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}]
246
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
247
+##Bank = 15, Pin name = IO_L10N_T1_AD11N_15,					Sch name = XADC4_N -> XA4_N
248
+#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}]
249
+#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
250
+
251
+
252
+
253
+#VGA Connector
254
+#Bank = 14, Pin name = ,					Sch name = VGA_R0
255
+set_property PACKAGE_PIN G19 [get_ports {VGA_RED[0]}]
256
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RED[0]}]
257
+#Bank = 14, Pin name = ,					Sch name = VGA_R1
258
+set_property PACKAGE_PIN H19 [get_ports {VGA_RED[1]}]
259
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RED[1]}]
260
+#Bank = 14, Pin name = ,					Sch name = VGA_R2
261
+set_property PACKAGE_PIN J19 [get_ports {VGA_RED[2]}]
262
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RED[2]}]
263
+#Bank = 14, Pin name = ,					Sch name = VGA_R3
264
+set_property PACKAGE_PIN N19 [get_ports {VGA_RED[3]}]
265
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_RED[3]}]
266
+#Bank = 14, Pin name = ,					Sch name = VGA_B0
267
+set_property PACKAGE_PIN N18 [get_ports {VGA_BLUE[0]}]
268
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_BLUE[0]}]
269
+#Bank = 14, Pin name = ,						Sch name = VGA_B1
270
+set_property PACKAGE_PIN L18 [get_ports {VGA_BLUE[1]}]
271
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_BLUE[1]}]
272
+#Bank = 14, Pin name = ,					Sch name = VGA_B2
273
+set_property PACKAGE_PIN K18 [get_ports {VGA_BLUE[2]}]
274
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_BLUE[2]}]
275
+#Bank = 14, Pin name = ,						Sch name = VGA_B3
276
+set_property PACKAGE_PIN J18 [get_ports {VGA_BLUE[3]}]
277
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_BLUE[3]}]
278
+#Bank = 14, Pin name = ,					Sch name = VGA_G0
279
+set_property PACKAGE_PIN J17 [get_ports {VGA_GREEN[0]}]
280
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_GREEN[0]}]
281
+#Bank = 14, Pin name = ,				Sch name = VGA_G1
282
+set_property PACKAGE_PIN H17 [get_ports {VGA_GREEN[1]}]
283
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_GREEN[1]}]
284
+#Bank = 14, Pin name = ,					Sch name = VGA_G2
285
+set_property PACKAGE_PIN G17 [get_ports {VGA_GREEN[2]}]
286
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_GREEN[2]}]
287
+#Bank = 14, Pin name = ,				Sch name = VGA_G3
288
+set_property PACKAGE_PIN D17 [get_ports {VGA_GREEN[3]}]
289
+set_property IOSTANDARD LVCMOS33 [get_ports {VGA_GREEN[3]}]
290
+#Bank = 14, Pin name = ,						Sch name = VGA_HS
291
+set_property PACKAGE_PIN P19 [get_ports VGA_HS]
292
+set_property IOSTANDARD LVCMOS33 [get_ports VGA_HS]
293
+#Bank = 14, Pin name = ,				Sch name = VGA_VS
294
+set_property PACKAGE_PIN R19 [get_ports VGA_VS]
295
+set_property IOSTANDARD LVCMOS33 [get_ports VGA_VS]
296
+
297
+
298
+##USB-RS232 Interface
299
+##Bank = 16, Pin name = ,					Sch name = UART_TXD_IN
300
+#set_property PACKAGE_PIN B18 [get_ports RsRx]
301
+#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
302
+#Bank = 16, Pin name = ,					Sch name = UART_RXD_OUT
303
+set_property PACKAGE_PIN A18 [get_ports UART_TXD]
304
+set_property IOSTANDARD LVCMOS33 [get_ports UART_TXD]
305
+
306
+
307
+
308
+#USB HID (PS/2)
309
+#Bank = 16, Pin name = ,					Sch name = PS2_CLK
310
+set_property PACKAGE_PIN C17 [get_ports PS2_CLK]
311
+set_property IOSTANDARD LVCMOS33 [get_ports PS2_CLK]
312
+set_property PULLUP true [get_ports PS2_CLK]
313
+#Bank = 16, Pin name = ,					Sch name = PS2_DATA
314
+set_property PACKAGE_PIN B17 [get_ports PS2_DATA]
315
+set_property IOSTANDARD LVCMOS33 [get_ports PS2_DATA]
316
+set_property PULLUP true [get_ports PS2_DATA]
317
+
318
+
319
+
320
+##Quad SPI Flash
321
+##Bank = CONFIG, Pin name = CCLK_0,							Sch name = QSPI_SCK
322
+#set_property PACKAGE_PIN C11 [get_ports {QspiSCK}]
323
+#set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}]
324
+##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14,			Sch name = QSPI_DQ0
325
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
326
+#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
327
+##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14,			Sch name = QSPI_DQ1
328
+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
329
+#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
330
+##Bank = CONFIG, Pin name = IO_L20_T0_D02_14,				Sch name = QSPI_DQ2
331
+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
332
+#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
333
+##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14,				Sch name = QSPI_DQ3
334
+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
335
+#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
336
+##Bank = CONFIG, Pin name = IO_L6P_T0_FCS_B_14,	Sch name = QSPI_CS
337
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
338
+#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
339
+
340
+
341
+
342
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
343
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
344
+set_property CONFIG_MODE SPIx4 [current_design]
345
+
346
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
347
+
348
+set_property CONFIG_VOLTAGE 3.3 [current_design]
349
+set_property CFGBVS VCCO [current_design]
350
+
351
+
352
+
353
+
354
+
355
+
356
+
357
+
358
+
359
+
360
+
361
+

+ 0
- 0
src/hdl/.keep View File


+ 476
- 0
src/hdl/GPIO_Demo.vhd View File

@@ -0,0 +1,476 @@
1
+----------------------------------------------------------------------------
2
+--	GPIO_Demo.vhd -- Basys3 GPIO/UART Demonstration Project
3
+----------------------------------------------------------------------------
4
+-- Author:  Marshall Wingerson Adapted from Sam Bobrowicz
5
+--          Copyright 2013 Digilent, Inc.
6
+----------------------------------------------------------------------------
7
+--
8
+----------------------------------------------------------------------------
9
+--	The GPIO/UART Demo project demonstrates a simple usage of the Basys3's 
10
+--  GPIO and UART. The behavior is as follows:
11
+--
12
+--	      *The 16 User LEDs are tied to the 16 User Switches. While the center
13
+--			 User button is pressed, the LEDs are instead tied to GND
14
+--	      *The 7-Segment display counts from 0 to 9 on each of its 8
15
+--        digits. This count is reset when the center button is pressed.
16
+--        Also, single anodes of the 7-Segment display are blanked by
17
+--	       holding BTNU, BTNL, BTND, or BTNR. Holding the center button 
18
+--        blanks all the 7-Segment anodes.
19
+--       *An introduction message is sent across the UART when the device
20
+--        is finished being configured, and after the center User button
21
+--        is pressed.
22
+--       *A message is sent over UART whenever BTNU, BTNL, BTND, or BTNR is
23
+--        pressed.
24
+--       *Note that the center user button behaves as a user reset button
25
+--        and is referred to as such in the code comments below
26
+--       *A test pattern is displayed on the VGA port at 1280x1024 resolution.
27
+--        If a mouse is attached to the USB-HID port, a cursor can be moved
28
+--        around the pattern.
29
+--        
30
+--	All UART communication can be captured by attaching the UART port to a
31
+-- computer running a Terminal program with 9600 Baud Rate, 8 data bits, no 
32
+-- parity, and 1 stop bit.																
33
+----------------------------------------------------------------------------
34
+--
35
+----------------------------------------------------------------------------
36
+-- Revision History:
37
+--  08/08/2011(SamB): Created using Xilinx Tools 13.2
38
+--  08/27/2013(MarshallW): Modified for the Nexys4 with Xilinx ISE 14.4\
39
+--  		--added RGB and microphone
40
+--  7/22/2014(SamB): Modified for the Basys3 with Vivado 2014.2\
41
+--  		--Removed RGB and microphone
42
+----------------------------------------------------------------------------
43
+
44
+library IEEE;
45
+use IEEE.STD_LOGIC_1164.ALL;
46
+
47
+--The IEEE.std_logic_unsigned contains definitions that allow 
48
+--std_logic_vector types to be used with the + operator to instantiate a 
49
+--counter.
50
+use IEEE.std_logic_unsigned.all;
51
+
52
+entity GPIO_demo is
53
+    Port ( SW 			: in  STD_LOGIC_VECTOR (15 downto 0);
54
+           BTN 			: in  STD_LOGIC_VECTOR (4 downto 0);
55
+           CLK 			: in  STD_LOGIC;
56
+           LED 			: out  STD_LOGIC_VECTOR (15 downto 0);
57
+           SSEG_CA 		: out  STD_LOGIC_VECTOR (7 downto 0);
58
+           SSEG_AN 		: out  STD_LOGIC_VECTOR (3 downto 0);
59
+           UART_TXD 	: out  STD_LOGIC;
60
+           VGA_RED      : out  STD_LOGIC_VECTOR (3 downto 0);
61
+           VGA_BLUE     : out  STD_LOGIC_VECTOR (3 downto 0);
62
+           VGA_GREEN    : out  STD_LOGIC_VECTOR (3 downto 0);
63
+           VGA_VS       : out  STD_LOGIC;
64
+           VGA_HS       : out  STD_LOGIC;
65
+           PS2_CLK      : inout STD_LOGIC;
66
+           PS2_DATA     : inout STD_LOGIC
67
+			  );
68
+end GPIO_demo;
69
+
70
+architecture Behavioral of GPIO_demo is
71
+
72
+component UART_TX_CTRL
73
+Port(
74
+	SEND : in std_logic;
75
+	DATA : in std_logic_vector(7 downto 0);
76
+	CLK : in std_logic;          
77
+	READY : out std_logic;
78
+	UART_TX : out std_logic
79
+	);
80
+end component;
81
+
82
+component debouncer
83
+Generic(
84
+        DEBNC_CLOCKS : integer;
85
+        PORT_WIDTH : integer);
86
+Port(
87
+		SIGNAL_I : in std_logic_vector(4 downto 0);
88
+		CLK_I : in std_logic;          
89
+		SIGNAL_O : out std_logic_vector(4 downto 0)
90
+		);
91
+end component;
92
+
93
+component vga_ctrl
94
+    Port ( CLK_I : in STD_LOGIC;
95
+           VGA_HS_O : out STD_LOGIC;
96
+           VGA_VS_O : out STD_LOGIC;
97
+           VGA_RED_O : out STD_LOGIC_VECTOR (3 downto 0);
98
+           VGA_BLUE_O : out STD_LOGIC_VECTOR (3 downto 0);
99
+           VGA_GREEN_O : out STD_LOGIC_VECTOR (3 downto 0);
100
+           PS2_CLK      : inout STD_LOGIC;
101
+           PS2_DATA     : inout STD_LOGIC
102
+           );
103
+end component;
104
+
105
+
106
+--The type definition for the UART state machine type. Here is a description of what
107
+--occurs during each state:
108
+-- RST_REG     -- Do Nothing. This state is entered after configuration or a user reset.
109
+--                The state is set to LD_INIT_STR.
110
+-- LD_INIT_STR -- The Welcome String is loaded into the sendStr variable and the strIndex
111
+--                variable is set to zero. The welcome string length is stored in the StrEnd
112
+--                variable. The state is set to SEND_CHAR.
113
+-- SEND_CHAR   -- uartSend is set high for a single clock cycle, signaling the character
114
+--                data at sendStr(strIndex) to be registered by the UART_TX_CTRL at the next
115
+--                cycle. Also, strIndex is incremented (behaves as if it were post 
116
+--                incremented after reading the sendStr data). The state is set to RDY_LOW.
117
+-- RDY_LOW     -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go low, 
118
+--                indicating a send operation has begun. State is set to WAIT_RDY.
119
+-- WAIT_RDY    -- Do nothing. Wait for the READY signal from the UART_TX_CTRL to go high, 
120
+--                indicating a send operation has finished. If READY is high and strEnd = 
121
+--                StrIndex then state is set to WAIT_BTN, else if READY is high and strEnd /=
122
+--                StrIndex then state is set to SEND_CHAR.
123
+-- WAIT_BTN    -- Do nothing. Wait for a button press on BTNU, BTNL, BTND, or BTNR. If a 
124
+--                button press is detected, set the state to LD_BTN_STR.
125
+-- LD_BTN_STR  -- The Button String is loaded into the sendStr variable and the strIndex
126
+--                variable is set to zero. The button string length is stored in the StrEnd
127
+--                variable. The state is set to SEND_CHAR.
128
+type UART_STATE_TYPE is (RST_REG, LD_INIT_STR, SEND_CHAR, RDY_LOW, WAIT_RDY, WAIT_BTN, LD_BTN_STR);
129
+
130
+--The CHAR_ARRAY type is a variable length array of 8 bit std_logic_vectors. 
131
+--Each std_logic_vector contains an ASCII value and represents a character in
132
+--a string. The character at index 0 is meant to represent the first
133
+--character of the string, the character at index 1 is meant to represent the
134
+--second character of the string, and so on.
135
+type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
136
+
137
+constant TMR_CNTR_MAX : std_logic_vector(26 downto 0) := "101111101011110000100000000"; --100,000,000 = clk cycles per second
138
+constant TMR_VAL_MAX : std_logic_vector(3 downto 0) := "1001"; --9
139
+
140
+constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
141
+
142
+constant MAX_STR_LEN : integer := 27;
143
+
144
+constant WELCOME_STR_LEN : natural := 27;
145
+constant BTN_STR_LEN : natural := 24;
146
+
147
+--Welcome string definition. Note that the values stored at each index
148
+--are the ASCII values of the indicated character.
149
+constant WELCOME_STR : CHAR_ARRAY(0 to 26) := (X"0A",  --\n
150
+															  X"0D",  --\r
151
+															  X"42",  --B
152
+															  X"41",  --A
153
+															  X"53",  --S
154
+															  X"59",  --Y
155
+															  X"53",  --S
156
+															  X"33",  --3
157
+															  X"20",  -- 
158
+															  X"47",  --G
159
+															  X"50",  --P
160
+															  X"49",  --I
161
+															  X"4F",  --O
162
+															  X"2F",  --/
163
+															  X"55",  --U
164
+															  X"41",  --A
165
+															  X"52",  --R
166
+															  X"54",  --T
167
+															  X"20",  -- 
168
+															  X"44",  --D
169
+															  X"45",  --E
170
+															  X"4D",  --M
171
+															  X"4F",  --O
172
+															  X"21",  --!
173
+															  X"0A",  --\n
174
+															  X"0A",  --\n
175
+															  X"0D"); --\r
176
+															  
177
+--Button press string definition.
178
+constant BTN_STR : CHAR_ARRAY(0 to 23) :=     (X"42",  --B
179
+															  X"75",  --u
180
+															  X"74",  --t
181
+															  X"74",  --t
182
+															  X"6F",  --o
183
+															  X"6E",  --n
184
+															  X"20",  -- 
185
+															  X"70",  --p
186
+															  X"72",  --r
187
+															  X"65",  --e
188
+															  X"73",  --s
189
+															  X"73",  --s
190
+															  X"20",  --
191
+															  X"64",  --d
192
+															  X"65",  --e
193
+															  X"74",  --t
194
+															  X"65",  --e
195
+															  X"63",  --c
196
+															  X"74",  --t
197
+															  X"65",  --e
198
+															  X"64",  --d
199
+															  X"21",  --!
200
+															  X"0A",  --\n
201
+															  X"0D"); --\r
202
+
203
+--This is used to determine when the 7-segment display should be
204
+--incremented
205
+signal tmrCntr : std_logic_vector(26 downto 0) := (others => '0');
206
+
207
+--This counter keeps track of which number is currently being displayed
208
+--on the 7-segment.
209
+signal tmrVal : std_logic_vector(3 downto 0) := (others => '0');
210
+
211
+--Contains the current string being sent over uart.
212
+signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1));
213
+
214
+--Contains the length of the current string being sent over uart.
215
+signal strEnd : natural;
216
+
217
+--Contains the index of the next character to be sent over uart
218
+--within the sendStr variable.
219
+signal strIndex : natural;
220
+
221
+--Used to determine when a button press has occured
222
+signal btnReg : std_logic_vector (3 downto 0) := "0000";
223
+signal btnDetect : std_logic;
224
+
225
+--UART_TX_CTRL control signals
226
+signal uartRdy : std_logic;
227
+signal uartSend : std_logic := '0';
228
+signal uartData : std_logic_vector (7 downto 0):= "00000000";
229
+signal uartTX : std_logic;
230
+
231
+--Current uart state signal
232
+signal uartState : UART_STATE_TYPE := RST_REG;
233
+
234
+--Debounced btn signals used to prevent single button presses
235
+--from being interpreted as multiple button presses.
236
+signal btnDeBnc : std_logic_vector(4 downto 0);
237
+
238
+signal clk_cntr_reg : std_logic_vector (4 downto 0) := (others=>'0'); 
239
+
240
+signal pwm_val_reg : std_logic := '0';
241
+
242
+--this counter counts the amount of time paused in the UART reset state
243
+signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
244
+
245
+begin
246
+
247
+----------------------------------------------------------
248
+------                LED Control                  -------
249
+----------------------------------------------------------
250
+
251
+with BTN(4) select
252
+	LED <= SW 			when '0',
253
+			 "0000000000000000" when others;
254
+			 			 
255
+----------------------------------------------------------
256
+------           7-Seg Display Control             -------
257
+----------------------------------------------------------
258
+--Digits are incremented every second, and are blanked in
259
+--response to button presses.
260
+
261
+--Individual and reset blanking of Anodes
262
+with BTN(4) select
263
+	SSEG_AN(3 downto 0) <= btnDeBnc(3 downto 0)	when '0',
264
+				  "1111" 			when others;	  			  
265
+
266
+--This process controls the counter that triggers the 7-segment
267
+--to be incremented. It counts 100,000,000 and then resets.		  
268
+timer_counter_process : process (CLK)
269
+begin
270
+	if (rising_edge(CLK)) then
271
+		if ((tmrCntr = TMR_CNTR_MAX) or (BTN(4) = '1')) then
272
+			tmrCntr <= (others => '0');
273
+		else
274
+			tmrCntr <= tmrCntr + 1;
275
+		end if;
276
+	end if;
277
+end process;
278
+
279
+--This process increments the digit being displayed on the 
280
+--7-segment display every second.
281
+timer_inc_process : process (CLK)
282
+begin
283
+	if (rising_edge(CLK)) then
284
+		if (BTN(4) = '1') then
285
+			tmrVal <= (others => '0');
286
+		elsif (tmrCntr = TMR_CNTR_MAX) then
287
+			if (tmrVal = TMR_VAL_MAX) then
288
+				tmrVal <= (others => '0');
289
+			else
290
+				tmrVal <= tmrVal + 1;
291
+			end if;
292
+		end if;
293
+	end if;
294
+end process;
295
+
296
+--This select statement encodes the value of tmrVal to the necessary
297
+--cathode signals to display it on the 7-segment
298
+with tmrVal select
299
+	SSEG_CA <= "01000000" when "0000",
300
+				  "01111001" when "0001",
301
+				  "00100100" when "0010",
302
+				  "00110000" when "0011",
303
+				  "00011001" when "0100",
304
+				  "00010010" when "0101",
305
+				  "00000010" when "0110",
306
+				  "01111000" when "0111",
307
+				  "00000000" when "1000",
308
+				  "00010000" when "1001",
309
+				  "11111111" when others;
310
+
311
+
312
+----------------------------------------------------------
313
+------              Button Control                 -------
314
+----------------------------------------------------------
315
+--Buttons are debounced and their rising edges are detected
316
+--to trigger UART messages
317
+
318
+
319
+--Debounces btn signals
320
+Inst_btn_debounce: debouncer 
321
+    generic map(
322
+        DEBNC_CLOCKS => (2**16),
323
+        PORT_WIDTH => 5)
324
+    port map(
325
+		SIGNAL_I => BTN,
326
+		CLK_I => CLK,
327
+		SIGNAL_O => btnDeBnc
328
+	);
329
+
330
+--Registers the debounced button signals, for edge detection.
331
+btn_reg_process : process (CLK)
332
+begin
333
+	if (rising_edge(CLK)) then
334
+		btnReg <= btnDeBnc(3 downto 0);
335
+	end if;
336
+end process;
337
+
338
+--btnDetect goes high for a single clock cycle when a btn press is
339
+--detected. This triggers a UART message to begin being sent.
340
+btnDetect <= '1' when ((btnReg(0)='0' and btnDeBnc(0)='1') or
341
+								(btnReg(1)='0' and btnDeBnc(1)='1') or
342
+								(btnReg(2)='0' and btnDeBnc(2)='1') or
343
+								(btnReg(3)='0' and btnDeBnc(3)='1')  ) else
344
+				  '0';
345
+				  
346
+
347
+
348
+
349
+----------------------------------------------------------
350
+------              UART Control                   -------
351
+----------------------------------------------------------
352
+--Messages are sent on reset and when a button is pressed.
353
+
354
+--This counter holds the UART state machine in reset for ~2 milliseconds. This
355
+--will complete transmission of any byte that may have been initiated during 
356
+--FPGA configuration due to the UART_TX line being pulled low, preventing a 
357
+--frame shift error from occuring during the first message.
358
+process(CLK)
359
+begin
360
+  if (rising_edge(CLK)) then
361
+    if ((reset_cntr = RESET_CNTR_MAX) or (uartState /= RST_REG)) then
362
+      reset_cntr <= (others=>'0');
363
+    else
364
+      reset_cntr <= reset_cntr + 1;
365
+    end if;
366
+  end if;
367
+end process;
368
+
369
+--Next Uart state logic (states described above)
370
+next_uartState_process : process (CLK)
371
+begin
372
+	if (rising_edge(CLK)) then
373
+		if (btnDeBnc(4) = '1') then
374
+			uartState <= RST_REG;
375
+		else	
376
+			case uartState is 
377
+			when RST_REG =>
378
+        if (reset_cntr = RESET_CNTR_MAX) then
379
+          uartState <= LD_INIT_STR;
380
+        end if;
381
+			when LD_INIT_STR =>
382
+				uartState <= SEND_CHAR;
383
+			when SEND_CHAR =>
384
+				uartState <= RDY_LOW;
385
+			when RDY_LOW =>
386
+				uartState <= WAIT_RDY;
387
+			when WAIT_RDY =>
388
+				if (uartRdy = '1') then
389
+					if (strEnd = strIndex) then
390
+						uartState <= WAIT_BTN;
391
+					else
392
+						uartState <= SEND_CHAR;
393
+					end if;
394
+				end if;
395
+			when WAIT_BTN =>
396
+				if (btnDetect = '1') then
397
+					uartState <= LD_BTN_STR;
398
+				end if;
399
+			when LD_BTN_STR =>
400
+				uartState <= SEND_CHAR;
401
+			when others=> --should never be reached
402
+				uartState <= RST_REG;
403
+			end case;
404
+		end if ;
405
+	end if;
406
+end process;
407
+
408
+--Loads the sendStr and strEnd signals when a LD state is
409
+--is reached.
410
+string_load_process : process (CLK)
411
+begin
412
+	if (rising_edge(CLK)) then
413
+		if (uartState = LD_INIT_STR) then
414
+			sendStr <= WELCOME_STR;
415
+			strEnd <= WELCOME_STR_LEN;
416
+		elsif (uartState = LD_BTN_STR) then
417
+			sendStr(0 to 23) <= BTN_STR;
418
+			strEnd <= BTN_STR_LEN;
419
+		end if;
420
+	end if;
421
+end process;
422
+
423
+--Conrols the strIndex signal so that it contains the index
424
+--of the next character that needs to be sent over uart
425
+char_count_process : process (CLK)
426
+begin
427
+	if (rising_edge(CLK)) then
428
+		if (uartState = LD_INIT_STR or uartState = LD_BTN_STR) then
429
+			strIndex <= 0;
430
+		elsif (uartState = SEND_CHAR) then
431
+			strIndex <= strIndex + 1;
432
+		end if;
433
+	end if;
434
+end process;
435
+
436
+--Controls the UART_TX_CTRL signals
437
+char_load_process : process (CLK)
438
+begin
439
+	if (rising_edge(CLK)) then
440
+		if (uartState = SEND_CHAR) then
441
+			uartSend <= '1';
442
+			uartData <= sendStr(strIndex);
443
+		else
444
+			uartSend <= '0';
445
+		end if;
446
+	end if;
447
+end process;
448
+
449
+--Component used to send a byte of data over a UART line.
450
+Inst_UART_TX_CTRL: UART_TX_CTRL port map(
451
+		SEND => uartSend,
452
+		DATA => uartData,
453
+		CLK => CLK,
454
+		READY => uartRdy,
455
+		UART_TX => uartTX 
456
+	);
457
+
458
+UART_TXD <= uartTX;
459
+
460
+
461
+----------------------------------------------------------
462
+------              VGA Control                    -------
463
+----------------------------------------------------------
464
+
465
+Inst_vga_ctrl: vga_ctrl port map(
466
+		CLK_I => CLK,
467
+		VGA_HS_O => VGA_HS,
468
+        VGA_VS_O => VGA_VS,
469
+		VGA_RED_O => VGA_RED,
470
+        VGA_BLUE_O => VGA_BLUE,
471
+        VGA_GREEN_O => VGA_GREEN,
472
+        PS2_CLK => PS2_CLK,
473
+        PS2_DATA => PS2_DATA
474
+	);
475
+
476
+end Behavioral;

+ 1169
- 0
src/hdl/MouseCtl.vhd
File diff suppressed because it is too large
View File


+ 269
- 0
src/hdl/MouseDisplay.vhd View File

@@ -0,0 +1,269 @@
1
+------------------------------------------------------------------------
2
+-- mouse_displayer.vhd
3
+------------------------------------------------------------------------
4
+-- Author : Ulrich Zoltán
5
+--          Copyright 2006 Digilent, Inc.
6
+------------------------------------------------------------------------
7
+-- Software version : Xilinx ISE 7.1.04i
8
+--                    WebPack
9
+-- Device	        : 3s200ft256-4
10
+------------------------------------------------------------------------
11
+-- This file contains the implementation of a mouse cursor.
12
+------------------------------------------------------------------------
13
+--  Behavioral description
14
+------------------------------------------------------------------------
15
+-- Mouse position is received from the mouse_controller, horizontal and
16
+-- vertical counters are received from vga_module and if the counters
17
+-- are inside the mouse cursor bounds, then the mouse is sent to the
18
+-- screen.
19
+-- The mouse display module can be also used as an overlay of the VGA 
20
+-- signal, also blanking the VGA screen, if the red_in, green_in, blue_in 
21
+-- and the blank_in signals are used. 
22
+-- In this application the signals mentioned and their corresponding code 
23
+-- lines are commented, therefore the mouse display module only generates 
24
+-- the RGB signals to display the cursor, and the VGA controller decides 
25
+-- whether or not to display the cursor.
26
+-- The mouse cursor is 16x16 pixels and uses 2 colors: white and black. 
27
+-- For the color encoding 2 bits are used to be able to use transparency. 
28
+-- The cursor is stored in a 256X2 bit distributed ram memory. If the current
29
+-- pixel of the mouse is "00" then output color is black, if "01" then is
30
+-- white and if "10" or "11" then the pixel is transparent and the input 
31
+-- R, G and B signals are passed to the output. 
32
+-- In this way, the mouse cursor will not be a 16x16 square, instead will 
33
+-- have an arrow shape.
34
+-- The memory address is composed from the difference of the vga counters
35
+-- and mouse position: xdiff is the difference on 4 bits (because cursor
36
+-- is 16 pixels width) between the horizontal vga counter and the xpos
37
+-- of the mouse. ydiff is the difference on 4 bits (because cursor
38
+-- has 16 pixels in height) between the vertical vga counter and the
39
+-- ypos of the mouse. By concatenating ydiff and xidff (in this order)
40
+-- the memory address of the current pixel is obtained.
41
+-- A distributed memory implementation is forced by the attributes, to save 
42
+-- BRAM resources.
43
+-- If the blank input from the vga_module is active, this means that current
44
+-- pixel is not inside visible screen and color outputs are set to black
45
+------------------------------------------------------------------------
46
+--  Port definitions
47
+------------------------------------------------------------------------
48
+-- pixel_clk      - input pin, representing the pixel clock, used
49
+--                - by the vga_controller for the currently used
50
+--                - resolution, generated by a dcm. 25MHz for 640x480,
51
+--                - 40MHz for 800x600 and 108 MHz for 1280x1024. 
52
+--                - This clock is used to read pixels from memory 
53
+--                - and output data on color outputs.
54
+-- xpos           - input pin, 10 bits, from mouse_controller
55
+--                - the x position of the mouse relative to the upper
56
+--                - left corner
57
+-- ypos           - input pin, 10 bits, from mouse_controller
58
+--                - the y position of the mouse relative to the upper
59
+--                - left corner
60
+-- hcount         - input pin, 11 bits, from vga_module
61
+--                - the horizontal counter from the vga_controller
62
+--                - tells the horizontal position of the current pixel
63
+--                - on the screen from left to right.
64
+-- vcount         - input pin, 11 bits, from vga_module
65
+--                - the vertical counter from the vga_controller
66
+--                - tells the vertical position of the currentl pixel
67
+--                - on the screen from top to bottom.
68
+-- red_out        - output pin, 4 bits, to vga hardware module.
69
+--                - red output channel
70
+-- green_out      - output pin, 4 bits, to vga hardware module.
71
+--                - green output channel
72
+-- blue_out       - output pin, 4 bits, to vga hardware module.
73
+--                - blue output channel
74
+
75
+------------------- Signals used when the mouse display is in overlay mode
76
+
77
+-- blank          - input pin, from vga_module
78
+--                - if active, current pixel is not in visible area,
79
+--                - and color outputs should be set on 0.
80
+-- red_in         - input pin, 4 bits, from effects_layer
81
+--                - red channel input of the image to be displayed
82
+-- green_in       - input pin, 4 bits, from effects_layer
83
+--                - green channel input of the image to be displayed
84
+-- blue_in        - input pin, 4 bits, from effects_layer
85
+--                - blue channel input of the image to be displayed
86
+------------------------------------------------------------------------
87
+
88
+library IEEE;
89
+use IEEE.STD_LOGIC_1164.ALL;
90
+use IEEE.STD_LOGIC_ARITH.ALL;
91
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
92
+
93
+-- simulation library
94
+--library UNISIM;
95
+--use UNISIM.VComponents.all;
96
+
97
+-- the mouse_displayer entity declaration
98
+-- read above for behavioral description and port definitions.
99
+entity MouseDisplay is
100
+port (
101
+   pixel_clk: in std_logic;
102
+   xpos     : in std_logic_vector(11 downto 0);
103
+   ypos     : in std_logic_vector(11 downto 0);
104
+
105
+   hcount   : in std_logic_vector(11 downto 0);
106
+   vcount   : in std_logic_vector(11 downto 0);
107
+   --blank    : in std_logic; -- if VGA blank is used
108
+
109
+   --red_in   : in std_logic_vector(3 downto 0); -- if VGA signal pass-through is used
110
+   --green_in : in std_logic_vector(3 downto 0);
111
+   --blue_in  : in std_logic_vector(3 downto 0);
112
+   
113
+   enable_mouse_display_out : out std_logic;
114
+
115
+   red_out  : out std_logic_vector(3 downto 0);
116
+   green_out: out std_logic_vector(3 downto 0);
117
+   blue_out : out std_logic_vector(3 downto 0)
118
+);
119
+
120
+-- force synthesizer to extract distributed ram for the
121
+-- displayrom signal, and not a block ram, to save BRAM resources.
122
+attribute rom_extract : string;
123
+attribute rom_extract of MouseDisplay: entity is "yes";
124
+attribute rom_style : string;
125
+attribute rom_style of MouseDisplay: entity is "distributed";
126
+
127
+end MouseDisplay;
128
+
129
+architecture Behavioral of MouseDisplay is
130
+
131
+------------------------------------------------------------------------
132
+-- CONSTANTS
133
+------------------------------------------------------------------------
134
+
135
+type displayrom is array(0 to 255) of std_logic_vector(1 downto 0);
136
+-- the memory that holds the cursor.
137
+-- 00 - black
138
+-- 01 - white
139
+-- 1x - transparent
140
+
141
+constant mouserom: displayrom := (
142
+"00","00","11","11","11","11","11","11","11","11","11","11","11","11","11","11",
143
+"00","01","00","11","11","11","11","11","11","11","11","11","11","11","11","11",
144
+"00","01","01","00","11","11","11","11","11","11","11","11","11","11","11","11",
145
+"00","01","01","01","00","11","11","11","11","11","11","11","11","11","11","11",
146
+"00","01","01","01","01","00","11","11","11","11","11","11","11","11","11","11",
147
+"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
148
+"00","01","01","01","01","01","01","00","11","11","11","11","11","11","11","11",
149
+"00","01","01","01","01","01","01","01","00","11","11","11","11","11","11","11",
150
+"00","01","01","01","01","01","00","00","00","00","11","11","11","11","11","11",
151
+"00","01","01","01","01","01","00","11","11","11","11","11","11","11","11","11",
152
+"00","01","00","00","01","01","00","11","11","11","11","11","11","11","11","11",
153
+"00","00","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
154
+"00","11","11","11","00","01","01","00","11","11","11","11","11","11","11","11",
155
+"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
156
+"11","11","11","11","11","00","01","01","00","11","11","11","11","11","11","11",
157
+"11","11","11","11","11","11","00","00","11","11","11","11","11","11","11","11"
158
+);
159
+
160
+-- width and height of cursor.
161
+constant OFFSET: std_logic_vector(4 downto 0) := "10000";   -- 16
162
+
163
+------------------------------------------------------------------------
164
+-- SIGNALS
165
+------------------------------------------------------------------------
166
+
167
+-- pixel from the display memory, representing currently displayed
168
+-- pixel of the cursor, if the cursor is being display at this point
169
+signal mousepixel: std_logic_vector(1 downto 0) := (others => '0');
170
+-- when high, enables displaying of the cursor, and reading the
171
+-- cursor memory.
172
+signal enable_mouse_display: std_logic := '0';
173
+
174
+-- difference in range 0-15 between the vga counters and mouse position
175
+signal xdiff: std_logic_vector(3 downto 0) := (others => '0');
176
+signal ydiff: std_logic_vector(3 downto 0) := (others => '0');
177
+
178
+signal red_int  : std_logic_vector(3 downto 0);
179
+signal green_int: std_logic_vector(3 downto 0);
180
+signal blue_int : std_logic_vector(3 downto 0);
181
+
182
+signal red_int1  : std_logic_vector(3 downto 0);
183
+signal green_int1: std_logic_vector(3 downto 0);
184
+signal blue_int1 : std_logic_vector(3 downto 0);
185
+
186
+begin
187
+
188
+   -- compute xdiff
189
+   x_diff: process(hcount, xpos)
190
+   variable temp_diff: std_logic_vector(11 downto 0) := (others => '0');
191
+   begin
192
+         temp_diff := hcount - xpos;
193
+         xdiff <= temp_diff(3 downto 0);
194
+   end process x_diff;
195
+
196
+   -- compute ydiff
197
+   y_diff: process(vcount, xpos)
198
+   variable temp_diff: std_logic_vector(11 downto 0) := (others => '0');
199
+   begin
200
+         temp_diff := vcount - ypos;
201
+         ydiff <= temp_diff(3 downto 0);
202
+   end process y_diff;
203
+
204
+ -- read pixel from memory at address obtained by concatenation of
205
+   -- ydiff and xdiff
206
+   mousepixel <= mouserom(conv_integer(ydiff & xdiff))
207
+                 when rising_edge(pixel_clk);
208
+
209
+   -- set enable_mouse_display high if vga counters inside cursor block
210
+   enable_mouse: process(pixel_clk, hcount, vcount, xpos, ypos)
211
+   begin
212
+      if(rising_edge(pixel_clk)) then
213
+         if(hcount >= xpos +X"001" and hcount < (xpos + OFFSET - X"001") and
214
+            vcount >= ypos and vcount < (ypos + OFFSET)) and
215
+            (mousepixel = "00" or mousepixel = "01")
216
+         then
217
+            enable_mouse_display <= '1';
218
+         else
219
+            enable_mouse_display <= '0';
220
+         end if;
221
+      end if;
222
+   end process enable_mouse;
223
+   
224
+enable_mouse_display_out <= enable_mouse_display;
225
+
226
+   -- if cursor display is enabled, then, according to pixel
227
+   -- value, set the output color channels.
228
+ process(pixel_clk)
229
+   begin
230
+      if(rising_edge(pixel_clk)) then
231
+         -- if in visible screen
232
+--       if(blank = '0') then
233
+            -- in display is enabled
234
+            if(enable_mouse_display = '1') then
235
+               -- white pixel of cursor
236
+               if(mousepixel = "01") then
237
+                  red_out <= (others => '1');
238
+                  green_out <= (others => '1');
239
+                  blue_out <= (others => '1');
240
+               -- black pixel of cursor
241
+               elsif(mousepixel = "00") then
242
+                  red_out <= (others => '0');
243
+                  green_out <= (others => '0');
244
+                  blue_out <= (others => '0');
245
+               -- transparent pixel of cursor
246
+               -- let input pass to output
247
+--               else
248
+--                  red_out <= red_in;
249
+--                  green_out <= green_in;
250
+--                  blue_out <= blue_in;
251
+               end if;
252
+            -- cursor display is not enabled
253
+            -- let input pass to output.
254
+--          else
255
+--               red_out <= red_in;
256
+--               green_out <= green_in;
257
+--               blue_out <= blue_in;
258
+            end if;
259
+         -- not in visible screen, black outputs.
260
+--       else
261
+--            red_out <= (others => '0');
262
+--            green_out <= (others => '0');
263
+--            blue_out <= (others => '0');
264
+--      end if;
265
+      end if;
266
+   end process;
267
+
268
+
269
+end Behavioral;

+ 807
- 0
src/hdl/Ps2Interface.vhd View File

@@ -0,0 +1,807 @@
1
+------------------------------------------------------------------------
2
+-- ps2interface.vhd
3
+------------------------------------------------------------------------
4
+-- Author : Ulrich Zoltán
5
+--          Copyright 2006 Digilent, Inc.
6
+------------------------------------------------------------------------
7
+-- This file contains the implementation of a generic bidirectional
8
+-- ps/2 interface.
9
+------------------------------------------------------------------------
10
+--  Behavioral description
11
+------------------------------------------------------------------------
12
+-- Please read the following article on the web for understanding how
13
+-- the ps/2 protocol works.
14
+-- http://www.computer-engineering.org/ps2protocol/
15
+
16
+-- This module implements a generic bidirectional ps/2 interface. It can
17
+-- be used with any ps/2 compatible device. It offers its clients a
18
+-- convenient way to exchange data with the device. The interface
19
+-- transparently wraps the byte to be sent into a ps/2 frame, generates
20
+-- parity for byte and sends the frame one bit at a time to the device.
21
+-- Similarly, when receiving data from the ps2 device, the interface
22
+-- receives the frame, checks for parity, and extract the usefull data
23
+-- and forwards it to the client. If an error occurs during receiving
24
+-- or sending a byte, the client is informed by settings the err output
25
+-- line high. This way, the client can resend the data or can issue
26
+-- a resend command to the device.
27
+
28
+-- The physical ps/2 interface uses 4 lines
29
+-- For the 6-pin connector pins are assigned as follows: 
30
+-- 1 - Data
31
+-- 2 - Not Implemented
32
+-- 3 - Ground
33
+-- 4 - Vcc (+5V)
34
+-- 5 - Clock
35
+-- 6 - Not Implemented
36
+
37
+-- The clock line carries the device generated clock which has a 
38
+-- frequency in range 10 - 16.7 kHz (30 to 50us). When line is idle
39
+-- it is placed in high impedance. The clock is only generated when
40
+-- device is sending or receiving data.
41
+-- The Data and Clock lines are both open-collector with pullup
42
+-- resistors to Vcc. An "open-collector" interface has two possible
43
+-- states: low('0') or high impedance('Z').
44
+
45
+-- When device wants to send a byte, it pulls the clock line low and the
46
+-- host(i.e. this interfaces) recognizes that the device is sending data
47
+-- When the host wants to send data, it maeks a request to send. This
48
+-- is done by holding the clock line low for at least 100us, then with
49
+-- the clock line low, the data line is brought low. Next the clock line
50
+-- is released (placed in high impedance). The devices begins generating
51
+-- clock signal on clock line.
52
+-- When receiving data, bits are read from the data line (ps2_data) on
53
+-- the falling edge of the clock (ps2_clk). When sending data, the
54
+-- device reads the bits from the data line on the rising edge of the
55
+-- clock.
56
+-- A frame for sending a byte is comprised of 11 bits as shown bellow:
57
+-- bits     10     9    8    7    6    5    4    3    2    1      0
58
+--        -------------------------------------------------------------
59
+--        | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
60
+--        -------------------------------------------------------------
61
+-- STOP  - stop  bit, always '1'
62
+-- PAR   - parity bit, odd parity for the 8 data bits.
63
+--       - select in such way that the number of bits of '1' in the data
64
+--       - bits together with parity bit is odd.
65
+-- D0-7  - data bits.
66
+-- START - start bit, always '0'
67
+--
68
+-- Frame is sent bit by bit starting with the least significant bit
69
+-- (starting bit) and is received the same way. This is done, when
70
+-- receiving, by shifting the frame register to the left when a bit
71
+-- is available and placing the bit on data line on the most significant
72
+-- bit. This way the first bit sent will reach the least significant bit
73
+-- of the frame when all the bits have been received. When sending data
74
+-- the least significant bit of the frame is placed on the data line
75
+-- and the frame is shifted to the right when another bit needs to be
76
+-- sent. During the request to send, when releasing the clock line,
77
+-- the device reads the data line and interprets the data on it as the
78
+-- first bit of the frame. Data line is low at that time, at this is the
79
+-- way the start bit('0') is sent. Because of this, when sending, only
80
+-- 10 shifts of the frame will be made.
81
+-- While the interface is sending or receiving data, the busy output
82
+-- signal goes high. When interface is idle, busy is low.
83
+-- After sending all the bits in the frame, the device must acknowledge
84
+-- the data sent. This is done by the host releasing and data line
85
+-- (clock line is already released) after the last bit is sent. The
86
+-- devices brings the data line and the clock line low, in this order,
87
+-- to acknowledge the data. If data line is high when clock line goes
88
+-- low after last bit, the device did not acknowledge the data and
89
+-- err output is set.
90
+-- A FSM is used to manage the transitions the set all the command
91
+-- signals. States that begin with "rx_" are used to receive data
92
+-- from device and states begining with "tx_" are used to send data
93
+-- to the device.
94
+-- For the parity bit, a ROM holds the parity bit for all possible
95
+-- data (256 possible values, since 8 bits of data). The ROM has
96
+-- dimensions 256x1bit. For obtaining the parity bit of a value,
97
+-- the bit at the data value address is read. Ex: to find the parity
98
+-- bit of 174, the bit at address 174 is read.
99
+-- For generating the necessary delay, counters are used. For example,
100
+-- to generate the 100us delay a 14 bit counter is used that has the
101
+-- upper limit for counting 10000. The interface is designed to run
102
+-- at 100MHz. Thus, 10000x10ns = 100us.
103
+
104
+-----------------------------------------------------------------------
105
+-- If using the interface at different frequency than 100MHz, adjusting
106
+-- the delay counters is necessary!!!
107
+-----------------------------------------------------------------------
108
+
109
+-- Clock line(ps2_clk) and data line(ps2_data) are passed through a
110
+-- debouncer for the transitions of the clock and data to be clean.
111
+-- Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
112
+-- value of the clock and data line to the system clock(clk).
113
+------------------------------------------------------------------------
114
+--  Port definitions
115
+------------------------------------------------------------------------
116
+-- ps2_clk        - inout pin, clock line of the ps/2 interface
117
+-- ps2_data       - inout pin, data line of the ps/2 interface
118
+-- clk            - input pin, system clock signal
119
+-- rst            - input pin, system reset signal
120
+-- tx_data        - input pin, 8 bits, from client
121
+--                - data to be sent to the device
122
+-- write_data     - input pin, from client
123
+--                - should be active for one clock period when then
124
+--                - client wants to send data to the device and
125
+--                - data to be sent is valid on tx_data
126
+-- rx_data        - output pin, 8 bits, to client
127
+--                - data received from device
128
+-- read           - output pin, to client
129
+--                - active for one clock period when new data is
130
+--                - available from device
131
+-- busy           - output pin, to client
132
+--                - active while sending or receiving data.
133
+-- err            - output pin, to client
134
+--                - active for one clock period when an error occurred
135
+--                - during sending or receiving.
136
+------------------------------------------------------------------------
137
+-- Revision History:
138
+-- 09/18/2006(UlrichZ): created
139
+------------------------------------------------------------------------
140
+
141
+library IEEE;
142
+use IEEE.STD_LOGIC_1164.ALL;
143
+use IEEE.STD_LOGIC_ARITH.ALL;
144
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
145
+
146
+-- simulation library
147
+library UNISIM;
148
+use UNISIM.VComponents.all;
149
+
150
+-- the ps2interface entity declaration
151
+-- read above for behavioral description and port definitions.
152
+entity Ps2Interface is
153
+port(
154
+   ps2_clk  : inout std_logic;
155
+   ps2_data : inout std_logic;
156
+
157
+   clk      : in std_logic;
158
+   rst      : in std_logic;
159
+
160
+   tx_data  : in std_logic_vector(7 downto 0);
161
+   write_data : in std_logic;
162
+   
163
+   rx_data  : out std_logic_vector(7 downto 0);
164
+   read_data  : out std_logic;
165
+   busy     : out std_logic;
166
+   err      : out std_logic
167
+
168
+);
169
+
170
+-- forces the extraction of distributed ram for
171
+-- the parity rom memory.
172
+-- please remove if block ram is preffered.
173
+attribute rom_extract : string;
174
+attribute rom_extract of Ps2Interface: entity is "yes";
175
+attribute rom_style : string;
176
+attribute rom_style of Ps2Interface: entity is "distributed";
177
+
178
+end Ps2Interface;
179
+
180
+architecture Behavioral of Ps2Interface is
181
+
182
+------------------------------------------------------------------------
183
+-- CONSTANTS
184
+------------------------------------------------------------------------
185
+
186
+-- Values are valid for a 100MHz clk. Please adjust for other
187
+-- frequencies if necessary!
188
+
189
+-- upper limit for 100us delay counter.
190
+-- 10000 * 10ns = 100us
191
+constant DELAY_100US : std_logic_vector(13 downto 0):= "10011100010000";
192
+                                                 -- 10000 clock periods
193
+-- upper limit for 20us delay counter.
194
+-- 2000 * 10ns = 20us
195
+constant DELAY_20US  : std_logic_vector(10 downto 0) := "11111010000";
196
+                                                  -- 2000 clock periods
197
+-- upper limit for 63clk delay counter.
198
+constant DELAY_63CLK : std_logic_vector(6 downto 0)  := "1111111";
199
+                                                    -- 63 clock periods
200
+-- delay from debouncing ps2_clk and ps2_data signals
201
+constant DEBOUNCE_DELAY : std_logic_vector(3 downto 0)  := "1111";
202
+
203
+-- number of bits in a frame
204
+constant NUMBITS: std_logic_vector(3 downto 0) := "1011"; -- 11
205
+
206
+-- parity bit position in frame
207
+constant PARITY_BIT: positive := 9;
208
+
209
+-- (odd) parity bit ROM
210
+-- Used instead of logic because this way speed is far greater
211
+-- 256x1bit rom
212
+-- If the odd parity bit for a 8 bits number, x, is needed
213
+-- the bit at address x is the parity bit.
214
+type ROM is array(0 to 255) of std_logic;
215
+constant parityrom : ROM := (
216
+'1','0','0','1','0','1','1','0',
217
+'0','1','1','0','1','0','0','1',
218
+'0','1','1','0','1','0','0','1',
219
+'1','0','0','1','0','1','1','0',
220
+'0','1','1','0','1','0','0','1',
221
+'1','0','0','1','0','1','1','0',
222
+'1','0','0','1','0','1','1','0',
223
+'0','1','1','0','1','0','0','1',
224
+'0','1','1','0','1','0','0','1',
225
+'1','0','0','1','0','1','1','0',
226
+'1','0','0','1','0','1','1','0',
227
+'0','1','1','0','1','0','0','1',
228
+'1','0','0','1','0','1','1','0',
229
+'0','1','1','0','1','0','0','1',
230
+'0','1','1','0','1','0','0','1',
231
+'1','0','0','1','0','1','1','0',
232
+'0','1','1','0','1','0','0','1',
233
+'1','0','0','1','0','1','1','0',
234
+'1','0','0','1','0','1','1','0',
235
+'0','1','1','0','1','0','0','1',
236
+'1','0','0','1','0','1','1','0',
237
+'0','1','1','0','1','0','0','1',
238
+'0','1','1','0','1','0','0','1',
239
+'1','0','0','1','0','1','1','0',
240
+'1','0','0','1','0','1','1','0',
241
+'0','1','1','0','1','0','0','1',
242
+'0','1','1','0','1','0','0','1',
243
+'1','0','0','1','0','1','1','0',
244
+'0','1','1','0','1','0','0','1',
245
+'1','0','0','1','0','1','1','0',
246
+'1','0','0','1','0','1','1','0',
247
+'0','1','1','0','1','0','0','1'
248
+);
249
+
250
+------------------------------------------------------------------------
251
+-- SIGNALS
252
+------------------------------------------------------------------------
253
+
254
+-- 14 bits counter
255
+-- max value DELAY_100US
256
+-- used to wait 100us
257
+signal delay_100us_count: std_logic_vector(13 downto 0) :=
258
+                                          (others => '0');
259
+
260
+-- 11 bits counter
261
+-- max value DELAY_20US
262
+-- used to wait 20us
263
+signal delay_20us_count: std_logic_vector(10 downto 0) :=
264
+                                         (others => '0');
265
+-- 11 bits counter
266
+-- max value DELAY_63CLK
267
+-- used to wait 63 clock periods
268
+signal delay_63clk_count: std_logic_vector(6 downto 0) :=
269
+                                          (others => '0');
270
+
271
+-- done signal for the couters above
272
+-- when a counter reaches max value,the corresponding done signal is set
273
+signal delay_100us_done, delay_20us_done, delay_63clk_done: std_logic;
274
+
275
+-- enable signal for 100us delay counter
276
+signal delay_100us_counter_enable: std_logic := '0';
277
+-- enable signal for 20us delay counter
278
+signal delay_20us_counter_enable : std_logic := '0';
279
+-- enable signal for 63clk delay counter
280
+signal delay_63clk_counter_enable: std_logic := '0';
281
+
282
+-- synchronzed input for ps2_clk and ps2_data
283
+signal ps2_clk_s,ps2_data_s: std_logic := '1';
284
+
285
+-- control the output of ps2_clk and ps2_data
286
+-- if 1 then corresponding signal (ps2_clk or ps2_data) is
287
+-- put in high impedance ('Z').
288
+signal ps2_clk_h,ps2_data_h: std_logic := '1';
289
+
290
+-- states of the FSM for controlling the communcation with the device
291
+-- states that begin with "rx_" are used when receiving data
292
+-- states that begin with "tx_" are used when transmiting data
293
+type fsm_state is
294
+(
295
+   idle,rx_clk_h,rx_clk_l,rx_down_edge,rx_error_parity,rx_data_ready,
296
+   tx_force_clk_l,tx_bring_data_down,tx_release_clk,
297
+   tx_first_wait_down_edge,tx_clk_l,tx_wait_up_edge,tx_clk_h,
298
+   tx_wait_up_edge_before_ack,tx_wait_ack,tx_received_ack,
299
+   tx_error_no_ack
300
+);
301
+
302
+-- the signal that holds the current state of the FSM
303
+-- implicitly state is idle.
304
+signal state: fsm_state := idle;
305
+
306
+-- register that holds the frame received or the one to be sent.
307
+-- Its contents are shifted in from the bus one bit at a time
308
+-- from left to right when receiving data and are shifted on the
309
+-- bus (ps2_data) one bit at a time to the right when sending data
310
+signal frame: std_logic_vector(10 downto 0) := (others => '0');
311
+
312
+-- how many bits have been sent or received.
313
+signal bit_count: std_logic_vector(3 downto 0) := (others => '0');
314
+
315
+-- when active the bit counter is reset.
316
+signal reset_bit_count: std_logic := '0';
317
+
318
+-- when active the contents of the frame is shifted to the right
319
+-- and the most significant bit of frame is loaded with ps2_data.
320
+signal shift_frame: std_logic := '0';
321
+
322
+-- parity of the byte that was received from the device.
323
+-- must match the parity bit received, else error occurred.
324
+signal rx_parity: std_logic := '0';
325
+-- parity bit that is sent with the frame, representing the
326
+-- odd parity of the byte currently being sent
327
+signal tx_parity: std_logic := '0';
328
+
329
+-- when active, frame is loaded with the start bit, data on
330
+-- tx_data, parity bit (tx_parity) and stop bit
331
+-- this frame will be sent to the device.
332
+signal load_tx_data: std_logic := '0';
333
+
334
+-- when active bits 8 downto 1 from frame are loaded into
335
+-- rx_data register. This is the byte received from the device.
336
+signal load_rx_data: std_logic := '0';
337
+
338
+-- intermediary signals used to debounce the inputs ps2_clk and ps2_data
339
+signal ps2_clk_clean,ps2_data_clean: std_logic := '1';
340
+-- debounce counter for the ps2_clk input and the ps2_data input.
341
+signal clk_count,data_count: std_logic_vector(3 downto 0);
342
+-- last value on ps2_clk and ps2_data.
343
+signal clk_inter,data_inter: std_logic := '1';
344
+
345
+begin
346
+
347
+   ---------------------------------------------------------------------
348
+   -- FLAGS and PS2 CLOCK AND DATA LINES
349
+   ---------------------------------------------------------------------
350
+
351
+   -- clean ps2_clk signal (debounce)
352
+   -- note that this introduces a delay in ps2_clk of
353
+   -- DEBOUNCE_DELAY clocks
354
+   process(clk)
355
+   begin
356
+      if(rising_edge(clk)) then
357
+         -- if the current bit on ps2_clk is different
358
+         -- from the last value, then reset counter
359
+         -- and retain value
360
+         if(ps2_clk /= clk_inter) then
361
+            clk_inter <= ps2_clk;
362
+            clk_count <= (others => '0');
363
+         -- if counter reached upper limit, then
364
+         -- the signal is clean
365
+         elsif(clk_count = DEBOUNCE_DELAY) then
366
+            ps2_clk_clean <= clk_inter;
367
+         -- ps2_clk did not change, but counter did not
368
+         -- reach limit. Increment counter
369
+         else
370
+            clk_count <= clk_count + 1;
371
+         end if;
372
+      end if;
373
+   end process;
374
+
375
+   -- clean ps2_data signal (debounce)
376
+   -- note that this introduces a delay in ps2_data of
377
+   -- DEBOUNCE_DELAY clocks
378
+   process(clk)
379
+   begin
380
+      if(rising_edge(clk)) then
381
+         -- if the current bit on ps2_data is different
382
+         -- from the last value, then reset counter
383
+         -- and retain value
384
+         if(ps2_data /= data_inter) then
385
+            data_inter <= ps2_data;
386
+            data_count <= (others => '0');
387
+         -- if counter reached upper limit, then
388
+         -- the signal is clean
389
+         elsif(data_count = DEBOUNCE_DELAY) then
390
+            ps2_data_clean <= data_inter;
391
+         -- ps2_data did not change, but counter did not
392
+         -- reach limit. Increment counter
393
+         else
394
+            data_count <= data_count + 1;
395
+         end if;
396
+      end if;
397
+   end process;
398
+   
399
+   -- Synchronize ps2 entries
400
+   ps2_clk_s <= ps2_clk_clean when rising_edge(clk);
401
+   ps2_data_s <= ps2_data_clean when rising_edge(clk);
402
+
403
+   -- Assign parity from frame bits 8 downto 1, this is the parity
404
+   -- that should be received inside the frame on PARITY_BIT position
405
+   rx_parity <= parityrom(conv_integer(frame(8 downto 1)))
406
+                when rising_edge(clk);
407
+   -- The parity for the data to be sent
408
+   tx_parity <= parityrom(conv_integer(tx_data)) when rising_edge(clk);
409
+
410
+   -- Force ps2_clk to '0' if ps2_clk_h = '0', else release the line
411
+   -- ('Z' = +5Vcc because of pull-ups)
412
+   ps2_clk <= 'Z' when ps2_clk_h = '1' else '0';
413
+
414
+   -- Force ps2_data to '0' if ps2_data_h = '0', else release the line
415
+   -- ('Z' = +5Vcc because of pull-ups)
416
+   ps2_data <= 'Z' when ps2_data_h = '1' else '0';
417
+
418
+   -- Control busy flag. Interface is not busy while in idle state.
419
+   busy <= '0' when state = idle else '1';
420
+
421
+   -- reset the bit counter when in idle state.
422
+   reset_bit_count <= '1' when state = idle else '0';
423
+
424
+   -- Control shifting of the frame
425
+   -- When receiving from device, data is read
426
+   -- on the falling edge of ps2_clk
427
+   -- When sending to device, data is read by device
428
+   -- on the rising edge of ps2_clk
429
+   shift_frame <= '1' when state = rx_down_edge or
430
+                           state = tx_clk_l else
431
+                  '0';
432
+
433
+   ---------------------------------------------------------------------
434
+   -- FINITE STATE MACHINE
435
+   ---------------------------------------------------------------------
436
+
437
+   -- For the current state establish next state
438
+   -- and give necessary commands
439
+   manage_fsm: process(clk,rst,state,ps2_clk_s,ps2_data_s,write_data,tx_data,
440
+                       bit_count,rx_parity,frame,delay_100us_done,
441
+                       delay_20us_done,delay_63clk_done)
442
+   begin
443
+      -- if reset occurs, go to idle state.
444
+      if(rst = '1') then
445
+         state <= idle;
446
+      elsif(rising_edge(clk)) then
447
+            
448
+         -- default values for these signals
449
+         -- ensures signals are reset to default value
450
+         -- when coditions for their activation are no
451
+         -- longer applied (transition to other state,
452
+         -- where signal should not be active)
453
+         -- Idle value for ps2_clk and ps2_data is 'Z'
454
+         ps2_clk_h <= '1';
455
+         ps2_data_h <= '1';
456
+         load_tx_data <= '0';
457
+         load_rx_data <= '0';
458
+         read_data <= '0';
459
+         err <= '0';
460
+
461
+         case state is
462
+   
463
+            -- wait for the device to begin a transmission
464
+            -- by pulling the clock line low and go to state