Browse Source

Test compteur, NON FONCTIONNEL

Paul Faure 5 months ago
parent
commit
3cc8138312

+ 75
- 75
Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -4,78 +4,78 @@
4 4
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5 5
 
6 6
 ## Clock signal
7
-set_property PACKAGE_PIN W5 [get_ports clk]
8
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
9
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
7
+set_property PACKAGE_PIN W5 [get_ports CLK]
8
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
9
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
10 10
 
11 11
 ## Switches
12
-set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
13
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
14
-set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
15
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
16
-set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
17
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
18
-set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
19
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
20
-set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
21
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
22
-set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
23
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
24
-set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26
-set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
28
-set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
-set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
-set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
-set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
-set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
-set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
-set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
-set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
12
+set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
13
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
14
+set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
15
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
16
+set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
17
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
18
+set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
19
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
20
+set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
21
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
22
+set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
23
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
24
+set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
25
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
26
+set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
27
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
28
+#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
+#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
+#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
+#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
+#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
+#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
+#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
+#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
44 44
 
45 45
 
46 46
 ## LEDs
47
-set_property PACKAGE_PIN U16 [get_ports {led[0]}]
48
-set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
49
-set_property PACKAGE_PIN E19 [get_ports {led[1]}]
50
-set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
51
-set_property PACKAGE_PIN U19 [get_ports {led[2]}]
52
-set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
53
-set_property PACKAGE_PIN V19 [get_ports {led[3]}]
54
-set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
55
-set_property PACKAGE_PIN W18 [get_ports {led[4]}]
56
-set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
57
-set_property PACKAGE_PIN U15 [get_ports {led[5]}]
58
-set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
59
-set_property PACKAGE_PIN U14 [get_ports {led[6]}]
60
-set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
61
-set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62
-set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
63
-set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64
-set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65
-set_property PACKAGE_PIN V3 [get_ports {led[9]}]
66
-set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
67
-set_property PACKAGE_PIN W3 [get_ports {led[10]}]
68
-set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69
-set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70
-set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71
-set_property PACKAGE_PIN P3 [get_ports {led[12]}]
72
-set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
73
-set_property PACKAGE_PIN N3 [get_ports {led[13]}]
74
-set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
75
-set_property PACKAGE_PIN P1 [get_ports {led[14]}]
76
-set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
77
-set_property PACKAGE_PIN L1 [get_ports {led[15]}]
78
-set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
47
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
48
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
49
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
50
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
51
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
52
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
53
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
54
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
55
+set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
56
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
57
+set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
58
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
59
+set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
60
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
61
+set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
62
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
63
+#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65
+#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
66
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
67
+#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
68
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69
+#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71
+#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
72
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
73
+#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
74
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
75
+#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
76
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
77
+#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
78
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
79 79
 
80 80
 
81 81
 ##7 segment display
@@ -108,16 +108,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
108 108
 
109 109
 
110 110
 ##Buttons
111
-#set_property PACKAGE_PIN U18 [get_ports btnC]
112
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
111
+set_property PACKAGE_PIN U18 [get_ports btnC]
112
+set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113 113
 #set_property PACKAGE_PIN T18 [get_ports btnU]
114 114
 	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
-#set_property PACKAGE_PIN W19 [get_ports btnL]
116
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
-#set_property PACKAGE_PIN T17 [get_ports btnR]
118
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119
-#set_property PACKAGE_PIN U17 [get_ports btnD]
120
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
115
+set_property PACKAGE_PIN W19 [get_ports btnL]
116
+set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
+set_property PACKAGE_PIN T17 [get_ports btnR]
118
+set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119
+set_property PACKAGE_PIN U17 [get_ports btnD]
120
+set_property IOSTANDARD LVCMOS33 [get_ports btnD]
121 121
 
122 122
 
123 123
 

+ 53
- 0
Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd View File

@@ -0,0 +1,53 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.04.2021 22:51:31
6
+-- Design Name: 
7
+-- Module Name: test_Compteur - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity test_Compteur is
35
+--  Port ( );
36
+end test_Compteur;
37
+
38
+architecture Behavioral of test_Compteur is
39
+    component Compteur is
40
+        Port ( CK : in STD_LOGIC;
41
+               RST : in STD_LOGIC;
42
+               SENS : in STD_LOGIC;
43
+               LOAD : in STD_LOGIC;
44
+               EN : in STD_LOGIC;
45
+               Din : in STD_LOGIC_VECTOR (7 downto 0);
46
+               Dout : out STD_LOGIC_VECTOR (7 downto 0));
47
+    end component;
48
+     
49
+    signal CK          
50
+begin
51
+
52
+
53
+end Behavioral;

Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd → Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd View File

@@ -2,9 +2,9 @@
2 2
 -- Company: 
3 3
 -- Engineer: 
4 4
 -- 
5
+-- Create Date: 09.04.2021 21:42:26
5 6
 -- Design Name: 
7
+-- Module Name: ClockDivider10 - Behavioral
6 8
 -- Project Name: 
7 9
 -- Target Devices: 
8 10
 -- Tool Versions: 
@@ -21,27 +21,34 @@
21 21
 
22 22
 library IEEE;
23 23
 use IEEE.STD_LOGIC_1164.ALL;
24
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
25 24
 
26 25
 -- Uncomment the following library declaration if using
27 26
 -- arithmetic functions with Signed or Unsigned values
28
-use IEEE.NUMERIC_STD.ALL;
27
+--use IEEE.NUMERIC_STD.ALL;
29 28
 
30 29
 -- Uncomment the following library declaration if instantiating
31 30
 -- any Xilinx leaf cells in this code.
32 31
 --library UNISIM;
33 32
 --use UNISIM.VComponents.all;
34 33
 
35
-entity LedTest is
36
-    Port ( clk : in STD_LOGIC;
37
-           sw : in STD_LOGIC_VECTOR (0 to 15);
38
-           led : out STD_LOGIC_VECTOR (0 to 15));
39
-end LedTest;
34
+entity ClockDivider10 is
35
+    Port ( clk_in : in STD_LOGIC;
36
+           clk_out : out STD_LOGIC);
37
+end ClockDivider10;
40 38
 
41
-architecture Behavioral of LedTest is
39
+architecture Behavioral of ClockDivider10 is
40
+    subtype int10 is INTEGER range 0 to 10;
41
+    signal N : int10 := 0;
42
+    signal aux : STD_LOGIC;
42 43
 begin
43 44
     process
44 45
     begin
45
-        led <= sw;
46
+        wait until clk_in'event and clk_in = '1';
47
+        N <= N + 1;
48
+        if N = 10 then
49
+            aux <= not aux;
50
+            N <= 0;
51
+        end if;
46 52
     end process;
53
+    clk_out <= aux;
47 54
 end Behavioral;

+ 50
- 0
Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd View File

@@ -0,0 +1,50 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.04.2021 21:44:36
6
+-- Design Name: 
7
+-- Module Name: ClockDivider1000 - Structural
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity ClockDivider1000 is
35
+    Port ( clk_in : in STD_LOGIC;
36
+           clk_out : out STD_LOGIC);
37
+end ClockDivider1000;
38
+
39
+architecture Structural of ClockDivider1000 is
40
+    component ClockDivider10
41
+        Port ( clk_in : in STD_LOGIC;
42
+               clk_out : out STD_LOGIC);
43
+    end component;
44
+    
45
+    signal aux1, aux2 : STD_LOGIC;
46
+begin
47
+    U1: ClockDivider10 port map(clk_in, aux1);
48
+    U2: ClockDivider10 port map(aux1, aux2);
49
+    U3: ClockDivider10 port map(aux2, clk_out);
50
+end Structural;

+ 64
- 0
Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd View File

@@ -0,0 +1,64 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.04.2021 21:20:39
6
+-- Design Name: 
7
+-- Module Name: Compteur - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+-- use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity Compteur is
36
+    Port ( CK : in STD_LOGIC;
37
+           RST : in STD_LOGIC;
38
+           SENS : in STD_LOGIC;
39
+           LOAD : in STD_LOGIC;
40
+           EN : in STD_LOGIC;
41
+           Din : in STD_LOGIC_VECTOR (7 downto 0);
42
+           Dout : out STD_LOGIC_VECTOR (7 downto 0));
43
+end Compteur;
44
+
45
+architecture Behavioral of Compteur is
46
+    signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
47
+begin
48
+    Dout <= aux;
49
+    process
50
+    begin
51
+        wait until CK'event and CK='1';
52
+        if RST = '0' then
53
+            aux <= (others => '0');
54
+        elsif LOAD = '1' then
55
+            aux <= Din;
56
+        elsif EN = '0' then
57
+            if SENS = '1' then
58
+                aux <= aux + 1;
59
+            else 
60
+                aux <= aux - 1;
61
+            end if;
62
+        end if;
63
+    end process;
64
+end Behavioral;

+ 66
- 0
Compteur8BitsBasys3.srcs/sources_1/new/System.vhd View File

@@ -0,0 +1,66 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.04.2021 22:03:10
6
+-- Design Name: 
7
+-- Module Name: System - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+
25
+-- Uncomment the following library declaration if using
26
+-- arithmetic functions with Signed or Unsigned values
27
+--use IEEE.NUMERIC_STD.ALL;
28
+
29
+-- Uncomment the following library declaration if instantiating
30
+-- any Xilinx leaf cells in this code.
31
+--library UNISIM;
32
+--use UNISIM.VComponents.all;
33
+
34
+entity System is
35
+    Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
36
+           btnL : in STD_LOGIC;
37
+           btnC : in STD_LOGIC;
38
+           btnR : in STD_LOGIC;
39
+           btnD : in STD_LOGIC;
40
+           LED : out STD_LOGIC_VECTOR (0 to 7);
41
+           CLK : in STD_LOGIC);
42
+end System;
43
+
44
+architecture Structural of System is
45
+
46
+    component ClockDivider1000
47
+        Port ( clk_in : in STD_LOGIC;
48
+               clk_out : out STD_LOGIC);
49
+    end component;
50
+    
51
+    component Compteur
52
+        Port ( CK : in STD_LOGIC;
53
+               RST : in STD_LOGIC;
54
+               SENS : in STD_LOGIC;
55
+               LOAD : in STD_LOGIC;
56
+               EN : in STD_LOGIC;
57
+               Din : in STD_LOGIC_VECTOR (7 downto 0);
58
+               Dout : out STD_LOGIC_VECTOR (7 downto 0));
59
+    end component;
60
+    
61
+    signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
62
+begin
63
+    DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
64
+    DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
65
+    CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
66
+end Structural;

+ 31
- 9
Compteur8BitsBasys3.xpr View File

@@ -54,7 +54,25 @@
54 54
   <FileSets Version="1" Minor="31">
55 55
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
56 56
       <Filter Type="Srcs"/>
57
-      <File Path="$PSRCDIR/sources_1/new/LedTest.vhd">
57
+      <File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
58
+        <FileInfo>
59
+          <Attr Name="UsedIn" Val="synthesis"/>
60
+          <Attr Name="UsedIn" Val="simulation"/>
61
+        </FileInfo>
62
+      </File>
63
+      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
64
+        <FileInfo>
65
+          <Attr Name="UsedIn" Val="synthesis"/>
66
+          <Attr Name="UsedIn" Val="simulation"/>
67
+        </FileInfo>
68
+      </File>
69
+      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
70
+        <FileInfo>
71
+          <Attr Name="UsedIn" Val="synthesis"/>
72
+          <Attr Name="UsedIn" Val="simulation"/>
73
+        </FileInfo>
74
+      </File>
75
+      <File Path="$PSRCDIR/sources_1/new/System.vhd">
58 76
         <FileInfo>
59 77
           <Attr Name="UsedIn" Val="synthesis"/>
60 78
           <Attr Name="UsedIn" Val="simulation"/>
@@ -62,7 +80,7 @@
62 80
       </File>
63 81
       <Config>
64 82
         <Option Name="DesignMode" Val="RTL"/>
65
-        <Option Name="TopModule" Val="LedTest"/>
83
+        <Option Name="TopModule" Val="System"/>
66 84
         <Option Name="TopAutoSet" Val="TRUE"/>
67 85
       </Config>
68 86
     </FileSet>
@@ -81,9 +99,17 @@
81 99
       </Config>
82 100
     </FileSet>
83 101
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
102
+      <Filter Type="Srcs"/>
103
+      <File Path="$PSRCDIR/sim_1/new/test_Compteur.vhd">
104
+        <FileInfo>
105
+          <Attr Name="AutoDisabled" Val="1"/>
106
+          <Attr Name="UsedIn" Val="synthesis"/>
107
+          <Attr Name="UsedIn" Val="simulation"/>
108
+        </FileInfo>
109
+      </File>
84 110
       <Config>
85 111
         <Option Name="DesignMode" Val="RTL"/>
86
-        <Option Name="TopModule" Val="LedTest"/>
112
+        <Option Name="TopModule" Val="System"/>
87 113
         <Option Name="TopLib" Val="xil_defaultlib"/>
88 114
         <Option Name="TopAutoSet" Val="TRUE"/>
89 115
         <Option Name="TransportPathDelay" Val="0"/>
@@ -114,9 +140,7 @@
114 140
   <Runs Version="1" Minor="10">
115 141
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
116 142
       <Strategy Version="1" Minor="2">
117
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
118
-          <Desc>Vivado Synthesis Defaults</Desc>
119
-        </StratHandle>
143
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
120 144
         <Step Id="synth_design"/>
121 145
       </Strategy>
122 146
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -124,9 +148,7 @@
124 148
     </Run>
125 149
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
126 150
       <Strategy Version="1" Minor="2">
127
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
128
-          <Desc>Default settings for Implementation.</Desc>
129
-        </StratHandle>
151
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
130 152
         <Step Id="init_design"/>
131 153
         <Step Id="opt_design"/>
132 154
         <Step Id="power_opt_design"/>

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