diff --git a/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc b/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
index 885300d..27543c5 100644
--- a/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
+++ b/Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc
@@ -4,78 +4,78 @@
 ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
 
 ## Clock signal
-set_property PACKAGE_PIN W5 [get_ports clk]
-set_property IOSTANDARD LVCMOS33 [get_ports clk]
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+set_property PACKAGE_PIN W5 [get_ports CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
 
 ## Switches
-set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
-set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
-set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
-set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
-set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
-set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
-set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
-set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
-set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
-set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
-set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
-set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
-set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
-set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
-set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
-set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
+set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
+set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
+set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
+set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
+set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
+set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
+set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
+#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
 
 
 ## LEDs
-set_property PACKAGE_PIN U16 [get_ports {led[0]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
-set_property PACKAGE_PIN E19 [get_ports {led[1]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
-set_property PACKAGE_PIN U19 [get_ports {led[2]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
-set_property PACKAGE_PIN V19 [get_ports {led[3]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
-set_property PACKAGE_PIN W18 [get_ports {led[4]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
-set_property PACKAGE_PIN U15 [get_ports {led[5]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
-set_property PACKAGE_PIN U14 [get_ports {led[6]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
-set_property PACKAGE_PIN V14 [get_ports {led[7]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
-set_property PACKAGE_PIN V13 [get_ports {led[8]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
-set_property PACKAGE_PIN V3 [get_ports {led[9]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
-set_property PACKAGE_PIN W3 [get_ports {led[10]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
-set_property PACKAGE_PIN U3 [get_ports {led[11]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
-set_property PACKAGE_PIN P3 [get_ports {led[12]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
-set_property PACKAGE_PIN N3 [get_ports {led[13]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
-set_property PACKAGE_PIN P1 [get_ports {led[14]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
-set_property PACKAGE_PIN L1 [get_ports {led[15]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
+set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
+set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
+set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
+set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
+set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
+set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
+set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
+#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
 
 
 ##7 segment display
@@ -108,16 +108,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
 
 
 ##Buttons
-#set_property PACKAGE_PIN U18 [get_ports btnC]
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+set_property PACKAGE_PIN U18 [get_ports btnC]
+set_property IOSTANDARD LVCMOS33 [get_ports btnC]
 #set_property PACKAGE_PIN T18 [get_ports btnU]
 	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
-#set_property PACKAGE_PIN W19 [get_ports btnL]
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
-#set_property PACKAGE_PIN T17 [get_ports btnR]
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
-#set_property PACKAGE_PIN U17 [get_ports btnD]
-	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
+set_property PACKAGE_PIN W19 [get_ports btnL]
+set_property IOSTANDARD LVCMOS33 [get_ports btnL]
+set_property PACKAGE_PIN T17 [get_ports btnR]
+set_property IOSTANDARD LVCMOS33 [get_ports btnR]
+set_property PACKAGE_PIN U17 [get_ports btnD]
+set_property IOSTANDARD LVCMOS33 [get_ports btnD]
 
 
 
diff --git a/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd b/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
new file mode 100644
index 0000000..88d42fb
--- /dev/null
+++ b/Compteur8BitsBasys3.srcs/sim_1/new/test_Compteur.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.04.2021 22:51:31
+-- Design Name: 
+-- Module Name: test_Compteur - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_Compteur is
+--  Port ( );
+end test_Compteur;
+
+architecture Behavioral of test_Compteur is
+    component Compteur is
+        Port ( CK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               SENS : in STD_LOGIC;
+               LOAD : in STD_LOGIC;
+               EN : in STD_LOGIC;
+               Din : in STD_LOGIC_VECTOR (7 downto 0);
+               Dout : out STD_LOGIC_VECTOR (7 downto 0));
+    end component;
+     
+    signal CK          
+begin
+
+
+end Behavioral;
diff --git a/Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd b/Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd
similarity index 58%
rename from Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd
rename to Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd
index 84521a9..d09c2ec 100644
--- a/Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd
+++ b/Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider10.vhd
@@ -2,9 +2,9 @@
 -- Company: 
 -- Engineer: 
 -- 
--- Create Date: 09.04.2021 19:00:49
+-- Create Date: 09.04.2021 21:42:26
 -- Design Name: 
--- Module Name: LedTest - Behavioral
+-- Module Name: ClockDivider10 - Behavioral
 -- Project Name: 
 -- Target Devices: 
 -- Tool Versions: 
@@ -21,27 +21,34 @@
 
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
+--use IEEE.NUMERIC_STD.ALL;
 
 -- Uncomment the following library declaration if instantiating
 -- any Xilinx leaf cells in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 
-entity LedTest is
-    Port ( clk : in STD_LOGIC;
-           sw : in STD_LOGIC_VECTOR (0 to 15);
-           led : out STD_LOGIC_VECTOR (0 to 15));
-end LedTest;
+entity ClockDivider10 is
+    Port ( clk_in : in STD_LOGIC;
+           clk_out : out STD_LOGIC);
+end ClockDivider10;
 
-architecture Behavioral of LedTest is
+architecture Behavioral of ClockDivider10 is
+    subtype int10 is INTEGER range 0 to 10;
+    signal N : int10 := 0;
+    signal aux : STD_LOGIC;
 begin
     process
     begin
-        led <= sw;
+        wait until clk_in'event and clk_in = '1';
+        N <= N + 1;
+        if N = 10 then
+            aux <= not aux;
+            N <= 0;
+        end if;
     end process;
+    clk_out <= aux;
 end Behavioral;
diff --git a/Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd b/Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd
new file mode 100644
index 0000000..cf026ad
--- /dev/null
+++ b/Compteur8BitsBasys3.srcs/sources_1/new/ClockDivider1000.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.04.2021 21:44:36
+-- Design Name: 
+-- Module Name: ClockDivider1000 - Structural
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ClockDivider1000 is
+    Port ( clk_in : in STD_LOGIC;
+           clk_out : out STD_LOGIC);
+end ClockDivider1000;
+
+architecture Structural of ClockDivider1000 is
+    component ClockDivider10
+        Port ( clk_in : in STD_LOGIC;
+               clk_out : out STD_LOGIC);
+    end component;
+    
+    signal aux1, aux2 : STD_LOGIC;
+begin
+    U1: ClockDivider10 port map(clk_in, aux1);
+    U2: ClockDivider10 port map(aux1, aux2);
+    U3: ClockDivider10 port map(aux2, clk_out);
+end Structural;
diff --git a/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd b/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
new file mode 100644
index 0000000..eb8a5ce
--- /dev/null
+++ b/Compteur8BitsBasys3.srcs/sources_1/new/Compteur.vhd
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.04.2021 21:20:39
+-- Design Name: 
+-- Module Name: Compteur - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+-- use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Compteur is
+    Port ( CK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           SENS : in STD_LOGIC;
+           LOAD : in STD_LOGIC;
+           EN : in STD_LOGIC;
+           Din : in STD_LOGIC_VECTOR (7 downto 0);
+           Dout : out STD_LOGIC_VECTOR (7 downto 0));
+end Compteur;
+
+architecture Behavioral of Compteur is
+    signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
+begin
+    Dout <= aux;
+    process
+    begin
+        wait until CK'event and CK='1';
+        if RST = '0' then
+            aux <= (others => '0');
+        elsif LOAD = '1' then
+            aux <= Din;
+        elsif EN = '0' then
+            if SENS = '1' then
+                aux <= aux + 1;
+            else 
+                aux <= aux - 1;
+            end if;
+        end if;
+    end process;
+end Behavioral;
diff --git a/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd b/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd
new file mode 100644
index 0000000..52fded3
--- /dev/null
+++ b/Compteur8BitsBasys3.srcs/sources_1/new/System.vhd
@@ -0,0 +1,66 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.04.2021 22:03:10
+-- Design Name: 
+-- Module Name: System - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity System is
+    Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
+           btnL : in STD_LOGIC;
+           btnC : in STD_LOGIC;
+           btnR : in STD_LOGIC;
+           btnD : in STD_LOGIC;
+           LED : out STD_LOGIC_VECTOR (0 to 7);
+           CLK : in STD_LOGIC);
+end System;
+
+architecture Structural of System is
+
+    component ClockDivider1000
+        Port ( clk_in : in STD_LOGIC;
+               clk_out : out STD_LOGIC);
+    end component;
+    
+    component Compteur
+        Port ( CK : in STD_LOGIC;
+               RST : in STD_LOGIC;
+               SENS : in STD_LOGIC;
+               LOAD : in STD_LOGIC;
+               EN : in STD_LOGIC;
+               Din : in STD_LOGIC_VECTOR (7 downto 0);
+               Dout : out STD_LOGIC_VECTOR (7 downto 0));
+    end component;
+    
+    signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
+begin
+    DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
+    DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
+    CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
+end Structural;
diff --git a/Compteur8BitsBasys3.xpr b/Compteur8BitsBasys3.xpr
index 761da2d..1fb19bf 100644
--- a/Compteur8BitsBasys3.xpr
+++ b/Compteur8BitsBasys3.xpr
@@ -54,7 +54,25 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
       <Filter Type="Srcs"/>
-      <File Path="$PSRCDIR/sources_1/new/LedTest.vhd">
+      <File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/System.vhd">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="simulation"/>
@@ -62,7 +80,7 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="LedTest"/>
+        <Option Name="TopModule" Val="System"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
@@ -81,9 +99,17 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/test_Compteur.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="LedTest"/>
+        <Option Name="TopModule" Val="System"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
         <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
@@ -114,9 +140,7 @@
   <Runs Version="1" Minor="10">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -124,9 +148,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>