Version initiale (Switch+LED)
This commit is contained in:
commit
38eabeaa19
4 changed files with 495 additions and 0 deletions
5
.gitignore
vendored
Normal file
5
.gitignore
vendored
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
Compteur8BitsBasys3.ip_user_files/*
|
||||
Compteur8BitsBasys3.cache/*
|
||||
Compteur8BitsBasys3.hw/*
|
||||
Compteur8BitsBasys3.runs/*
|
||||
Compteur8BitsBasys3.sim/*
|
||||
|
|
@ -0,0 +1,299 @@
|
|||
## This file is a general .xdc for the Basys3 rev B board
|
||||
## To use it in a project:
|
||||
## - uncomment the lines corresponding to used pins
|
||||
## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
|
||||
|
||||
## Clock signal
|
||||
set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
|
||||
|
||||
## Switches
|
||||
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
|
||||
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
|
||||
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
|
||||
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
|
||||
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
|
||||
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
|
||||
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
|
||||
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
|
||||
set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
|
||||
set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
|
||||
set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
|
||||
set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
|
||||
set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
|
||||
set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
|
||||
|
||||
|
||||
## LEDs
|
||||
set_property PACKAGE_PIN U16 [get_ports {led[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {led[1]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN V19 [get_ports {led[3]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN W18 [get_ports {led[4]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
|
||||
set_property PACKAGE_PIN U15 [get_ports {led[5]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
|
||||
set_property PACKAGE_PIN U14 [get_ports {led[6]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
|
||||
set_property PACKAGE_PIN V14 [get_ports {led[7]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
|
||||
set_property PACKAGE_PIN V13 [get_ports {led[8]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
|
||||
set_property PACKAGE_PIN V3 [get_ports {led[9]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
|
||||
set_property PACKAGE_PIN W3 [get_ports {led[10]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
|
||||
set_property PACKAGE_PIN U3 [get_ports {led[11]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
|
||||
set_property PACKAGE_PIN P3 [get_ports {led[12]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
|
||||
set_property PACKAGE_PIN N3 [get_ports {led[13]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
|
||||
set_property PACKAGE_PIN P1 [get_ports {led[14]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
|
||||
set_property PACKAGE_PIN L1 [get_ports {led[15]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
|
||||
|
||||
|
||||
##7 segment display
|
||||
#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
|
||||
#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
|
||||
#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
|
||||
#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
|
||||
#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
|
||||
#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
|
||||
#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
|
||||
|
||||
#set_property PACKAGE_PIN V7 [get_ports dp]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports dp]
|
||||
|
||||
#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
|
||||
#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
|
||||
#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
|
||||
#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
|
||||
|
||||
|
||||
##Buttons
|
||||
#set_property PACKAGE_PIN U18 [get_ports btnC]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
|
||||
#set_property PACKAGE_PIN T18 [get_ports btnU]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
|
||||
#set_property PACKAGE_PIN W19 [get_ports btnL]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
|
||||
#set_property PACKAGE_PIN T17 [get_ports btnR]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
|
||||
#set_property PACKAGE_PIN U17 [get_ports btnD]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JA
|
||||
##Sch name = JA1
|
||||
#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
|
||||
##Sch name = JA2
|
||||
#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
|
||||
##Sch name = JA3
|
||||
#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
|
||||
##Sch name = JA4
|
||||
#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
|
||||
##Sch name = JA7
|
||||
#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
|
||||
##Sch name = JA8
|
||||
#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
|
||||
##Sch name = JA9
|
||||
#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
|
||||
##Sch name = JA10
|
||||
#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JB
|
||||
##Sch name = JB1
|
||||
#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
|
||||
##Sch name = JB2
|
||||
#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
|
||||
##Sch name = JB3
|
||||
#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
|
||||
##Sch name = JB4
|
||||
#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
|
||||
##Sch name = JB7
|
||||
#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
|
||||
##Sch name = JB8
|
||||
#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
|
||||
##Sch name = JB9
|
||||
#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
|
||||
##Sch name = JB10
|
||||
#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
|
||||
|
||||
|
||||
|
||||
##Pmod Header JC
|
||||
##Sch name = JC1
|
||||
#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
|
||||
##Sch name = JC2
|
||||
#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
|
||||
##Sch name = JC3
|
||||
#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
|
||||
##Sch name = JC4
|
||||
#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
|
||||
##Sch name = JC7
|
||||
#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
|
||||
##Sch name = JC8
|
||||
#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
|
||||
##Sch name = JC9
|
||||
#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
|
||||
##Sch name = JC10
|
||||
#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
|
||||
|
||||
|
||||
##Pmod Header JXADC
|
||||
##Sch name = XA1_P
|
||||
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
|
||||
##Sch name = XA2_P
|
||||
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
|
||||
##Sch name = XA3_P
|
||||
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
|
||||
##Sch name = XA4_P
|
||||
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
|
||||
##Sch name = XA1_N
|
||||
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
|
||||
##Sch name = XA2_N
|
||||
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
|
||||
##Sch name = XA3_N
|
||||
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
|
||||
##Sch name = XA4_N
|
||||
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
|
||||
|
||||
|
||||
|
||||
##VGA Connector
|
||||
#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
|
||||
#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
|
||||
#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
|
||||
#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
|
||||
#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
|
||||
#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
|
||||
#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
|
||||
#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
|
||||
#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
|
||||
#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
|
||||
#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
|
||||
#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
|
||||
#set_property PACKAGE_PIN P19 [get_ports Hsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
|
||||
#set_property PACKAGE_PIN R19 [get_ports Vsync]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
|
||||
|
||||
|
||||
##USB-RS232 Interface
|
||||
#set_property PACKAGE_PIN B18 [get_ports RsRx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
|
||||
#set_property PACKAGE_PIN A18 [get_ports RsTx]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
|
||||
|
||||
|
||||
##USB HID (PS/2)
|
||||
#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
|
||||
#set_property PULLUP true [get_ports PS2Clk]
|
||||
#set_property PACKAGE_PIN B17 [get_ports PS2Data]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
|
||||
#set_property PULLUP true [get_ports PS2Data]
|
||||
|
||||
|
||||
##Quad SPI Flash
|
||||
##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
|
||||
##STARTUPE2 primitive.
|
||||
#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
|
||||
#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
|
||||
#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
|
||||
#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
|
||||
#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
|
||||
|
||||
|
||||
## Configuration options, can be used for all designs
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
47
Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd
Normal file
47
Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.04.2021 19:00:49
|
||||
-- Design Name:
|
||||
-- Module Name: LedTest - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity LedTest is
|
||||
Port ( clk : in STD_LOGIC;
|
||||
sw : in STD_LOGIC_VECTOR (0 to 15);
|
||||
led : out STD_LOGIC_VECTOR (0 to 15));
|
||||
end LedTest;
|
||||
|
||||
architecture Behavioral of LedTest is
|
||||
begin
|
||||
process
|
||||
begin
|
||||
led <= sw;
|
||||
end process;
|
||||
end Behavioral;
|
||||
144
Compteur8BitsBasys3.xpr
Normal file
144
Compteur8BitsBasys3.xpr
Normal file
|
|
@ -0,0 +1,144 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2016.4 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b3843060a8224f8699d89033689dec00"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="TargetLanguage" Val="VHDL"/>
|
||||
<Option Name="SimulatorLanguage" Val="VHDL"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="basys3"/>
|
||||
<Option Name="DSANumComputeUnits" Val="16"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="64"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/LedTest.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LedTest"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1614979917"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LedTest"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SimMode" Val="post-implementation"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
</Project>
|
||||
Loading…
Reference in a new issue