Browse Source

Version initiale (Switch+LED)

Paul Faure 5 months ago
commit
38eabeaa19

+ 5
- 0
.gitignore View File

@@ -0,0 +1,5 @@
1
+Compteur8BitsBasys3.ip_user_files/*
2
+Compteur8BitsBasys3.cache/*
3
+Compteur8BitsBasys3.hw/*
4
+Compteur8BitsBasys3.runs/*
5
+Compteur8BitsBasys3.sim/*

+ 299
- 0
Compteur8BitsBasys3.srcs/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc View File

@@ -0,0 +1,299 @@
1
+## This file is a general .xdc for the Basys3 rev B board
2
+## To use it in a project:
3
+## - uncomment the lines corresponding to used pins
4
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
5
+
6
+## Clock signal
7
+set_property PACKAGE_PIN W5 [get_ports clk]
8
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
9
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
10
+
11
+## Switches
12
+set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
13
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
14
+set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
15
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
16
+set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
17
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
18
+set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
19
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
20
+set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
21
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
22
+set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
23
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
24
+set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
25
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
26
+set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
27
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
28
+set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
29
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
30
+set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
31
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
32
+set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
33
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
34
+set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
35
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
36
+set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
37
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
38
+set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
39
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
40
+set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
41
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
42
+set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
43
+set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
44
+
45
+
46
+## LEDs
47
+set_property PACKAGE_PIN U16 [get_ports {led[0]}]
48
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
49
+set_property PACKAGE_PIN E19 [get_ports {led[1]}]
50
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
51
+set_property PACKAGE_PIN U19 [get_ports {led[2]}]
52
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
53
+set_property PACKAGE_PIN V19 [get_ports {led[3]}]
54
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
55
+set_property PACKAGE_PIN W18 [get_ports {led[4]}]
56
+set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
57
+set_property PACKAGE_PIN U15 [get_ports {led[5]}]
58
+set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
59
+set_property PACKAGE_PIN U14 [get_ports {led[6]}]
60
+set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
61
+set_property PACKAGE_PIN V14 [get_ports {led[7]}]
62
+set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
63
+set_property PACKAGE_PIN V13 [get_ports {led[8]}]
64
+set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
65
+set_property PACKAGE_PIN V3 [get_ports {led[9]}]
66
+set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
67
+set_property PACKAGE_PIN W3 [get_ports {led[10]}]
68
+set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
69
+set_property PACKAGE_PIN U3 [get_ports {led[11]}]
70
+set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
71
+set_property PACKAGE_PIN P3 [get_ports {led[12]}]
72
+set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
73
+set_property PACKAGE_PIN N3 [get_ports {led[13]}]
74
+set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
75
+set_property PACKAGE_PIN P1 [get_ports {led[14]}]
76
+set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
77
+set_property PACKAGE_PIN L1 [get_ports {led[15]}]
78
+set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
79
+
80
+
81
+##7 segment display
82
+#set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
83
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
84
+#set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
85
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
86
+#set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
87
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
88
+#set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
89
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
90
+#set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
91
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
92
+#set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
93
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
94
+#set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
95
+	#set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
96
+
97
+#set_property PACKAGE_PIN V7 [get_ports dp]
98
+	#set_property IOSTANDARD LVCMOS33 [get_ports dp]
99
+
100
+#set_property PACKAGE_PIN U2 [get_ports {an[0]}]
101
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
102
+#set_property PACKAGE_PIN U4 [get_ports {an[1]}]
103
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
104
+#set_property PACKAGE_PIN V4 [get_ports {an[2]}]
105
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
106
+#set_property PACKAGE_PIN W4 [get_ports {an[3]}]
107
+	#set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
108
+
109
+
110
+##Buttons
111
+#set_property PACKAGE_PIN U18 [get_ports btnC]
112
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
113
+#set_property PACKAGE_PIN T18 [get_ports btnU]
114
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
115
+#set_property PACKAGE_PIN W19 [get_ports btnL]
116
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
117
+#set_property PACKAGE_PIN T17 [get_ports btnR]
118
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
119
+#set_property PACKAGE_PIN U17 [get_ports btnD]
120
+	#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
121
+
122
+
123
+
124
+##Pmod Header JA
125
+##Sch name = JA1
126
+#set_property PACKAGE_PIN J1 [get_ports {JA[0]}]
127
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
128
+##Sch name = JA2
129
+#set_property PACKAGE_PIN L2 [get_ports {JA[1]}]
130
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
131
+##Sch name = JA3
132
+#set_property PACKAGE_PIN J2 [get_ports {JA[2]}]
133
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
134
+##Sch name = JA4
135
+#set_property PACKAGE_PIN G2 [get_ports {JA[3]}]
136
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
137
+##Sch name = JA7
138
+#set_property PACKAGE_PIN H1 [get_ports {JA[4]}]
139
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
140
+##Sch name = JA8
141
+#set_property PACKAGE_PIN K2 [get_ports {JA[5]}]
142
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
143
+##Sch name = JA9
144
+#set_property PACKAGE_PIN H2 [get_ports {JA[6]}]
145
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
146
+##Sch name = JA10
147
+#set_property PACKAGE_PIN G3 [get_ports {JA[7]}]
148
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
149
+
150
+
151
+
152
+##Pmod Header JB
153
+##Sch name = JB1
154
+#set_property PACKAGE_PIN A14 [get_ports {JB[0]}]
155
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
156
+##Sch name = JB2
157
+#set_property PACKAGE_PIN A16 [get_ports {JB[1]}]
158
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
159
+##Sch name = JB3
160
+#set_property PACKAGE_PIN B15 [get_ports {JB[2]}]
161
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
162
+##Sch name = JB4
163
+#set_property PACKAGE_PIN B16 [get_ports {JB[3]}]
164
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
165
+##Sch name = JB7
166
+#set_property PACKAGE_PIN A15 [get_ports {JB[4]}]
167
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
168
+##Sch name = JB8
169
+#set_property PACKAGE_PIN A17 [get_ports {JB[5]}]
170
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
171
+##Sch name = JB9
172
+#set_property PACKAGE_PIN C15 [get_ports {JB[6]}]
173
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
174
+##Sch name = JB10
175
+#set_property PACKAGE_PIN C16 [get_ports {JB[7]}]
176
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
177
+
178
+
179
+
180
+##Pmod Header JC
181
+##Sch name = JC1
182
+#set_property PACKAGE_PIN K17 [get_ports {JC[0]}]
183
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
184
+##Sch name = JC2
185
+#set_property PACKAGE_PIN M18 [get_ports {JC[1]}]
186
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
187
+##Sch name = JC3
188
+#set_property PACKAGE_PIN N17 [get_ports {JC[2]}]
189
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
190
+##Sch name = JC4
191
+#set_property PACKAGE_PIN P18 [get_ports {JC[3]}]
192
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
193
+##Sch name = JC7
194
+#set_property PACKAGE_PIN L17 [get_ports {JC[4]}]
195
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
196
+##Sch name = JC8
197
+#set_property PACKAGE_PIN M19 [get_ports {JC[5]}]
198
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
199
+##Sch name = JC9
200
+#set_property PACKAGE_PIN P17 [get_ports {JC[6]}]
201
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
202
+##Sch name = JC10
203
+#set_property PACKAGE_PIN R18 [get_ports {JC[7]}]
204
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
205
+
206
+
207
+##Pmod Header JXADC
208
+##Sch name = XA1_P
209
+#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]
210
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
211
+##Sch name = XA2_P
212
+#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]
213
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
214
+##Sch name = XA3_P
215
+#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]
216
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
217
+##Sch name = XA4_P
218
+#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]
219
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
220
+##Sch name = XA1_N
221
+#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]
222
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
223
+##Sch name = XA2_N
224
+#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]
225
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
226
+##Sch name = XA3_N
227
+#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]
228
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
229
+##Sch name = XA4_N
230
+#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]
231
+	#set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
232
+
233
+
234
+
235
+##VGA Connector
236
+#set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}]
237
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
238
+#set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}]
239
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
240
+#set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}]
241
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
242
+#set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}]
243
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
244
+#set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}]
245
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
246
+#set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}]
247
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
248
+#set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}]
249
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
250
+#set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}]
251
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
252
+#set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}]
253
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
254
+#set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}]
255
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
256
+#set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}]
257
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
258
+#set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}]
259
+	#set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
260
+#set_property PACKAGE_PIN P19 [get_ports Hsync]
261
+	#set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
262
+#set_property PACKAGE_PIN R19 [get_ports Vsync]
263
+	#set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
264
+
265
+
266
+##USB-RS232 Interface
267
+#set_property PACKAGE_PIN B18 [get_ports RsRx]
268
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
269
+#set_property PACKAGE_PIN A18 [get_ports RsTx]
270
+	#set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
271
+
272
+
273
+##USB HID (PS/2)
274
+#set_property PACKAGE_PIN C17 [get_ports PS2Clk]
275
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
276
+	#set_property PULLUP true [get_ports PS2Clk]
277
+#set_property PACKAGE_PIN B17 [get_ports PS2Data]
278
+	#set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
279
+	#set_property PULLUP true [get_ports PS2Data]
280
+
281
+
282
+##Quad SPI Flash
283
+##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the
284
+##STARTUPE2 primitive.
285
+#set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}]
286
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
287
+#set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}]
288
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
289
+#set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}]
290
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
291
+#set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}]
292
+	#set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
293
+#set_property PACKAGE_PIN K19 [get_ports QspiCSn]
294
+	#set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
295
+
296
+
297
+## Configuration options, can be used for all designs
298
+set_property CONFIG_VOLTAGE 3.3 [current_design]
299
+set_property CFGBVS VCCO [current_design]

+ 47
- 0
Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd View File

@@ -0,0 +1,47 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date: 09.04.2021 19:00:49
6
+-- Design Name: 
7
+-- Module Name: LedTest - Behavioral
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool Versions: 
11
+-- Description: 
12
+-- 
13
+-- Dependencies: 
14
+-- 
15
+-- Revision:
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments:
18
+-- 
19
+----------------------------------------------------------------------------------
20
+
21
+
22
+library IEEE;
23
+use IEEE.STD_LOGIC_1164.ALL;
24
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
+
26
+-- Uncomment the following library declaration if using
27
+-- arithmetic functions with Signed or Unsigned values
28
+use IEEE.NUMERIC_STD.ALL;
29
+
30
+-- Uncomment the following library declaration if instantiating
31
+-- any Xilinx leaf cells in this code.
32
+--library UNISIM;
33
+--use UNISIM.VComponents.all;
34
+
35
+entity LedTest is
36
+    Port ( clk : in STD_LOGIC;
37
+           sw : in STD_LOGIC_VECTOR (0 to 15);
38
+           led : out STD_LOGIC_VECTOR (0 to 15));
39
+end LedTest;
40
+
41
+architecture Behavioral of LedTest is
42
+begin
43
+    process
44
+    begin
45
+        led <= sw;
46
+    end process;
47
+end Behavioral;

+ 144
- 0
Compteur8BitsBasys3.xpr View File

@@ -0,0 +1,144 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- Product Version: Vivado v2016.4 (64-bit)              -->
3
+<!--                                                         -->
4
+<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.   -->
5
+
6
+<Project Version="7" Minor="17" Path="C:/Users/Hp/Documents/Compteur8BitsBasys3/Compteur8BitsBasys3.xpr">
7
+  <DefaultLaunch Dir="$PRUNDIR"/>
8
+  <Configuration>
9
+    <Option Name="Id" Val="b3843060a8224f8699d89033689dec00"/>
10
+    <Option Name="Part" Val="xc7a35tcpg236-1"/>
11
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
12
+    <Option Name="CompiledLibDirXSim" Val=""/>
13
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
14
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
15
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
16
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
17
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
18
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
19
+    <Option Name="TargetLanguage" Val="VHDL"/>
20
+    <Option Name="SimulatorLanguage" Val="VHDL"/>
21
+    <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.1"/>
22
+    <Option Name="ActiveSimSet" Val="sim_1"/>
23
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
24
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
25
+    <Option Name="IPCachePermission" Val="read"/>
26
+    <Option Name="IPCachePermission" Val="write"/>
27
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
28
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
29
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files"/>
30
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/Compteur8BitsBasys3.ip_user_files/ipstatic"/>
31
+    <Option Name="EnableBDX" Val="FALSE"/>
32
+    <Option Name="DSABoardId" Val="basys3"/>
33
+    <Option Name="DSANumComputeUnits" Val="16"/>
34
+    <Option Name="WTXSimLaunchSim" Val="0"/>
35
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
36
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
37
+    <Option Name="WTIesLaunchSim" Val="0"/>
38
+    <Option Name="WTVcsLaunchSim" Val="0"/>
39
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
40
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
41
+    <Option Name="WTXSimExportSim" Val="0"/>
42
+    <Option Name="WTModelSimExportSim" Val="0"/>
43
+    <Option Name="WTQuestaExportSim" Val="0"/>
44
+    <Option Name="WTIesExportSim" Val="0"/>
45
+    <Option Name="WTVcsExportSim" Val="0"/>
46
+    <Option Name="WTRivieraExportSim" Val="0"/>
47
+    <Option Name="WTActivehdlExportSim" Val="0"/>
48
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
49
+    <Option Name="XSimRadix" Val="hex"/>
50
+    <Option Name="XSimTimeUnit" Val="ns"/>
51
+    <Option Name="XSimArrayDisplayLimit" Val="64"/>
52
+    <Option Name="XSimTraceLimit" Val="65536"/>
53
+  </Configuration>
54
+  <FileSets Version="1" Minor="31">
55
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
56
+      <Filter Type="Srcs"/>
57
+      <File Path="$PSRCDIR/sources_1/new/LedTest.vhd">
58
+        <FileInfo>
59
+          <Attr Name="UsedIn" Val="synthesis"/>
60
+          <Attr Name="UsedIn" Val="simulation"/>
61
+        </FileInfo>
62
+      </File>
63
+      <Config>
64
+        <Option Name="DesignMode" Val="RTL"/>
65
+        <Option Name="TopModule" Val="LedTest"/>
66
+        <Option Name="TopAutoSet" Val="TRUE"/>
67
+      </Config>
68
+    </FileSet>
69
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
70
+      <Filter Type="Constrs"/>
71
+      <File Path="$PSRCDIR/constrs_1/imports/digilent-xdc-master/Basys-3-Master.xdc">
72
+        <FileInfo>
73
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../../Xilinx/digilent-xdc-master/Basys-3-Master.xdc"/>
74
+          <Attr Name="ImportTime" Val="1614979917"/>
75
+          <Attr Name="UsedIn" Val="synthesis"/>
76
+          <Attr Name="UsedIn" Val="implementation"/>
77
+        </FileInfo>
78
+      </File>
79
+      <Config>
80
+        <Option Name="ConstrsType" Val="XDC"/>
81
+      </Config>
82
+    </FileSet>
83
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
84
+      <Config>
85
+        <Option Name="DesignMode" Val="RTL"/>
86
+        <Option Name="TopModule" Val="LedTest"/>
87
+        <Option Name="TopLib" Val="xil_defaultlib"/>
88
+        <Option Name="TopAutoSet" Val="TRUE"/>
89
+        <Option Name="TransportPathDelay" Val="0"/>
90
+        <Option Name="TransportIntDelay" Val="0"/>
91
+        <Option Name="SimMode" Val="post-implementation"/>
92
+        <Option Name="SrcSet" Val="sources_1"/>
93
+      </Config>
94
+    </FileSet>
95
+  </FileSets>
96
+  <Simulators>
97
+    <Simulator Name="XSim">
98
+      <Option Name="Description" Val="Vivado Simulator"/>
99
+      <Option Name="CompiledLib" Val="0"/>
100
+    </Simulator>
101
+    <Simulator Name="ModelSim">
102
+      <Option Name="Description" Val="ModelSim Simulator"/>
103
+    </Simulator>
104
+    <Simulator Name="Questa">
105
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
106
+    </Simulator>
107
+    <Simulator Name="Riviera">
108
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
109
+    </Simulator>
110
+    <Simulator Name="ActiveHDL">
111
+      <Option Name="Description" Val="Active-HDL Simulator"/>
112
+    </Simulator>
113
+  </Simulators>
114
+  <Runs Version="1" Minor="10">
115
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
116
+      <Strategy Version="1" Minor="2">
117
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
118
+          <Desc>Vivado Synthesis Defaults</Desc>
119
+        </StratHandle>
120
+        <Step Id="synth_design"/>
121
+      </Strategy>
122
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
123
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
124
+    </Run>
125
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
126
+      <Strategy Version="1" Minor="2">
127
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
128
+          <Desc>Default settings for Implementation.</Desc>
129
+        </StratHandle>
130
+        <Step Id="init_design"/>
131
+        <Step Id="opt_design"/>
132
+        <Step Id="power_opt_design"/>
133
+        <Step Id="place_design"/>
134
+        <Step Id="post_place_power_opt_design"/>
135
+        <Step Id="phys_opt_design"/>
136
+        <Step Id="route_design"/>
137
+        <Step Id="post_route_phys_opt_design"/>
138
+        <Step Id="write_bitstream"/>
139
+      </Strategy>
140
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
141
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
142
+    </Run>
143
+  </Runs>
144
+</Project>

Loading…
Cancel
Save