Processeur/Compteur8BitsBasys3.srcs/sources_1/new/LedTest.vhd

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.04.2021 19:00:49
-- Design Name: 
-- Module Name: LedTest - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LedTest is
    Port ( clk : in STD_LOGIC;
           sw : in STD_LOGIC_VECTOR (0 to 15);
           led : out STD_LOGIC_VECTOR (0 to 15));
end LedTest;

architecture Behavioral of LedTest is
begin
    process
    begin
        led <= sw;
    end process;
end Behavioral;