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- -- file: clk_wiz_0.vhd
- --
- -- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
- --
- -- This file contains confidential and proprietary information
- -- of Xilinx, Inc. and is protected under U.S. and
- -- international copyright and other intellectual property
- -- laws.
- --
- -- DISCLAIMER
- -- This disclaimer is not a license and does not grant any
- -- rights to the materials distributed herewith. Except as
- -- otherwise provided in a valid license issued to you by
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- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- -- (2) Xilinx shall not be liable (whether in contract or tort,
- -- including negligence, or under any other theory of
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- -- loss or damage suffered as a result of any action brought
- -- by a third party) even if such damage or loss was
- -- reasonably foreseeable or Xilinx had been advised of the
- -- possibility of the same.
- --
- -- CRITICAL APPLICATIONS
- -- Xilinx products are not designed or intended to be fail-
- -- safe, or for use in any application requiring fail-safe
- -- performance, such as life-support or safety devices or
- -- systems, Class III medical devices, nuclear facilities,
- -- applications related to the deployment of airbags, or any
- -- other applications that could lead to death, personal
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- -- (individually and collectively, "Critical
- -- Applications"). Customer assumes the sole risk and
- -- liability of any use of Xilinx products in Critical
- -- Applications, subject only to applicable laws and
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- --
- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- -- PART OF THIS FILE AT ALL TIMES.
- --
- ------------------------------------------------------------------------------
- -- User entered comments
- ------------------------------------------------------------------------------
- -- None
- --
- ------------------------------------------------------------------------------
- -- Output Output Phase Duty Cycle Pk-to-Pk Phase
- -- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
- ------------------------------------------------------------------------------
- -- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
- --
- ------------------------------------------------------------------------------
- -- Input Clock Freq (MHz) Input Jitter (UI)
- ------------------------------------------------------------------------------
- -- __primary_________100.000____________0.010
-
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- use ieee.std_logic_arith.all;
- use ieee.numeric_std.all;
-
- library unisim;
- use unisim.vcomponents.all;
-
- entity clk_wiz_0 is
- port
- (-- Clock in ports
- clk_in1 : in std_logic;
- -- Clock out ports
- clk_out1 : out std_logic
- );
- end clk_wiz_0;
-
- architecture xilinx of clk_wiz_0 is
- attribute CORE_GENERATION_INFO : string;
- attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
-
- component clk_wiz_0_clk_wiz
- port
- (-- Clock in ports
- clk_in1 : in std_logic;
- -- Clock out ports
- clk_out1 : out std_logic
- );
- end component;
-
- begin
-
- U0: clk_wiz_0_clk_wiz
- port map (
-
- -- Clock in ports
- clk_in1 => clk_in1,
- -- Clock out ports
- clk_out1 => clk_out1
- );
-
- end xilinx;
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