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@ -2,23 +2,987 @@
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# Vivado v2016.4 (64-bit)
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# SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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# Start of session at: Mon May 03 15:56:37 2021
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# Process ID: 5172
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# Start of session at: Mon May 10 16:43:40 2021
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# Process ID: 13872
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# Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15260 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
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# Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
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# Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
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#-----------------------------------------------------------
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start_gui
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open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
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INFO: [Project 1-313] Project file moved from 'C:/Users/Hp/Documents/Processeur' since last save.
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CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg', nor could it be found using path 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
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CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg', nor could it be found using path 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
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CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
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Scanning sources...
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Finished scanning sources
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
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open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 832.355 ; gain = 177.891
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exit
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INFO: [Common 17-206] Exiting Vivado at Mon May 03 15:58:00 2021...
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open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 839.340 ; gain = 198.637
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launch_simulation
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Pipeline
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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Vivado Simulator 2016.4
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Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.std_logic_arith
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Compiling package ieee.std_logic_unsigned
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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Built simulation snapshot Test_Pipeline_behav
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****** Webtalk v2016.4 (64-bit)
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**** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
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**** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
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** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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source C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
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INFO: [Common 17-206] Exiting Webtalk at Mon May 10 17:15:25 2021...
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INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
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INFO: [USF-XSim-4] XSim::Simulate design
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WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
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WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
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WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
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WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
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INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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INFO: [USF-XSim-98] *** Running xsim
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with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
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INFO: [USF-XSim-8] Loading simulator feature
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Vivado Simulator 2016.4
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Time resolution is 1 ps
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source Test_Pipeline.tcl
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# set curr_wave [current_wave_config]
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# if { [string length $curr_wave] == 0 } {
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# if { [llength [get_objects]] > 0} {
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# add_wave /
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# set_property needs_save false [current_wave_config]
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# } else {
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# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
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# }
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# }
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# run 1000ns
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ERROR: Index 191 out of bound 127 downto 0
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Time: 10 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/line__68
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd:68
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INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
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INFO: [USF-XSim-97] XSim simulation ran for 1000ns
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launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 872.664 ; gain = 3.988
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relaunch_sim
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Pipeline
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
|
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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Vivado Simulator 2016.4
|
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Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.std_logic_arith
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Compiling package ieee.std_logic_unsigned
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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Built simulation snapshot Test_Pipeline_behav
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INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
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|
Vivado Simulator 2016.4
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Time resolution is 1 ps
|
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ERROR: Array sizes do not match, left array has 5 elements, right array has 8 elements
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Time: 0 ps Iteration: 0 Process: /Test_Pipeline/instance/instance_Etage4/line__190
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd:190
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relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 884.223 ; gain = 0.000
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relaunch_sim
|
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
|
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
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INFO: [USF-XSim-2] XSim::Compile design
|
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
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|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Pipeline
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
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|
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
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|
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INFO: [USF-XSim-3] XSim::Elaborate design
|
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
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|
Vivado Simulator 2016.4
|
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|
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Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
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|
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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|
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Using 2 slave threads.
|
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Starting static elaboration
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Completed static elaboration
|
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Starting simulation data flow analysis
|
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
|
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Compiling package ieee.std_logic_1164
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Compiling package ieee.std_logic_arith
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Compiling package ieee.std_logic_unsigned
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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Built simulation snapshot Test_Pipeline_behav
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
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|
Vivado Simulator 2016.4
|
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Time resolution is 1 ps
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ERROR: Index 185 out of bound 95 downto 0
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Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
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relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 886.633 ; gain = 0.000
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restart
|
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INFO: [Simtcl 6-17] Simulation restarted
|
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run 10 us
|
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ERROR: Index 185 out of bound 95 downto 0
|
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Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
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restart
|
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INFO: [Simtcl 6-17] Simulation restarted
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run 10 us
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ERROR: Index 185 out of bound 95 downto 0
|
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Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
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|
restart
|
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INFO: [Simtcl 6-17] Simulation restarted
|
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|
run 10 us
|
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|
ERROR: Index 185 out of bound 95 downto 0
|
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|
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|
Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
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|
File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
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|
restart
|
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INFO: [Simtcl 6-17] Simulation restarted
|
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|
|
run 10 us
|
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|
ERROR: Index 185 out of bound 95 downto 0
|
|
|
|
|
Time: 580 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
|
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|
File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
|
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|
HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
|
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|
relaunch_sim
|
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
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|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
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INFO: [USF-XSim-97] Finding global include files...
|
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
|
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|
INFO: [USF-XSim-2] XSim::Compile design
|
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|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
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|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
|
|
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|
|
INFO: [VRFC 10-307] analyzing entity ALU
|
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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|
|
INFO: [VRFC 10-307] analyzing entity System
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
|
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|
|
|
INFO: [VRFC 10-307] analyzing entity BancRegistres
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
|
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|
|
|
INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
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|
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity MUX
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity LC
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
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|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
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|
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
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|
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
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|
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
|
|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_MUX
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
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|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
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|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
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|
|
INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
|
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|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
|
|
|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
|
|
|
|
Vivado Simulator 2016.4
|
|
|
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
|
|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
|
|
|
Using 2 slave threads.
|
|
|
|
|
Starting static elaboration
|
|
|
|
|
Completed static elaboration
|
|
|
|
|
Starting simulation data flow analysis
|
|
|
|
|
Completed simulation data flow analysis
|
|
|
|
|
Time Resolution for simulation is 1ps
|
|
|
|
|
Compiling package std.standard
|
|
|
|
|
Compiling package std.textio
|
|
|
|
|
Compiling package ieee.std_logic_1164
|
|
|
|
|
Compiling package ieee.std_logic_arith
|
|
|
|
|
Compiling package ieee.std_logic_unsigned
|
|
|
|
|
Compiling package ieee.numeric_std
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
|
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
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|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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Built simulation snapshot Test_Pipeline_behav
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
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Vivado Simulator 2016.4
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Time resolution is 1 ps
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ERROR: Index 185 out of bound 95 downto 0
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Time: 520 ns Iteration: 2 Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
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File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
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HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
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relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
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relaunch_sim
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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ERROR: [VRFC 10-1412] syntax error near begin [C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
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INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd ignored due to errors
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Pipeline
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
|
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INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log'
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ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
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|
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
|
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ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
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ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
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|
relaunch_sim
|
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
|
|
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|
INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
|
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|
|
INFO: [USF-XSim-97] Finding global include files...
|
|
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|
INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
|
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|
INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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|
INFO: [USF-XSim-2] XSim::Compile design
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|
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
|
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|
|
"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Pipeline
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
|
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INFO: [USF-XSim-3] XSim::Elaborate design
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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|
Vivado Simulator 2016.4
|
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|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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Compiling package ieee.std_logic_arith
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Compiling package ieee.std_logic_unsigned
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
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Built simulation snapshot Test_Pipeline_behav
|
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
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|
Vivado Simulator 2016.4
|
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|
Time resolution is 1 ps
|
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relaunch_sim
|
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Pipeline
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Clock_Divider
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestBancRegistres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_LC
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_MUX
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity Test_Pipeline
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INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
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INFO: [USF-XSim-3] XSim::Elaborate design
|
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INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
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|
Vivado Simulator 2016.4
|
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|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
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|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
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|
Using 2 slave threads.
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|
Starting static elaboration
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|
Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling package std.standard
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Compiling package std.textio
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Compiling package ieee.std_logic_1164
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|
Compiling package ieee.std_logic_arith
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Compiling package ieee.std_logic_unsigned
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Compiling package ieee.numeric_std
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Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
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Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
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Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
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Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
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Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
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Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
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Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
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Built simulation snapshot Test_Pipeline_behav
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INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
|
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|
|
Vivado Simulator 2016.4
|
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|
Time resolution is 1 ps
|
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relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
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restart
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INFO: [Simtcl 6-17] Simulation restarted
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run 100 us
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reset_run synth_1
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WARNING: [Vivado 12-1017] Problems encountered:
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|
|
1. Failed to delete one or more files in run directory C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1
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launch_runs synth_1 -jobs 2
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[Mon May 10 18:17:42 2021] Launched synth_1...
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|
Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1/runme.log
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|
launch_runs impl_1 -jobs 2
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|
[Mon May 10 18:20:21 2021] Launched impl_1...
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|
|
Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
|
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|
launch_runs impl_1 -to_step write_bitstream -jobs 2
|
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[Mon May 10 18:21:46 2021] Launched impl_1...
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|
Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
|
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open_hw
|
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connect_hw_server
|
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INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
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INFO: [Labtools 27-2222] Launching hw_server...
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INFO: [Labtools 27-2221] Launch Output:
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|
****** Xilinx hw_server v2016.4
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|
**** Build date : Jan 23 2017-19:37:29
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|
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
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open_hw_target
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INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
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set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
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|
current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
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|
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
|
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|
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
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WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
|
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|
|
Resolution:
|
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|
|
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
|
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|
|
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
|
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|
set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
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|
set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
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|
program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
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|
INFO: [Labtools 27-3164] End of startup status: HIGH
|
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|
refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
|
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|
INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
|
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|
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
|
|
|
|
|
Resolution:
|
|
|
|
|
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
|
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2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
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WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
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WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
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WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
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WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
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restart
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INFO: [Simtcl 6-17] Simulation restarted
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run 100 us
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restart
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INFO: [Simtcl 6-17] Simulation restarted
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run 100 us
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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restart
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INFO: [Simtcl 6-17] Simulation restarted
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run 100 us
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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restart
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INFO: [Simtcl 6-17] Simulation restarted
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run 100 us
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
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ERROR: [Wavedata 42-440] There is no current wave configuration open to save
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ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
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Check cable connectivity and that the target board is powered up then
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use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
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ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
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close_hw
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relaunch_sim
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INFO: [SIM-utils-51] Simulation object is 'sim_1'
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INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
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INFO: [USF-XSim-97] Finding global include files...
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INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
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INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
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INFO: [USF-XSim-2] XSim::Compile design
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INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
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"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity ALU
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity System
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity BancRegistres
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
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INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity MemoireInstructions
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity MemoireDonnees
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity MUX
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity LC
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
|
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|
|
INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
|
|
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|
INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
|
|
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|
|
INFO: [VRFC 10-307] analyzing entity Pipeline
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
|
|
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|
|
INFO: [VRFC 10-307] analyzing entity Clock_Divider
|
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
|
|
|
|
|
INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
|
|
|
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|
INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
|
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|
|
|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
|
|
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|
INFO: [VRFC 10-307] analyzing entity TestBancRegistres
|
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|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
|
|
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|
|
INFO: [VRFC 10-307] analyzing entity TestALU
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity Test_LC
|
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_MUX
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
|
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
|
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INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
|
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INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
|
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|
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
|
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|
INFO: [VRFC 10-307] analyzing entity Test_Pipeline
|
|
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|
|
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
|
|
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|
|
INFO: [USF-XSim-3] XSim::Elaborate design
|
|
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|
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
|
|
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|
|
Vivado Simulator 2016.4
|
|
|
|
|
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
|
|
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|
|
Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log
|
|
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|
|
Using 2 slave threads.
|
|
|
|
|
Starting static elaboration
|
|
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|
|
Completed static elaboration
|
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|
|
Starting simulation data flow analysis
|
|
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|
|
Completed simulation data flow analysis
|
|
|
|
|
Time Resolution for simulation is 1ps
|
|
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|
|
Compiling package std.standard
|
|
|
|
|
Compiling package std.textio
|
|
|
|
|
Compiling package ieee.std_logic_1164
|
|
|
|
|
Compiling package ieee.std_logic_arith
|
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|
|
Compiling package ieee.std_logic_unsigned
|
|
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|
|
Compiling package ieee.numeric_std
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
|
|
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|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
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|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
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|
Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
|
|
|
|
|
Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
|
|
|
|
|
Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
|
|
|
|
|
Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
|
|
|
|
|
Built simulation snapshot Test_Pipeline_behav
|
|
|
|
|
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
|
|
|
|
|
Vivado Simulator 2016.4
|
|
|
|
|
Time resolution is 1 ps
|
|
|
|
|