Browse Source

Processeur finito

Paul Faure 4 months ago
parent
commit
73a2d861b7

+ 2
- 1
Processeur.srcs/sim_1/new/Test_Pipeline.vhd View File

@@ -63,6 +63,8 @@ architecture Behavioral of Test_Pipeline is
63 63
     
64 64
 begin
65 65
     instance : Pipeline
66
+    generic map (Addr_Memoire_Instruction_Size => 7,
67
+                 Memoire_Instruction_Size => 128)
66 68
     port map (CLK => my_CLK,
67 69
               RST => my_RST,
68 70
               STD_IN => my_STD_IN,
@@ -78,7 +80,6 @@ begin
78 80
     
79 81
     process 
80 82
     begin
81
-        my_RST <= '0' after 34 ns, '1' after 57 ns;
82 83
         wait;
83 84
     end process;
84 85
 end Behavioral;

+ 6
- 5
Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd View File

@@ -34,6 +34,7 @@ use IEEE.STD_LOGIC_1164.ALL;
34 34
 entity Etage2_5_Registres is
35 35
     Generic ( Nb_bits : Natural;
36 36
               Nb_registres : Natural;
37
+              Addr_registres_size : Natural;
37 38
               Instruction_bus_size : Natural;
38 39
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
39 40
               Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
@@ -130,12 +131,12 @@ begin
130 131
 
131 132
     instance_BancRegistres : BancRegistres
132 133
     generic map (Nb_bits => Nb_bits,
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-                 Addr_size => Nb_bits,
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+                 Addr_size => Addr_registres_size,
134 135
                  Nb_regs => Nb_registres)
135
-    port map ( AddrA => IN_2_A,
136
-               AddrB => IN_2_B,
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-               AddrC => IN_2_C,
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-               AddrW => IN_5_A,
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+    port map ( AddrA => IN_2_A(Addr_registres_size - 1 downto 0),
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+               AddrB => IN_2_B(Addr_registres_size - 1 downto 0),
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+               AddrC => IN_2_C(Addr_registres_size - 1 downto 0),
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+               AddrW => IN_5_A(Addr_registres_size - 1 downto 0),
139 140
                W => Commande_BancRegistres(0),
140 141
                DATA => Entree_BancRegistre_DATA,
141 142
                RST => RST,

+ 14
- 11
Processeur.srcs/sources_1/new/Etage4_Memoire.vhd View File

@@ -35,6 +35,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
35 35
 entity Etage4_Memoire is
36 36
     Generic ( Nb_bits : Natural;
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               Mem_size : Natural;
38
+              Adresse_mem_size : Natural;
38 39
               Instruction_bus_size : Natural;
39 40
               Mem_EBP_size : Natural;
40 41
               Adresse_size_mem_EBP : Natural;
@@ -99,13 +100,14 @@ architecture Structural of Etage4_Memoire is
99 100
                OUTPUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
100 101
     end component;
101 102
     
102
-    signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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-    signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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-    signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
103
+    signal Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
104
+    signal IN_Addr_MemoireDonnees : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
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+    signal Addr_MemoireDonnees_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
105 106
     signal Commande_MemoireDonnees : STD_LOGIC_VECTOR (0 downto 0) := "0";
106 107
     signal Sortie_MemoireDonnees : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
107 108
     signal intern_OUT_B : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
108
-    signal EBP : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
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+    signal EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
110
+    signal New_EBP : STD_LOGIC_VECTOR (Adresse_mem_size - 1 downto 0) := (others => '0');
109 111
     signal R_Aux : STD_LOGIC := '0';
110 112
     signal W_Aux : STD_LOGIC := '0';
111 113
     signal E : STD_LOGIC;
@@ -121,16 +123,16 @@ begin
121 123
                  Commande => Commande_MemoireDonnees);
122 124
                  
123 125
     instance_MUX_IN : MUX
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-    generic map (Nb_bits => Nb_bits,
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+    generic map (Nb_bits => Adresse_mem_size,
125 127
                  Instruction_Vector_Size => Instruction_bus_size,
126 128
                  Bits_Controle => Bits_Controle_MUX_IN)
127 129
     port map (   Instruction => IN_Instruction,
128
-                 IN1 => IN_A,
129
-                 IN2 => IN_B,
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+                 IN1 => IN_A (Adresse_mem_size - 1 downto 0),
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+                 IN2 => IN_B (Adresse_mem_size - 1 downto 0),
130 132
                  OUTPUT => IN_Addr_MemoireDonnees);
131 133
                  
132 134
     instance_MUX_IN_EBP : MUX
133
-    generic map (Nb_bits => Nb_bits,
135
+    generic map (Nb_bits => Adresse_mem_size,
134 136
                  Instruction_Vector_Size => Instruction_bus_size,
135 137
                  Bits_Controle => Bits_Controle_MUX_IN_EBP)
136 138
     port map (   Instruction => IN_Instruction,
@@ -149,7 +151,7 @@ begin
149 151
 
150 152
     instance_MemoireDonnees : MemoireDonnees
151 153
     generic map (Nb_bits => Nb_bits,
152
-                 Addr_size => Nb_bits,
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+                 Addr_size => Adresse_mem_size,
153 155
                  Mem_size => Mem_size)
154 156
     port map ( Addr => Addr_MemoireDonnees,
155 157
                RW => Commande_MemoireDonnees(0),
@@ -159,13 +161,13 @@ begin
159 161
                D_OUT => Sortie_MemoireDonnees);
160 162
                
161 163
     instance_MemoireEBP : MemoireAdressesRetour
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-    generic map (Nb_bits => Nb_bits,
164
+    generic map (Nb_bits => Adresse_mem_size,
163 165
                  Addr_size => Adresse_size_mem_EBP,
164 166
                  Mem_size => Mem_EBP_size
165 167
     )
166 168
     port map ( R => R_Aux,
167 169
                W => W_Aux,
168
-               D_IN => IN_B,
170
+               D_IN => New_EBP,
169 171
                RST => RST,
170 172
                CLK => CLK,
171 173
                D_OUT => EBP,
@@ -187,4 +189,5 @@ begin
187 189
              '0';
188 190
              
189 191
     Addr_MemoireDonnees_EBP <= IN_Addr_MemoireDonnees + EBP;
192
+    New_EBP <= EBP + IN_B (Adresse_mem_size - 1 downto 0);
190 193
 end Structural;

+ 2
- 2
Processeur.srcs/sources_1/new/MemoireDonnees.vhd View File

@@ -54,9 +54,9 @@ begin
54 54
         else 
55 55
             if (RW = '0') then
56 56
                 MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits - 1) downto Nb_bits * to_integer(unsigned(Addr))) <= D_IN;
57
-            else 
58
-                D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
59 57
             end if;
60 58
         end if;
61 59
     end process;
60
+    
61
+    D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
62 62
 end Behavioral;

+ 2
- 1
Processeur.srcs/sources_1/new/MemoireInstructions.vhd View File

@@ -40,7 +40,8 @@ entity MemoireInstructions is
40 40
 end MemoireInstructions;
41 41
 
42 42
 architecture Behavioral of MemoireInstructions is
43
-    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := "10100"&x"000000"&"10001"&x"020000"&"01111"&x"010000"&"10101"&x"0a0000"&"10001"&x"000000"&"10101"&x"0a0000"&"10001"&x"010000"&"01001"&x"01ff00";
43
+    signal MEMORY : STD_LOGIC_VECTOR ((Mem_Size * Nb_bits)-1 downto 0) := 
44
+  "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "00000000000000000000000000000" & "10101000000000000000000000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "01010000000100000010100000000" & "00010000000000000000100000000" & "01001000000010000000100000000" & "01110000001010000000100000000" & "01001000000010000000000000000" & "01001000000000000000000000000" & "10011000101110000010000000000" & "01011000001010000001100000000" & "01011000000110000001000000000" & "01110000001000000000100000000" & "01001000000010000000000000000" & "01011000001100000000100000000" & "01101000000100000001100000000" & "01001000000110000110000000000" & "00001000000100000000000000010" & "01010000000000000010000000000" & "01011000000100000000000000000" & "00010000000100000000100000010" & "01001000000010000000100000000" & "01110000001000000000100000000" & "01001000000010000000000000000" & "01011000001010000000100000000" & "01001000000100000000100000000" & "01101000000000000001100000000" & "01001000000110000000100000000" & "00001000000000000001000000000" & "01010000000100000001100000000" & "00010000000000000000100000000" & "01001000000010000000100000000" & "01110000000110000000100000000" & "01001000000010000000000000000" & "01001000000000000000000000000" & "10100000000000000000000000000" & "01011000000010000000000000000" & "01011000000000000000100000000" & "01000000000010000000000000000" & "01001000000000000000100000000" & "10011000000010000000100000000" & "01011000000110000001100000000" & "01011000000100000001000000000" & "01011000000010000000000000000" & "01000000000000000000100000000" & "01101000000000000001000000000" & "01001000000100000101000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01001000000000000000100000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01010000000010000000000000000" & "01001000000000000000000000000" & "10100000000000000000000000000" & "01011000000110000001100000000" & "01011000000100000001000000000" & "01011000000010000000000000000" & "01011000000000000000100000000" & "01000000000010000000000000000" & "01001000000000000001000000000" & "01101000000000000001000000000" & "01001000000100000111000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01001000000000000000000000000" & "10001000000000000000000000000" & "01100000000000000000000000000" & "00001000000000000001000000000" & "00010000000000000001100000000" & "01001000000110000000100000000" & "01000000000100000000100000000" & "01010000000010000000000000000" & "01001000000000000000100000000" & "01111001100000000000000000000";
44 45
 begin
45 46
     D_OUT <= MEMORY (((to_integer(unsigned(Addr)) + 1) * Nb_bits) - 1 downto Nb_bits * to_integer(unsigned(Addr)));
46 47
 end Behavioral;

+ 7
- 1
Processeur.srcs/sources_1/new/Pipeline.vhd View File

@@ -39,7 +39,9 @@ entity Pipeline is
39 39
              Instruction_Bus_Size : Natural := 5;
40 40
              Nb_Instructions : Natural := 32;
41 41
              Nb_Registres : Natural := 16;
42
+             Addr_registres_size : Natural := 4;
42 43
              Memoire_Size : Natural := 32;
44
+             Adresse_mem_size : Natural := 5;
43 45
              Memoire_Adresses_Retour_Size : Natural := 16;
44 46
              Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
45 47
     Port (CLK : STD_LOGIC;
@@ -80,6 +82,7 @@ architecture Behavioral of Pipeline is
80 82
     component Etage2_5_Registres is
81 83
     Generic ( Nb_bits : Natural;
82 84
               Nb_registres : Natural;
85
+              Addr_registres_size : Natural;
83 86
               Instruction_bus_size : Natural;
84 87
               Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
85 88
               Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
@@ -125,6 +128,7 @@ architecture Behavioral of Pipeline is
125 128
     component Etage4_Memoire is
126 129
         Generic ( Nb_bits : Natural;
127 130
                   Mem_size : Natural;
131
+                  Adresse_mem_size : Natural;
128 132
                   Instruction_bus_size : Natural;
129 133
                   Mem_EBP_size : Natural;
130 134
                   Adresse_size_mem_EBP : Natural;
@@ -183,7 +187,7 @@ architecture Behavioral of Pipeline is
183 187
     constant Bits_Controle_MUX_3        : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
184 188
     constant Bits_Controle_LC_4         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
185 189
     constant Bits_Controle_MUX_4_IN     : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
186
-    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111100001111111111";
190
+    constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
187 191
     constant Bits_Controle_MUX_4_OUT    : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
188 192
     constant Bits_Controle_LC_5         : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
189 193
     constant Code_Instruction_JMP  : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
@@ -231,6 +235,7 @@ begin
231 235
     instance_Etage2_5 : Etage2_5_Registres
232 236
     generic map( Nb_bits => Nb_bits,
233 237
                  Nb_Registres => Nb_Registres,
238
+                 Addr_registres_size => Addr_registres_size,
234 239
                  Instruction_bus_size => Instruction_Bus_Size,
235 240
                  Bits_Controle_LC_5 => Bits_Controle_LC_5,
236 241
                  Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
@@ -278,6 +283,7 @@ begin
278 283
     instance_Etage4 : Etage4_Memoire
279 284
     generic map( Nb_bits => Nb_bits,
280 285
                  Mem_size => Memoire_Size,
286
+                 Adresse_mem_size => Adresse_mem_size,
281 287
                  Instruction_bus_size => Instruction_Bus_Size,
282 288
                  Mem_EBP_size => Memoire_Adresses_Retour_Size,
283 289
                  Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,

+ 2
- 0
Processeur.srcs/sources_1/new/System.vhd View File

@@ -75,6 +75,8 @@ begin
75 75
               CLK_OUT => my_CLK);
76 76
               
77 77
     instance : Pipeline
78
+    generic map (Addr_Memoire_Instruction_Size => 7,
79
+                 Memoire_Instruction_Size => 128)
78 80
     port map (CLK => my_CLK,
79 81
               RST => my_RST,
80 82
               STD_IN => sw,

+ 1
- 1
Processeur.xpr View File

@@ -32,7 +32,7 @@
32 32
     <Option Name="EnableBDX" Val="FALSE"/>
33 33
     <Option Name="DSABoardId" Val="basys3"/>
34 34
     <Option Name="DSANumComputeUnits" Val="16"/>
35
-    <Option Name="WTXSimLaunchSim" Val="176"/>
35
+    <Option Name="WTXSimLaunchSim" Val="230"/>
36 36
     <Option Name="WTModelSimLaunchSim" Val="0"/>
37 37
     <Option Name="WTQuestaLaunchSim" Val="0"/>
38 38
     <Option Name="WTIesLaunchSim" Val="0"/>

+ 165
- 0
Test_Pipeline_behav1.wcfg View File

@@ -0,0 +1,165 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<wave_config>
3
+   <wave_state>
4
+   </wave_state>
5
+   <db_ref_list>
6
+      <db_ref path="Test_Pipeline_behav1.wdb" id="1">
7
+         <top_modules>
8
+            <top_module name="Test_Pipeline" />
9
+         </top_modules>
10
+      </db_ref>
11
+   </db_ref_list>
12
+   <zoom_setting>
13
+      <ZoomStartTime time="320666666fs"></ZoomStartTime>
14
+      <ZoomEndTime time="441266667fs"></ZoomEndTime>
15
+      <Cursor1Time time="404267000fs"></Cursor1Time>
16
+   </zoom_setting>
17
+   <column_width_setting>
18
+      <NameColumnWidth column_width="146"></NameColumnWidth>
19
+      <ValueColumnWidth column_width="73"></ValueColumnWidth>
20
+   </column_width_setting>
21
+   <WVObjectSize size="10" />
22
+   <wvobject fp_name="/Test_Pipeline/my_CLK" type="logic">
23
+      <obj_property name="ElementShortName">my_CLK</obj_property>
24
+      <obj_property name="ObjectShortName">my_CLK</obj_property>
25
+   </wvobject>
26
+   <wvobject fp_name="/Test_Pipeline/my_RST" type="logic">
27
+      <obj_property name="ElementShortName">my_RST</obj_property>
28
+      <obj_property name="ObjectShortName">my_RST</obj_property>
29
+   </wvobject>
30
+   <wvobject fp_name="/Test_Pipeline/my_STD_IN" type="array">
31
+      <obj_property name="ElementShortName">my_STD_IN[7:0]</obj_property>
32
+      <obj_property name="ObjectShortName">my_STD_IN[7:0]</obj_property>
33
+   </wvobject>
34
+   <wvobject fp_name="/Test_Pipeline/my_STD_OUT" type="array">
35
+      <obj_property name="ElementShortName">my_STD_OUT[7:0]</obj_property>
36
+      <obj_property name="ObjectShortName">my_STD_OUT[7:0]</obj_property>
37
+   </wvobject>
38
+   <wvobject fp_name="/Test_Pipeline/CLK_period" type="other">
39
+      <obj_property name="ElementShortName">CLK_period</obj_property>
40
+      <obj_property name="ObjectShortName">CLK_period</obj_property>
41
+   </wvobject>
42
+   <wvobject fp_name="group20" type="group">
43
+      <obj_property name="label">Etage1</obj_property>
44
+      <obj_property name="DisplayName">label</obj_property>
45
+      <obj_property name="isExpanded"></obj_property>
46
+      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_1" type="array">
47
+         <obj_property name="ElementShortName">Instruction_from_1[4:0]</obj_property>
48
+         <obj_property name="ObjectShortName">Instruction_from_1[4:0]</obj_property>
49
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
50
+      </wvobject>
51
+      <wvobject fp_name="/Test_Pipeline/instance/A_from_1" type="array">
52
+         <obj_property name="ElementShortName">A_from_1[7:0]</obj_property>
53
+         <obj_property name="ObjectShortName">A_from_1[7:0]</obj_property>
54
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
55
+      </wvobject>
56
+      <wvobject fp_name="/Test_Pipeline/instance/B_from_1" type="array">
57
+         <obj_property name="ElementShortName">B_from_1[7:0]</obj_property>
58
+         <obj_property name="ObjectShortName">B_from_1[7:0]</obj_property>
59
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
60
+      </wvobject>
61
+      <wvobject fp_name="/Test_Pipeline/instance/C_from_1" type="array">
62
+         <obj_property name="ElementShortName">C_from_1[7:0]</obj_property>
63
+         <obj_property name="ObjectShortName">C_from_1[7:0]</obj_property>
64
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
65
+      </wvobject>
66
+   </wvobject>
67
+   <wvobject fp_name="group21" type="group">
68
+      <obj_property name="label">Etage2</obj_property>
69
+      <obj_property name="DisplayName">label</obj_property>
70
+      <obj_property name="isExpanded"></obj_property>
71
+      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_2" type="array">
72
+         <obj_property name="ElementShortName">Instruction_from_2[4:0]</obj_property>
73
+         <obj_property name="ObjectShortName">Instruction_from_2[4:0]</obj_property>
74
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
75
+      </wvobject>
76
+      <wvobject fp_name="/Test_Pipeline/instance/A_from_2" type="array">
77
+         <obj_property name="ElementShortName">A_from_2[7:0]</obj_property>
78
+         <obj_property name="ObjectShortName">A_from_2[7:0]</obj_property>
79
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
80
+      </wvobject>
81
+      <wvobject fp_name="/Test_Pipeline/instance/B_from_2" type="array">
82
+         <obj_property name="ElementShortName">B_from_2[7:0]</obj_property>
83
+         <obj_property name="ObjectShortName">B_from_2[7:0]</obj_property>
84
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
85
+      </wvobject>
86
+      <wvobject fp_name="/Test_Pipeline/instance/C_from_2" type="array">
87
+         <obj_property name="ElementShortName">C_from_2[7:0]</obj_property>
88
+         <obj_property name="ObjectShortName">C_from_2[7:0]</obj_property>
89
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
90
+      </wvobject>
91
+   </wvobject>
92
+   <wvobject fp_name="group22" type="group">
93
+      <obj_property name="label">Etage3</obj_property>
94
+      <obj_property name="DisplayName">label</obj_property>
95
+      <obj_property name="isExpanded"></obj_property>
96
+      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_3" type="array">
97
+         <obj_property name="ElementShortName">Instruction_from_3[4:0]</obj_property>
98
+         <obj_property name="ObjectShortName">Instruction_from_3[4:0]</obj_property>
99
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
100
+      </wvobject>
101
+      <wvobject fp_name="/Test_Pipeline/instance/A_from_3" type="array">
102
+         <obj_property name="ElementShortName">A_from_3[7:0]</obj_property>
103
+         <obj_property name="ObjectShortName">A_from_3[7:0]</obj_property>
104
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
105
+      </wvobject>
106
+      <wvobject fp_name="/Test_Pipeline/instance/B_from_3" type="array">
107
+         <obj_property name="ElementShortName">B_from_3[7:0]</obj_property>
108
+         <obj_property name="ObjectShortName">B_from_3[7:0]</obj_property>
109
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
110
+      </wvobject>
111
+   </wvobject>
112
+   <wvobject fp_name="group23" type="group">
113
+      <obj_property name="label">Etage4</obj_property>
114
+      <obj_property name="DisplayName">label</obj_property>
115
+      <obj_property name="isExpanded"></obj_property>
116
+      <wvobject fp_name="/Test_Pipeline/instance/Instruction_from_4" type="array">
117
+         <obj_property name="ElementShortName">Instruction_from_4[4:0]</obj_property>
118
+         <obj_property name="ObjectShortName">Instruction_from_4[4:0]</obj_property>
119
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
120
+      </wvobject>
121
+      <wvobject fp_name="/Test_Pipeline/instance/A_from_4" type="array">
122
+         <obj_property name="ElementShortName">A_from_4[7:0]</obj_property>
123
+         <obj_property name="ObjectShortName">A_from_4[7:0]</obj_property>
124
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
125
+      </wvobject>
126
+      <wvobject fp_name="/Test_Pipeline/instance/B_from_4" type="array">
127
+         <obj_property name="ElementShortName">B_from_4[7:0]</obj_property>
128
+         <obj_property name="ObjectShortName">B_from_4[7:0]</obj_property>
129
+         <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
130
+      </wvobject>
131
+   </wvobject>
132
+   <wvobject fp_name="group31" type="group">
133
+      <obj_property name="label">Registres</obj_property>
134
+      <obj_property name="DisplayName">label</obj_property>
135
+      <obj_property name="isExpanded"></obj_property>
136
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/REGISTRES" type="array">
137
+         <obj_property name="ElementShortName">REGISTRES[127:0]</obj_property>
138
+         <obj_property name="ObjectShortName">REGISTRES[127:0]</obj_property>
139
+      </wvobject>
140
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrA" type="array">
141
+         <obj_property name="ElementShortName">AddrA[3:0]</obj_property>
142
+         <obj_property name="ObjectShortName">AddrA[3:0]</obj_property>
143
+      </wvobject>
144
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrB" type="array">
145
+         <obj_property name="ElementShortName">AddrB[3:0]</obj_property>
146
+         <obj_property name="ObjectShortName">AddrB[3:0]</obj_property>
147
+      </wvobject>
148
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrC" type="array">
149
+         <obj_property name="ElementShortName">AddrC[3:0]</obj_property>
150
+         <obj_property name="ObjectShortName">AddrC[3:0]</obj_property>
151
+      </wvobject>
152
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/AddrW" type="array">
153
+         <obj_property name="ElementShortName">AddrW[3:0]</obj_property>
154
+         <obj_property name="ObjectShortName">AddrW[3:0]</obj_property>
155
+      </wvobject>
156
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/W" type="logic">
157
+         <obj_property name="ElementShortName">W</obj_property>
158
+         <obj_property name="ObjectShortName">W</obj_property>
159
+      </wvobject>
160
+      <wvobject fp_name="/Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/DATA" type="array">
161
+         <obj_property name="ElementShortName">DATA[7:0]</obj_property>
162
+         <obj_property name="ObjectShortName">DATA[7:0]</obj_property>
163
+      </wvobject>
164
+   </wvobject>
165
+</wave_config>

+ 55
- 3
vivado.jou View File

@@ -2,12 +2,64 @@
2 2
 # Vivado v2016.4 (64-bit)
3 3
 # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4 4
 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Mon May 03 15:56:37 2021
6
-# Process ID: 5172
5
+# Start of session at: Mon May 10 16:43:40 2021
6
+# Process ID: 13872
7 7
 # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15260 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
8
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
9 9
 # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
10 10
 # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
11 11
 #-----------------------------------------------------------
12 12
 start_gui
13 13
 open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
14
+launch_simulation
15
+source Test_Pipeline.tcl
16
+relaunch_sim
17
+relaunch_sim
18
+restart
19
+run 10 us
20
+restart
21
+run 10 us
22
+restart
23
+run 10 us
24
+restart
25
+run 10 us
26
+relaunch_sim
27
+relaunch_sim
28
+relaunch_sim
29
+relaunch_sim
30
+restart
31
+run 100 us
32
+reset_run synth_1
33
+launch_runs synth_1 -jobs 2
34
+wait_on_run synth_1
35
+launch_runs impl_1 -jobs 2
36
+wait_on_run impl_1
37
+launch_runs impl_1 -to_step write_bitstream -jobs 2
38
+wait_on_run impl_1
39
+open_hw
40
+connect_hw_server
41
+open_hw_target
42
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
43
+current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
44
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
45
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
46
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
47
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
48
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
49
+restart
50
+run 100 us
51
+restart
52
+run 100 us
53
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
54
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
55
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
56
+restart
57
+run 100 us
58
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
59
+restart
60
+run 100 us
61
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
62
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
63
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
64
+close_hw
65
+relaunch_sim

+ 973
- 9
vivado.log View File

@@ -2,23 +2,987 @@
2 2
 # Vivado v2016.4 (64-bit)
3 3
 # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
4 4
 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
5
-# Start of session at: Mon May 03 15:56:37 2021
6
-# Process ID: 5172
5
+# Start of session at: Mon May 10 16:43:40 2021
6
+# Process ID: 13872
7 7
 # Current directory: C:/Users/Hp/Documents/Compteur8BitsBasys3
8
-# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent15260 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
8
+# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent1028 C:\Users\Hp\Documents\Compteur8BitsBasys3\Processeur.xpr
9 9
 # Log file: C:/Users/Hp/Documents/Compteur8BitsBasys3/vivado.log
10 10
 # Journal file: C:/Users/Hp/Documents/Compteur8BitsBasys3\vivado.jou
11 11
 #-----------------------------------------------------------
12 12
 start_gui
13 13
 open_project C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.xpr
14
-INFO: [Project 1-313] Project file moved from 'C:/Users/Hp/Documents/Processeur' since last save.
15
-CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg', nor could it be found using path 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
16
-CRITICAL WARNING: [Project 1-311] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg', nor could it be found using path 'C:/Users/Hp/Documents/Processeur/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
14
+CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg'.
15
+CRITICAL WARNING: [Project 1-19] Could not find the file 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg'.
17 16
 Scanning sources...
18 17
 Finished scanning sources
19 18
 INFO: [IP_Flow 19-234] Refreshing IP repositories
20 19
 INFO: [IP_Flow 19-1704] No user IP repositories specified
21 20
 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2016.4/data/ip'.
22
-open_project: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 832.355 ; gain = 177.891
23
-exit
24
-INFO: [Common 17-206] Exiting Vivado at Mon May 03 15:58:00 2021...
21
+open_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 839.340 ; gain = 198.637
22
+launch_simulation
23
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
24
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
25
+INFO: [USF-XSim-97] Finding global include files...
26
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
27
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
28
+INFO: [USF-XSim-2] XSim::Compile design
29
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
30
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
31
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
32
+INFO: [VRFC 10-307] analyzing entity ALU
33
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
34
+INFO: [VRFC 10-307] analyzing entity System
35
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
36
+INFO: [VRFC 10-307] analyzing entity BancRegistres
37
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
38
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
39
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
40
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
41
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
42
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
43
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
44
+INFO: [VRFC 10-307] analyzing entity MUX
45
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
46
+INFO: [VRFC 10-307] analyzing entity LC
47
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
48
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
49
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
50
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
51
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
52
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
53
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
54
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
55
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
56
+INFO: [VRFC 10-307] analyzing entity Pipeline
57
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
58
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
59
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
60
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
61
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
62
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
63
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
64
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
65
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
66
+INFO: [VRFC 10-307] analyzing entity TestALU
67
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
68
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
69
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
70
+INFO: [VRFC 10-307] analyzing entity Test_LC
71
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
72
+INFO: [VRFC 10-307] analyzing entity Test_MUX
73
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
74
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
75
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
76
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
77
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
78
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
79
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
80
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
81
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
82
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
83
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
84
+INFO: [USF-XSim-3] XSim::Elaborate design
85
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
86
+Vivado Simulator 2016.4
87
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
88
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
89
+Using 2 slave threads.
90
+Starting static elaboration
91
+Completed static elaboration
92
+Starting simulation data flow analysis
93
+Completed simulation data flow analysis
94
+Time Resolution for simulation is 1ps
95
+Compiling package std.standard
96
+Compiling package std.textio
97
+Compiling package ieee.std_logic_1164
98
+Compiling package ieee.std_logic_arith
99
+Compiling package ieee.std_logic_unsigned
100
+Compiling package ieee.numeric_std
101
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
102
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
103
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
104
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
105
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
106
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
107
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
108
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
109
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
110
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
111
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
112
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
113
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
114
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
115
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
116
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
117
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
118
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
119
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
120
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
121
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
122
+Built simulation snapshot Test_Pipeline_behav
123
+
124
+****** Webtalk v2016.4 (64-bit)
125
+  **** SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017
126
+  **** IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
127
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
128
+
129
+source C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/xsim_webtalk.tcl -notrace
130
+INFO: [Common 17-206] Exiting Webtalk at Mon May 10 17:15:25 2021...
131
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
132
+INFO: [USF-XSim-4] XSim::Simulate design
133
+WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
134
+WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
135
+WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xsim.dir/Test_Pipeline_behav/webtalk/Test_Pipeline_behav.wcfg
136
+WARNING: [USF-XSim-17] WCFG file does not exist:C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg
137
+INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
138
+INFO: [USF-XSim-98] *** Running xsim
139
+   with args "Test_Pipeline_behav -key {Behavioral:sim_1:Functional:Test_Pipeline} -tclbatch {Test_Pipeline.tcl} -log {simulate.log}"
140
+INFO: [USF-XSim-8] Loading simulator feature
141
+Vivado Simulator 2016.4
142
+Time resolution is 1 ps
143
+source Test_Pipeline.tcl
144
+# set curr_wave [current_wave_config]
145
+# if { [string length $curr_wave] == 0 } {
146
+#   if { [llength [get_objects]] > 0} {
147
+#     add_wave /
148
+#     set_property needs_save false [current_wave_config]
149
+#   } else {
150
+#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
151
+#   }
152
+# }
153
+# run 1000ns
154
+ERROR: Index 191 out of bound 127 downto 0
155
+Time: 10 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage2_5/instance_BancRegistres/line__68
156
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd
157
+
158
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd:68
159
+INFO: [USF-XSim-96] XSim completed. Design snapshot 'Test_Pipeline_behav' loaded.
160
+INFO: [USF-XSim-97] XSim simulation ran for 1000ns
161
+launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 872.664 ; gain = 3.988
162
+relaunch_sim
163
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
164
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
165
+INFO: [USF-XSim-97] Finding global include files...
166
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
167
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
168
+INFO: [USF-XSim-2] XSim::Compile design
169
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
170
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
171
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
172
+INFO: [VRFC 10-307] analyzing entity ALU
173
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
174
+INFO: [VRFC 10-307] analyzing entity System
175
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
176
+INFO: [VRFC 10-307] analyzing entity BancRegistres
177
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
178
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
179
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
180
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
181
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
182
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
183
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
184
+INFO: [VRFC 10-307] analyzing entity MUX
185
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
186
+INFO: [VRFC 10-307] analyzing entity LC
187
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
188
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
189
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
190
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
191
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
192
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
193
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
194
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
195
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
196
+INFO: [VRFC 10-307] analyzing entity Pipeline
197
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
198
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
199
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
200
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
201
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
202
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
203
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
204
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
205
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
206
+INFO: [VRFC 10-307] analyzing entity TestALU
207
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
208
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
209
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
210
+INFO: [VRFC 10-307] analyzing entity Test_LC
211
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
212
+INFO: [VRFC 10-307] analyzing entity Test_MUX
213
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
214
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
215
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
216
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
217
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
218
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
219
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
220
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
221
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
222
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
223
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
224
+INFO: [USF-XSim-3] XSim::Elaborate design
225
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
226
+Vivado Simulator 2016.4
227
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
228
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
229
+Using 2 slave threads.
230
+Starting static elaboration
231
+Completed static elaboration
232
+Starting simulation data flow analysis
233
+Completed simulation data flow analysis
234
+Time Resolution for simulation is 1ps
235
+Compiling package std.standard
236
+Compiling package std.textio
237
+Compiling package ieee.std_logic_1164
238
+Compiling package ieee.std_logic_arith
239
+Compiling package ieee.std_logic_unsigned
240
+Compiling package ieee.numeric_std
241
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
242
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
243
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
244
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
245
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
246
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
247
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
248
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
249
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
250
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
251
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
252
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
253
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
254
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
255
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
256
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
257
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
258
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=8...]
259
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
260
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
261
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
262
+Built simulation snapshot Test_Pipeline_behav
263
+INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds
264
+Vivado Simulator 2016.4
265
+Time resolution is 1 ps
266
+ERROR: Array sizes do not match, left array has 5 elements, right array has 8 elements
267
+Time: 0 ps  Iteration: 0  Process: /Test_Pipeline/instance/instance_Etage4/line__190
268
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd
269
+
270
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd:190
271
+relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 884.223 ; gain = 0.000
272
+relaunch_sim
273
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
274
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
275
+INFO: [USF-XSim-97] Finding global include files...
276
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
277
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
278
+INFO: [USF-XSim-2] XSim::Compile design
279
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
280
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
281
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
282
+INFO: [VRFC 10-307] analyzing entity ALU
283
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
284
+INFO: [VRFC 10-307] analyzing entity System
285
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
286
+INFO: [VRFC 10-307] analyzing entity BancRegistres
287
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
288
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
289
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
290
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
291
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
292
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
293
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
294
+INFO: [VRFC 10-307] analyzing entity MUX
295
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
296
+INFO: [VRFC 10-307] analyzing entity LC
297
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
298
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
299
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
300
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
301
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
302
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
303
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
304
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
305
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
306
+INFO: [VRFC 10-307] analyzing entity Pipeline
307
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
308
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
309
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
310
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
311
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
312
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
313
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
314
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
315
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
316
+INFO: [VRFC 10-307] analyzing entity TestALU
317
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
318
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
319
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
320
+INFO: [VRFC 10-307] analyzing entity Test_LC
321
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
322
+INFO: [VRFC 10-307] analyzing entity Test_MUX
323
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
324
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
325
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
326
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
327
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
328
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
329
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
330
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
331
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
332
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
333
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
334
+INFO: [USF-XSim-3] XSim::Elaborate design
335
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
336
+Vivado Simulator 2016.4
337
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
338
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
339
+Using 2 slave threads.
340
+Starting static elaboration
341
+Completed static elaboration
342
+Starting simulation data flow analysis
343
+Completed simulation data flow analysis
344
+Time Resolution for simulation is 1ps
345
+Compiling package std.standard
346
+Compiling package std.textio
347
+Compiling package ieee.std_logic_1164
348
+Compiling package ieee.std_logic_arith
349
+Compiling package ieee.std_logic_unsigned
350
+Compiling package ieee.numeric_std
351
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
352
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
353
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
354
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
355
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
356
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
357
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
358
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
359
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
360
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
361
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
362
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
363
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
364
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
365
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
366
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
367
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
368
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
369
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
370
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
371
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
372
+Built simulation snapshot Test_Pipeline_behav
373
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
374
+Vivado Simulator 2016.4
375
+Time resolution is 1 ps
376
+ERROR: Index 185 out of bound 95 downto 0
377
+Time: 580 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
378
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
379
+
380
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
381
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 886.633 ; gain = 0.000
382
+restart
383
+INFO: [Simtcl 6-17] Simulation restarted
384
+run 10 us
385
+ERROR: Index 185 out of bound 95 downto 0
386
+Time: 580 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
387
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
388
+
389
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
390
+restart
391
+INFO: [Simtcl 6-17] Simulation restarted
392
+run 10 us
393
+ERROR: Index 185 out of bound 95 downto 0
394
+Time: 580 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
395
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
396
+
397
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
398
+restart
399
+INFO: [Simtcl 6-17] Simulation restarted
400
+run 10 us
401
+ERROR: Index 185 out of bound 95 downto 0
402
+Time: 580 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
403
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
404
+
405
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
406
+restart
407
+INFO: [Simtcl 6-17] Simulation restarted
408
+run 10 us
409
+ERROR: Index 185 out of bound 95 downto 0
410
+Time: 580 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
411
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
412
+
413
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
414
+relaunch_sim
415
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
416
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
417
+INFO: [USF-XSim-97] Finding global include files...
418
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
419
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
420
+INFO: [USF-XSim-2] XSim::Compile design
421
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
422
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
423
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
424
+INFO: [VRFC 10-307] analyzing entity ALU
425
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
426
+INFO: [VRFC 10-307] analyzing entity System
427
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
428
+INFO: [VRFC 10-307] analyzing entity BancRegistres
429
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
430
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
431
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
432
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
433
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
434
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
435
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
436
+INFO: [VRFC 10-307] analyzing entity MUX
437
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
438
+INFO: [VRFC 10-307] analyzing entity LC
439
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
440
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
441
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
442
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
443
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
444
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
445
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
446
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
447
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
448
+INFO: [VRFC 10-307] analyzing entity Pipeline
449
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
450
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
451
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
452
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
453
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
454
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
455
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
456
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
457
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
458
+INFO: [VRFC 10-307] analyzing entity TestALU
459
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
460
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
461
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
462
+INFO: [VRFC 10-307] analyzing entity Test_LC
463
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
464
+INFO: [VRFC 10-307] analyzing entity Test_MUX
465
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
466
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
467
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
468
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
469
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
470
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
471
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
472
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
473
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
474
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
475
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
476
+INFO: [USF-XSim-3] XSim::Elaborate design
477
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
478
+Vivado Simulator 2016.4
479
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
480
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
481
+Using 2 slave threads.
482
+Starting static elaboration
483
+Completed static elaboration
484
+Starting simulation data flow analysis
485
+Completed simulation data flow analysis
486
+Time Resolution for simulation is 1ps
487
+Compiling package std.standard
488
+Compiling package std.textio
489
+Compiling package ieee.std_logic_1164
490
+Compiling package ieee.std_logic_arith
491
+Compiling package ieee.std_logic_unsigned
492
+Compiling package ieee.numeric_std
493
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
494
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
495
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
496
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
497
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
498
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
499
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
500
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
501
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
502
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
503
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
504
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
505
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
506
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
507
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
508
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
509
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
510
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
511
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
512
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
513
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
514
+Built simulation snapshot Test_Pipeline_behav
515
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
516
+Vivado Simulator 2016.4
517
+Time resolution is 1 ps
518
+ERROR: Index 185 out of bound 95 downto 0
519
+Time: 520 ns  Iteration: 2  Process: /Test_Pipeline/instance/instance_Etage1/instance_MemoireAdressesRetour/line__76
520
+  File: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd
521
+
522
+HDL Line: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd:76
523
+relaunch_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
524
+relaunch_sim
525
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
526
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
527
+INFO: [USF-XSim-97] Finding global include files...
528
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
529
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
530
+INFO: [USF-XSim-2] XSim::Compile design
531
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
532
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
533
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
534
+INFO: [VRFC 10-307] analyzing entity ALU
535
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
536
+INFO: [VRFC 10-307] analyzing entity System
537
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
538
+INFO: [VRFC 10-307] analyzing entity BancRegistres
539
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
540
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
541
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
542
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
543
+ERROR: [VRFC 10-1412] syntax error near begin [C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd:44]
544
+INFO: [VRFC 10-240] VHDL file C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd ignored due to errors
545
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
546
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
547
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
548
+INFO: [VRFC 10-307] analyzing entity MUX
549
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
550
+INFO: [VRFC 10-307] analyzing entity LC
551
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
552
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
553
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
554
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
555
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
556
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
557
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
558
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
559
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
560
+INFO: [VRFC 10-307] analyzing entity Pipeline
561
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
562
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
563
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
564
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
565
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
566
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
567
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
568
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
569
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
570
+INFO: [VRFC 10-307] analyzing entity TestALU
571
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
572
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
573
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
574
+INFO: [VRFC 10-307] analyzing entity Test_LC
575
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
576
+INFO: [VRFC 10-307] analyzing entity Test_MUX
577
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
578
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
579
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
580
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
581
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
582
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
583
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
584
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
585
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
586
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
587
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
588
+INFO: [USF-XSim-99] Step results log file:'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log'
589
+ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/xvhdl.log' file for more information.
590
+ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
591
+ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
592
+ERROR: [Common 17-69] Command failed: ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
593
+
594
+relaunch_sim
595
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
596
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
597
+INFO: [USF-XSim-97] Finding global include files...
598
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
599
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
600
+INFO: [USF-XSim-2] XSim::Compile design
601
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
602
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
603
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
604
+INFO: [VRFC 10-307] analyzing entity ALU
605
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
606
+INFO: [VRFC 10-307] analyzing entity System
607
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
608
+INFO: [VRFC 10-307] analyzing entity BancRegistres
609
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
610
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
611
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
612
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
613
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
614
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
615
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
616
+INFO: [VRFC 10-307] analyzing entity MUX
617
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
618
+INFO: [VRFC 10-307] analyzing entity LC
619
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
620
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
621
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
622
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
623
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
624
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
625
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
626
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
627
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
628
+INFO: [VRFC 10-307] analyzing entity Pipeline
629
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
630
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
631
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
632
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
633
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
634
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
635
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
636
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
637
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
638
+INFO: [VRFC 10-307] analyzing entity TestALU
639
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
640
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
641
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
642
+INFO: [VRFC 10-307] analyzing entity Test_LC
643
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
644
+INFO: [VRFC 10-307] analyzing entity Test_MUX
645
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
646
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
647
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
648
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
649
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
650
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
651
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
652
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
653
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
654
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
655
+INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
656
+INFO: [USF-XSim-3] XSim::Elaborate design
657
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
658
+Vivado Simulator 2016.4
659
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
660
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
661
+Using 2 slave threads.
662
+Starting static elaboration
663
+Completed static elaboration
664
+Starting simulation data flow analysis
665
+Completed simulation data flow analysis
666
+Time Resolution for simulation is 1ps
667
+Compiling package std.standard
668
+Compiling package std.textio
669
+Compiling package ieee.std_logic_1164
670
+Compiling package ieee.std_logic_arith
671
+Compiling package ieee.std_logic_unsigned
672
+Compiling package ieee.numeric_std
673
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
674
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
675
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
676
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
677
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
678
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
679
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
680
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
681
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
682
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
683
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
684
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
685
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
686
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
687
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
688
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
689
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
690
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
691
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
692
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
693
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
694
+Built simulation snapshot Test_Pipeline_behav
695
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
696
+Vivado Simulator 2016.4
697
+Time resolution is 1 ps
698
+relaunch_sim
699
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
700
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
701
+INFO: [USF-XSim-97] Finding global include files...
702
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
703
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
704
+INFO: [USF-XSim-2] XSim::Compile design
705
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
706
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
707
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
708
+INFO: [VRFC 10-307] analyzing entity ALU
709
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
710
+INFO: [VRFC 10-307] analyzing entity System
711
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
712
+INFO: [VRFC 10-307] analyzing entity BancRegistres
713
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
714
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
715
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
716
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
717
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
718
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
719
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
720
+INFO: [VRFC 10-307] analyzing entity MUX
721
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
722
+INFO: [VRFC 10-307] analyzing entity LC
723
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
724
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
725
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
726
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
727
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
728
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
729
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
730
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
731
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
732
+INFO: [VRFC 10-307] analyzing entity Pipeline
733
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
734
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
735
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
736
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
737
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
738
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
739
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
740
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
741
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
742
+INFO: [VRFC 10-307] analyzing entity TestALU
743
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
744
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
745
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
746
+INFO: [VRFC 10-307] analyzing entity Test_LC
747
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
748
+INFO: [VRFC 10-307] analyzing entity Test_MUX
749
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
750
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
751
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
752
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
753
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
754
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
755
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
756
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
757
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
758
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
759
+INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
760
+INFO: [USF-XSim-3] XSim::Elaborate design
761
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
762
+Vivado Simulator 2016.4
763
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
764
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
765
+Using 2 slave threads.
766
+Starting static elaboration
767
+Completed static elaboration
768
+Starting simulation data flow analysis
769
+Completed simulation data flow analysis
770
+Time Resolution for simulation is 1ps
771
+Compiling package std.standard
772
+Compiling package std.textio
773
+Compiling package ieee.std_logic_1164
774
+Compiling package ieee.std_logic_arith
775
+Compiling package ieee.std_logic_unsigned
776
+Compiling package ieee.numeric_std
777
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
778
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
779
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
780
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
781
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
782
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
783
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
784
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
785
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
786
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
787
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
788
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
789
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
790
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
791
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
792
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
793
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
794
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
795
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
796
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
797
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
798
+Built simulation snapshot Test_Pipeline_behav
799
+INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
800
+Vivado Simulator 2016.4
801
+Time resolution is 1 ps
802
+relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 897.563 ; gain = 0.000
803
+restart
804
+INFO: [Simtcl 6-17] Simulation restarted
805
+run 100 us
806
+reset_run synth_1
807
+WARNING: [Vivado 12-1017] Problems encountered:
808
+1. Failed to delete one or more files in run directory C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1
809
+
810
+launch_runs synth_1 -jobs 2
811
+[Mon May 10 18:17:42 2021] Launched synth_1...
812
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/synth_1/runme.log
813
+launch_runs impl_1 -jobs 2
814
+[Mon May 10 18:20:21 2021] Launched impl_1...
815
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
816
+launch_runs impl_1 -to_step write_bitstream -jobs 2
817
+[Mon May 10 18:21:46 2021] Launched impl_1...
818
+Run output will be captured here: C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/runme.log
819
+open_hw
820
+connect_hw_server
821
+INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
822
+INFO: [Labtools 27-2222] Launching hw_server...
823
+INFO: [Labtools 27-2221] Launch Output:
824
+
825
+****** Xilinx hw_server v2016.4
826
+  **** Build date : Jan 23 2017-19:37:29
827
+    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
828
+
829
+
830
+open_hw_target
831
+INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
832
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
833
+current_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
834
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a35t_0] 0]
835
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
836
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
837
+Resolution: 
838
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
839
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
840
+set_property PROBES.FILE {} [lindex [get_hw_devices xc7a35t_0] 0]
841
+set_property PROGRAM.FILE {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.runs/impl_1/System.bit} [lindex [get_hw_devices xc7a35t_0] 0]
842
+program_hw_devices [lindex [get_hw_devices xc7a35t_0] 0]
843
+INFO: [Labtools 27-3164] End of startup status: HIGH
844
+refresh_hw_device [lindex [get_hw_devices xc7a35t_0] 0]
845
+INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
846
+WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
847
+Resolution: 
848
+1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
849
+2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
850
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
851
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
852
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
853
+WARNING: [Labtoolstcl 44-130] No matching hw_ilas were found.
854
+restart
855
+INFO: [Simtcl 6-17] Simulation restarted
856
+run 100 us
857
+restart
858
+INFO: [Simtcl 6-17] Simulation restarted
859
+run 100 us
860
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
861
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
862
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
863
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
864
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
865
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
866
+restart
867
+INFO: [Simtcl 6-17] Simulation restarted
868
+run 100 us
869
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
870
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
871
+restart
872
+INFO: [Simtcl 6-17] Simulation restarted
873
+run 100 us
874
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
875
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
876
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav/Test_Pipeline_behav.wcfg}
877
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
878
+save_wave_config {C:/Users/Hp/Documents/Compteur8BitsBasys3/Test_Pipeline_behav.wcfg}
879
+ERROR: [Wavedata 42-440] There is no current wave configuration open to save
880
+ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA.
881
+Check cable connectivity and that the target board is powered up then
882
+use the disconnect_hw_server and connect_hw_server to re-register this hardware target.
883
+ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210183AB4E4EA
884
+close_hw
885
+relaunch_sim
886
+INFO: [SIM-utils-51] Simulation object is 'sim_1'
887
+INFO: [USF-XSim-37] Inspecting design source files for 'Test_Pipeline' in fileset 'sim_1'...
888
+INFO: [USF-XSim-97] Finding global include files...
889
+INFO: [USF-XSim-100] Fetching design files from 'sources_1'...(this may take a while)...
890
+INFO: [USF-XSim-101] Fetching design files from 'sim_1'...
891
+INFO: [USF-XSim-2] XSim::Compile design
892
+INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
893
+"xvhdl -m64 --relax -prj Test_Pipeline_vhdl.prj"
894
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
895
+INFO: [VRFC 10-307] analyzing entity ALU
896
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/System.vhd" into library xil_defaultlib
897
+INFO: [VRFC 10-307] analyzing entity System
898
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/BancRegistres.vhd" into library xil_defaultlib
899
+INFO: [VRFC 10-307] analyzing entity BancRegistres
900
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireAdressesRetour.vhd" into library xil_defaultlib
901
+INFO: [VRFC 10-307] analyzing entity MemoireAdressesRetour
902
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireInstructions.vhd" into library xil_defaultlib
903
+INFO: [VRFC 10-307] analyzing entity MemoireInstructions
904
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MemoireDonnees.vhd" into library xil_defaultlib
905
+INFO: [VRFC 10-307] analyzing entity MemoireDonnees
906
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/MUX.vhd" into library xil_defaultlib
907
+INFO: [VRFC 10-307] analyzing entity MUX
908
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/LC.vhd" into library xil_defaultlib
909
+INFO: [VRFC 10-307] analyzing entity LC
910
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage1_LectureInstruction.vhd" into library xil_defaultlib
911
+INFO: [VRFC 10-307] analyzing entity Etage1_LectureInstruction
912
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage2-5_Registres.vhd" into library xil_defaultlib
913
+INFO: [VRFC 10-307] analyzing entity Etage2_5_Registres
914
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage4_Memoire.vhd" into library xil_defaultlib
915
+INFO: [VRFC 10-307] analyzing entity Etage4_Memoire
916
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Etage3_Calcul.vhd" into library xil_defaultlib
917
+INFO: [VRFC 10-307] analyzing entity Etage3_Calcul
918
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
919
+INFO: [VRFC 10-307] analyzing entity Pipeline
920
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sources_1/new/Clock_Divider.vhd" into library xil_defaultlib
921
+INFO: [VRFC 10-307] analyzing entity Clock_Divider
922
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireDonnees.vhd" into library xil_defaultlib
923
+INFO: [VRFC 10-307] analyzing entity TestMemoireDonnees
924
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireAdressesRetour.vhd" into library xil_defaultlib
925
+INFO: [VRFC 10-307] analyzing entity TestMemoireAdressesRetour
926
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestBancRegistres.vhd" into library xil_defaultlib
927
+INFO: [VRFC 10-307] analyzing entity TestBancRegistres
928
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestALU.vhd" into library xil_defaultlib
929
+INFO: [VRFC 10-307] analyzing entity TestALU
930
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/TestMemoireInstructions.vhd" into library xil_defaultlib
931
+INFO: [VRFC 10-307] analyzing entity TestMemoireInstructions
932
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_LC.vhd" into library xil_defaultlib
933
+INFO: [VRFC 10-307] analyzing entity Test_LC
934
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_MUX.vhd" into library xil_defaultlib
935
+INFO: [VRFC 10-307] analyzing entity Test_MUX
936
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etape1_LectureInstruction.vhd" into library xil_defaultlib
937
+INFO: [VRFC 10-307] analyzing entity Test_Etape1_LectureInstruction
938
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage3_Calcul.vhd" into library xil_defaultlib
939
+INFO: [VRFC 10-307] analyzing entity Test_Etage3_Calcul
940
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage4_Memoire.vhd" into library xil_defaultlib
941
+INFO: [VRFC 10-307] analyzing entity Test_Etage4_Memoire
942
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Etage2_5_Registres.vhd" into library xil_defaultlib
943
+INFO: [VRFC 10-307] analyzing entity Test_Etage2_5_Registres
944
+INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.srcs/sim_1/new/Test_Pipeline.vhd" into library xil_defaultlib
945
+INFO: [VRFC 10-307] analyzing entity Test_Pipeline
946
+INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
947
+INFO: [USF-XSim-3] XSim::Elaborate design
948
+INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Hp/Documents/Compteur8BitsBasys3/Processeur.sim/sim_1/behav'
949
+Vivado Simulator 2016.4
950
+Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
951
+Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto c2fc77f80b2a4a04afc3ac9eb7900c74 --debug typical --relax --mt 2 -L xil_defaultlib -L secureip --snapshot Test_Pipeline_behav xil_defaultlib.Test_Pipeline -log elaborate.log 
952
+Using 2 slave threads.
953
+Starting static elaboration
954
+Completed static elaboration
955
+Starting simulation data flow analysis
956
+Completed simulation data flow analysis
957
+Time Resolution for simulation is 1ps
958
+Compiling package std.standard
959
+Compiling package std.textio
960
+Compiling package ieee.std_logic_1164
961
+Compiling package ieee.std_logic_arith
962
+Compiling package ieee.std_logic_unsigned
963
+Compiling package ieee.numeric_std
964
+Compiling architecture behavioral of entity xil_defaultlib.MemoireInstructions [\MemoireInstructions(nb_bits=29,...]
965
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=6...]
966
+Compiling architecture behavioral of entity xil_defaultlib.Etage1_LectureInstruction [\Etage1_LectureInstruction(instr...]
967
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
968
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
969
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
970
+Compiling architecture behavioral of entity xil_defaultlib.BancRegistres [\BancRegistres(nb_bits=8,addr_si...]
971
+Compiling architecture behavioral of entity xil_defaultlib.Etage2_5_Registres [\Etage2_5_Registres(nb_bits=8,nb...]
972
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
973
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
974
+Compiling architecture behavioral of entity xil_defaultlib.ALU [\ALU(nb_bits=8)\]
975
+Compiling architecture structural of entity xil_defaultlib.Etage3_Calcul [\Etage3_Calcul(nb_bits=8,instruc...]
976
+Compiling architecture behavioral of entity xil_defaultlib.LC [\LC(instruction_vector_size=5,co...]
977
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
978
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=5,instruction_vecto...]
979
+Compiling architecture behavioral of entity xil_defaultlib.MUX [\MUX(nb_bits=8,instruction_vecto...]
980
+Compiling architecture behavioral of entity xil_defaultlib.MemoireDonnees [\MemoireDonnees(nb_bits=8,addr_s...]
981
+Compiling architecture behavioral of entity xil_defaultlib.MemoireAdressesRetour [\MemoireAdressesRetour(nb_bits=5...]
982
+Compiling architecture structural of entity xil_defaultlib.Etage4_Memoire [\Etage4_Memoire(nb_bits=8,mem_si...]
983
+Compiling architecture behavioral of entity xil_defaultlib.Pipeline [\Pipeline(addr_memoire_instructi...]
984
+Compiling architecture behavioral of entity xil_defaultlib.test_pipeline
985
+Built simulation snapshot Test_Pipeline_behav
986
+INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
987
+Vivado Simulator 2016.4
988
+Time resolution is 1 ps

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