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Pipeline.vhd 16KB

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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 19.04.2021 16:57:41
  6. -- Design Name:
  7. -- Module Name: Pipeline - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. -- Uncomment the following library declaration if using
  23. -- arithmetic functions with Signed or Unsigned values
  24. --use IEEE.NUMERIC_STD.ALL;
  25. -- Uncomment the following library declaration if instantiating
  26. -- any Xilinx leaf cells in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29. entity Pipeline is
  30. Generic (Nb_bits : Natural := 8;
  31. Instruction_En_Memoire_Size : Natural := 29;
  32. Addr_Memoire_Instruction_Size : Natural := 3;
  33. Memoire_Instruction_Size : Natural := 8;
  34. Instruction_Bus_Size : Natural := 5;
  35. Nb_Instructions : Natural := 32;
  36. Nb_Registres : Natural := 16;
  37. Addr_registres_size : Natural := 4;
  38. Memoire_Size : Natural := 32;
  39. Adresse_mem_size : Natural := 5;
  40. Memoire_Adresses_Retour_Size : Natural := 16;
  41. Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
  42. Port (CLK : STD_LOGIC;
  43. RST : STD_LOGIC;
  44. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  45. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0));
  46. end Pipeline;
  47. architecture Behavioral of Pipeline is
  48. component Etage1_LectureInstruction is
  49. Generic (Instruction_size_in_memory : Natural;
  50. Addr_size_mem_instruction : Natural;
  51. Mem_instruction_size : Natural;
  52. Nb_bits : Natural;
  53. Instruction_bus_size : Natural;
  54. Nb_registres : Natural;
  55. Mem_adresse_retour_size : Natural;
  56. Adresse_size_mem_adresse_retour : Natural;
  57. Instructions_critiques_lecture_A : STD_LOGIC_VECTOR;
  58. Instructions_critiques_lecture_B : STD_LOGIC_VECTOR;
  59. Instructions_critiques_lecture_C : STD_LOGIC_VECTOR;
  60. Instructions_critiques_ecriture : STD_LOGIC_VECTOR;
  61. Code_Instruction_JMP : STD_LOGIC_VECTOR;
  62. Code_Instruction_JMZ : STD_LOGIC_VECTOR;
  63. Code_Instruction_CALL : STD_LOGIC_VECTOR;
  64. Code_Instruction_RET : STD_LOGIC_VECTOR;
  65. Code_Instruction_STOP : STD_LOGIC_VECTOR);
  66. Port ( CLK : in STD_LOGIC;
  67. RST : in STD_LOGIC;
  68. Z : in STD_LOGIC;
  69. A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  70. B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  71. C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  72. Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
  73. end component;
  74. component Etage2_5_Registres is
  75. Generic ( Nb_bits : Natural;
  76. Nb_registres : Natural;
  77. Addr_registres_size : Natural;
  78. Instruction_bus_size : Natural;
  79. Bits_Controle_LC_5 : STD_LOGIC_VECTOR;
  80. Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR;
  81. Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR;
  82. Code_Instruction_PRI : STD_LOGIC_VECTOR;
  83. Code_Instruction_GET : STD_LOGIC_VECTOR);
  84. Port ( CLK : in STD_LOGIC;
  85. RST : in STD_LOGIC;
  86. STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  87. STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  88. IN_2_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  89. IN_2_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  90. IN_2_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  91. IN_2_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
  92. OUT_2_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  93. OUT_2_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  94. OUT_2_C : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  95. OUT_2_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
  96. IN_5_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  97. IN_5_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  98. IN_5_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
  99. end component;
  100. component Etage3_Calcul is
  101. Generic ( Nb_bits : Natural;
  102. Instruction_bus_size : Natural;
  103. Bits_Controle_LC : STD_LOGIC_VECTOR;
  104. Bits_Controle_MUX : STD_LOGIC_VECTOR);
  105. Port ( RST : in STD_LOGIC;
  106. IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  107. IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  108. IN_C : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  109. IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
  110. OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  111. OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  112. OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
  113. N : out STD_LOGIC;
  114. O : out STD_LOGIC;
  115. Z : out STD_LOGIC;
  116. C : out STD_LOGIC);
  117. end component;
  118. component Etage4_Memoire is
  119. Generic ( Nb_bits : Natural;
  120. Mem_size : Natural;
  121. Adresse_mem_size : Natural;
  122. Instruction_bus_size : Natural;
  123. Mem_EBP_size : Natural;
  124. Adresse_size_mem_EBP : Natural;
  125. Bits_Controle_LC : STD_LOGIC_VECTOR;
  126. Bits_Controle_MUX_IN : STD_LOGIC_VECTOR;
  127. Bits_Controle_MUX_IN_EBP : STD_LOGIC_VECTOR;
  128. Bits_Controle_MUX_OUT : STD_LOGIC_VECTOR;
  129. Code_Instruction_CALL : STD_LOGIC_VECTOR;
  130. Code_Instruction_RET : STD_LOGIC_VECTOR);
  131. Port ( CLK : in STD_LOGIC;
  132. RST : in STD_LOGIC;
  133. IN_A : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  134. IN_B : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  135. IN_Instruction : in STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0);
  136. OUT_A : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  137. OUT_B : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0);
  138. OUT_Instruction : out STD_LOGIC_VECTOR (Instruction_bus_size - 1 downto 0));
  139. end component;
  140. signal A_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  141. signal A_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  142. signal A_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  143. signal A_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  144. signal A_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  145. signal A_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  146. signal A_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  147. signal A_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  148. signal B_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  149. signal B_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  150. signal B_from_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  151. signal B_from_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  152. signal B_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  153. signal B_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  154. signal B_to_4 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  155. signal B_to_5 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  156. signal C_from_1 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  157. signal C_from_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  158. signal C_to_2 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  159. signal C_to_3 : STD_LOGIC_VECTOR (Nb_bits - 1 downto 0) := (others => '0');
  160. signal Instruction_from_1 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  161. signal Instruction_from_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  162. signal Instruction_from_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  163. signal Instruction_from_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  164. signal Instruction_to_2 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  165. signal Instruction_to_3 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  166. signal Instruction_to_4 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  167. signal Instruction_to_5 : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := (others => '0');
  168. signal N : STD_LOGIC := '0';
  169. signal Z : STD_LOGIC := '0';
  170. signal O : STD_LOGIC := '0';
  171. signal C : STD_LOGIC := '0';
  172. constant Bits_Controle_MUX_2_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111011101111111111111";
  173. constant Bits_Controle_MUX_2_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111000011000000001";
  174. constant Bits_Controle_LC_3 : STD_LOGIC_VECTOR (Nb_Instructions * 3 - 1 downto 0) := "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "000" & "111" & "110" & "101" & "100" & "010" & "011" & "001" & "000";
  175. constant Bits_Controle_MUX_3 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111111111100000001";
  176. constant Bits_Controle_LC_4 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111001011111111111";
  177. constant Bits_Controle_MUX_4_IN : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111110101111111111";
  178. constant Bits_Controle_MUX_4_IN_EBP : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "1111111011001111111111";
  179. constant Bits_Controle_MUX_4_OUT : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000001010000000000";
  180. constant Bits_Controle_LC_5 : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
  181. constant Code_Instruction_JMP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "01111";
  182. constant Code_Instruction_JMZ : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10000";
  183. constant Code_Instruction_PRI : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10001";
  184. constant Code_Instruction_GET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10010";
  185. constant Code_Instruction_CALL : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10011";
  186. constant Code_Instruction_RET : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10100";
  187. constant Code_Instruction_STOP : STD_LOGIC_VECTOR (Instruction_Bus_Size - 1 downto 0) := "10101";
  188. constant Instructions_critiques_lecture_A : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000100010000000000000";
  189. constant Instructions_critiques_lecture_B : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000111100111111110";
  190. constant Instructions_critiques_lecture_C : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0000000000000011111110";
  191. constant Instructions_critiques_ecriture : STD_LOGIC_VECTOR (Nb_Instructions - 1 downto 0) := "1111111111" & "0001000001011111111110";
  192. begin
  193. instance_Etage1 : Etage1_LectureInstruction
  194. generic map (Instruction_size_in_memory => Instruction_En_Memoire_Size,
  195. Addr_size_mem_instruction => Addr_Memoire_Instruction_Size,
  196. Mem_instruction_size => Memoire_Instruction_Size,
  197. Nb_bits => Nb_bits,
  198. Instruction_bus_size => Instruction_Bus_Size,
  199. Nb_registres => Nb_Registres,
  200. Mem_adresse_retour_size => Memoire_Adresses_Retour_Size,
  201. Adresse_size_mem_adresse_retour => Adresse_Memoire_Adresses_Retour_Size,
  202. Instructions_critiques_lecture_A => Instructions_critiques_lecture_A,
  203. Instructions_critiques_lecture_B => Instructions_critiques_lecture_B,
  204. Instructions_critiques_lecture_C => Instructions_critiques_lecture_C,
  205. Instructions_critiques_ecriture => Instructions_critiques_ecriture,
  206. Code_Instruction_JMP => Code_Instruction_JMP,
  207. Code_Instruction_JMZ => Code_Instruction_JMZ,
  208. Code_Instruction_CALL => Code_Instruction_CALL,
  209. Code_Instruction_RET => Code_Instruction_RET,
  210. Code_Instruction_STOP => Code_Instruction_STOP
  211. )
  212. port map (
  213. CLK => CLK,
  214. RST => RST,
  215. Z => Z,
  216. A => A_from_1,
  217. B => B_from_1,
  218. C => C_from_1,
  219. Instruction => Instruction_from_1
  220. );
  221. instance_Etage2_5 : Etage2_5_Registres
  222. generic map( Nb_bits => Nb_bits,
  223. Nb_Registres => Nb_Registres,
  224. Addr_registres_size => Addr_registres_size,
  225. Instruction_bus_size => Instruction_Bus_Size,
  226. Bits_Controle_LC_5 => Bits_Controle_LC_5,
  227. Bits_Controle_MUX_2_A => Bits_Controle_MUX_2_A,
  228. Bits_Controle_MUX_2_B => Bits_Controle_MUX_2_B,
  229. Code_Instruction_PRI => Code_Instruction_PRI,
  230. Code_Instruction_GET => Code_Instruction_GET
  231. )
  232. port map( CLK => CLK,
  233. RST => RST,
  234. STD_IN => STD_IN,
  235. STD_OUT => STD_OUT,
  236. IN_2_A => A_to_2,
  237. IN_2_B => B_to_2,
  238. IN_2_C => C_to_2,
  239. IN_2_Instruction => Instruction_to_2,
  240. OUT_2_A => A_from_2,
  241. OUT_2_B => B_from_2,
  242. OUT_2_C => C_from_2,
  243. OUT_2_Instruction => Instruction_from_2,
  244. IN_5_A => A_to_5,
  245. IN_5_B => B_to_5,
  246. IN_5_Instruction => Instruction_to_5
  247. );
  248. instance_Etage3 : Etage3_Calcul
  249. generic map( Nb_bits => Nb_bits,
  250. Instruction_bus_size => Instruction_Bus_Size,
  251. Bits_Controle_LC => Bits_Controle_LC_3,
  252. Bits_Controle_MUX => Bits_Controle_MUX_3
  253. )
  254. port map( RST => RST,
  255. IN_A => A_to_3,
  256. IN_B => B_to_3,
  257. IN_C => C_to_3,
  258. IN_Instruction => Instruction_to_3,
  259. OUT_A => A_from_3,
  260. OUT_B => B_from_3,
  261. OUT_Instruction => Instruction_from_3,
  262. N => N,
  263. O => O,
  264. Z => Z,
  265. C => C
  266. );
  267. instance_Etage4 : Etage4_Memoire
  268. generic map( Nb_bits => Nb_bits,
  269. Mem_size => Memoire_Size,
  270. Adresse_mem_size => Adresse_mem_size,
  271. Instruction_bus_size => Instruction_Bus_Size,
  272. Mem_EBP_size => Memoire_Adresses_Retour_Size,
  273. Adresse_size_mem_EBP => Adresse_Memoire_Adresses_Retour_Size,
  274. Bits_Controle_LC => Bits_Controle_LC_4,
  275. Bits_Controle_MUX_IN => Bits_Controle_MUX_4_IN,
  276. Bits_Controle_MUX_IN_EBP => Bits_Controle_MUX_4_IN_EBP,
  277. Bits_Controle_MUX_OUT => Bits_Controle_MUX_4_OUT,
  278. Code_Instruction_CALL => Code_Instruction_CALL,
  279. Code_Instruction_RET => Code_Instruction_RET
  280. )
  281. port map( CLK => CLK,
  282. RST => RST,
  283. IN_A => A_to_4,
  284. IN_B => B_to_4,
  285. IN_Instruction => Instruction_to_4,
  286. OUT_A => A_from_4,
  287. OUT_B => B_from_4,
  288. OUT_Instruction => Instruction_from_4
  289. );
  290. process
  291. begin
  292. wait until CLK'event and CLK = '1';
  293. A_to_2 <= A_from_1;
  294. B_to_2 <= B_from_1;
  295. C_to_2 <= C_from_1;
  296. Instruction_to_2 <= Instruction_from_1;
  297. A_to_3 <= A_from_2;
  298. B_to_3 <= B_from_2;
  299. C_to_3 <= C_from_2;
  300. Instruction_to_3 <= Instruction_from_2;
  301. A_to_4 <= A_from_3;
  302. B_to_4 <= B_from_3;
  303. Instruction_to_4 <= Instruction_from_3;
  304. A_to_5 <= A_from_4;
  305. B_to_5 <= B_from_4;
  306. Instruction_to_5 <= Instruction_from_4;
  307. end process;
  308. end Behavioral;