Test compteur, NON FONCTIONNEL
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共有 7 個檔案被更改,包括 357 行新增 和 95 行删除
Compteur8BitsBasys3.srcs
constrs_1/imports/digilent-xdc-master
sim_1/new
sources_1/new
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@ -4,78 +4,78 @@
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## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
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## Clock signal
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set_property PACKAGE_PIN W5 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
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set_property PACKAGE_PIN W5 [get_ports CLK]
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set_property IOSTANDARD LVCMOS33 [get_ports CLK]
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create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
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## Switches
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set_property PACKAGE_PIN V17 [get_ports {sw[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
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set_property PACKAGE_PIN V16 [get_ports {sw[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
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set_property PACKAGE_PIN W16 [get_ports {sw[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
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set_property PACKAGE_PIN W17 [get_ports {sw[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
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set_property PACKAGE_PIN W15 [get_ports {sw[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
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set_property PACKAGE_PIN V15 [get_ports {sw[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
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set_property PACKAGE_PIN W14 [get_ports {sw[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
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set_property PACKAGE_PIN W13 [get_ports {sw[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
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set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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set_property PACKAGE_PIN V17 [get_ports {SW[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[0]}]
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set_property PACKAGE_PIN V16 [get_ports {SW[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]
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set_property PACKAGE_PIN W16 [get_ports {SW[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
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set_property PACKAGE_PIN W17 [get_ports {SW[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
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set_property PACKAGE_PIN W15 [get_ports {SW[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[4]}]
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set_property PACKAGE_PIN V15 [get_ports {SW[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[5]}]
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set_property PACKAGE_PIN W14 [get_ports {SW[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[6]}]
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set_property PACKAGE_PIN W13 [get_ports {SW[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SW[7]}]
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#set_property PACKAGE_PIN V2 [get_ports {sw[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
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#set_property PACKAGE_PIN T3 [get_ports {sw[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
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#set_property PACKAGE_PIN T2 [get_ports {sw[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
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#set_property PACKAGE_PIN R3 [get_ports {sw[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
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#set_property PACKAGE_PIN W2 [get_ports {sw[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
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#set_property PACKAGE_PIN U1 [get_ports {sw[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
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#set_property PACKAGE_PIN T1 [get_ports {sw[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
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#set_property PACKAGE_PIN R2 [get_ports {sw[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
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## LEDs
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set_property PACKAGE_PIN U16 [get_ports {led[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
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set_property PACKAGE_PIN E19 [get_ports {led[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
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set_property PACKAGE_PIN U19 [get_ports {led[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
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set_property PACKAGE_PIN V19 [get_ports {led[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
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set_property PACKAGE_PIN W18 [get_ports {led[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
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set_property PACKAGE_PIN U15 [get_ports {led[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
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set_property PACKAGE_PIN U14 [get_ports {led[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
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set_property PACKAGE_PIN V14 [get_ports {led[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
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set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
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set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
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set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
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set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
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set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
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set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
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set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
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set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
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#set_property PACKAGE_PIN V13 [get_ports {led[8]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
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#set_property PACKAGE_PIN V3 [get_ports {led[9]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
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#set_property PACKAGE_PIN W3 [get_ports {led[10]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
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#set_property PACKAGE_PIN U3 [get_ports {led[11]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
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#set_property PACKAGE_PIN P3 [get_ports {led[12]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
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#set_property PACKAGE_PIN N3 [get_ports {led[13]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
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#set_property PACKAGE_PIN P1 [get_ports {led[14]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
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#set_property PACKAGE_PIN L1 [get_ports {led[15]}]
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#set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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##7 segment display
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@ -108,16 +108,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
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##Buttons
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#set_property PACKAGE_PIN U18 [get_ports btnC]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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set_property PACKAGE_PIN U18 [get_ports btnC]
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set_property IOSTANDARD LVCMOS33 [get_ports btnC]
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#set_property PACKAGE_PIN T18 [get_ports btnU]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnU]
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#set_property PACKAGE_PIN W19 [get_ports btnL]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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#set_property PACKAGE_PIN T17 [get_ports btnR]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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#set_property PACKAGE_PIN U17 [get_ports btnD]
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#set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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set_property PACKAGE_PIN W19 [get_ports btnL]
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set_property IOSTANDARD LVCMOS33 [get_ports btnL]
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set_property PACKAGE_PIN T17 [get_ports btnR]
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set_property IOSTANDARD LVCMOS33 [get_ports btnR]
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set_property PACKAGE_PIN U17 [get_ports btnD]
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set_property IOSTANDARD LVCMOS33 [get_ports btnD]
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@ -0,0 +1,53 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.04.2021 22:51:31
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-- Design Name:
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-- Module Name: test_Compteur - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity test_Compteur is
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-- Port ( );
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end test_Compteur;
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architecture Behavioral of test_Compteur is
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component Compteur is
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Port ( CK : in STD_LOGIC;
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RST : in STD_LOGIC;
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SENS : in STD_LOGIC;
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LOAD : in STD_LOGIC;
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EN : in STD_LOGIC;
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Din : in STD_LOGIC_VECTOR (7 downto 0);
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Dout : out STD_LOGIC_VECTOR (7 downto 0));
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end component;
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signal CK
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begin
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end Behavioral;
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@ -2,9 +2,9 @@
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-- Company:
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-- Engineer:
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--
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-- Create Date: 09.04.2021 19:00:49
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-- Create Date: 09.04.2021 21:42:26
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-- Design Name:
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-- Module Name: LedTest - Behavioral
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-- Module Name: ClockDivider10 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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@ -21,27 +21,34 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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||||
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-- Uncomment the following library declaration if using
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||||
-- arithmetic functions with Signed or Unsigned values
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||||
use IEEE.NUMERIC_STD.ALL;
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--use IEEE.NUMERIC_STD.ALL;
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||||
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-- Uncomment the following library declaration if instantiating
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||||
-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity LedTest is
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Port ( clk : in STD_LOGIC;
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sw : in STD_LOGIC_VECTOR (0 to 15);
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led : out STD_LOGIC_VECTOR (0 to 15));
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end LedTest;
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entity ClockDivider10 is
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Port ( clk_in : in STD_LOGIC;
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clk_out : out STD_LOGIC);
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end ClockDivider10;
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architecture Behavioral of LedTest is
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architecture Behavioral of ClockDivider10 is
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subtype int10 is INTEGER range 0 to 10;
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signal N : int10 := 0;
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signal aux : STD_LOGIC;
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begin
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process
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begin
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led <= sw;
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wait until clk_in'event and clk_in = '1';
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N <= N + 1;
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if N = 10 then
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aux <= not aux;
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N <= 0;
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end if;
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end process;
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clk_out <= aux;
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end Behavioral;
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@ -0,0 +1,50 @@
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----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.04.2021 21:44:36
|
||||
-- Design Name:
|
||||
-- Module Name: ClockDivider1000 - Structural
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
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||||
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||||
entity ClockDivider1000 is
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||||
Port ( clk_in : in STD_LOGIC;
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||||
clk_out : out STD_LOGIC);
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||||
end ClockDivider1000;
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||||
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||||
architecture Structural of ClockDivider1000 is
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||||
component ClockDivider10
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||||
Port ( clk_in : in STD_LOGIC;
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||||
clk_out : out STD_LOGIC);
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||||
end component;
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||||
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||||
signal aux1, aux2 : STD_LOGIC;
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||||
begin
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||||
U1: ClockDivider10 port map(clk_in, aux1);
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||||
U2: ClockDivider10 port map(aux1, aux2);
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||||
U3: ClockDivider10 port map(aux2, clk_out);
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||||
end Structural;
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@ -0,0 +1,64 @@
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|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.04.2021 21:20:39
|
||||
-- Design Name:
|
||||
-- Module Name: Compteur - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
-- use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity Compteur is
|
||||
Port ( CK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
SENS : in STD_LOGIC;
|
||||
LOAD : in STD_LOGIC;
|
||||
EN : in STD_LOGIC;
|
||||
Din : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Dout : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end Compteur;
|
||||
|
||||
architecture Behavioral of Compteur is
|
||||
signal aux: STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
|
||||
begin
|
||||
Dout <= aux;
|
||||
process
|
||||
begin
|
||||
wait until CK'event and CK='1';
|
||||
if RST = '0' then
|
||||
aux <= (others => '0');
|
||||
elsif LOAD = '1' then
|
||||
aux <= Din;
|
||||
elsif EN = '0' then
|
||||
if SENS = '1' then
|
||||
aux <= aux + 1;
|
||||
else
|
||||
aux <= aux - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
|
@ -0,0 +1,66 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 09.04.2021 22:03:10
|
||||
-- Design Name:
|
||||
-- Module Name: System - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity System is
|
||||
Port ( SW : in STD_LOGIC_VECTOR (0 to 7);
|
||||
btnL : in STD_LOGIC;
|
||||
btnC : in STD_LOGIC;
|
||||
btnR : in STD_LOGIC;
|
||||
btnD : in STD_LOGIC;
|
||||
LED : out STD_LOGIC_VECTOR (0 to 7);
|
||||
CLK : in STD_LOGIC);
|
||||
end System;
|
||||
|
||||
architecture Structural of System is
|
||||
|
||||
component ClockDivider1000
|
||||
Port ( clk_in : in STD_LOGIC;
|
||||
clk_out : out STD_LOGIC);
|
||||
end component;
|
||||
|
||||
component Compteur
|
||||
Port ( CK : in STD_LOGIC;
|
||||
RST : in STD_LOGIC;
|
||||
SENS : in STD_LOGIC;
|
||||
LOAD : in STD_LOGIC;
|
||||
EN : in STD_LOGIC;
|
||||
Din : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
Dout : out STD_LOGIC_VECTOR (7 downto 0));
|
||||
end component;
|
||||
|
||||
signal CLK_DIV_1000, CLK_DIV_1000000 : STD_LOGIC;
|
||||
begin
|
||||
DIV1: ClockDivider1000 port map(CLK, CLK_DIV_1000);
|
||||
DIV2: ClockDivider1000 port map(CLK_DIV_1000, CLK_DIV_1000000);
|
||||
CMPT: Compteur port map(CLK_DIV_1000000, btnC, btnR, btnL, btnD, SW, LED);
|
||||
end Structural;
|
|
@ -54,7 +54,25 @@
|
|||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/LedTest.vhd">
|
||||
<File Path="$PSRCDIR/sources_1/new/ClockDivider10.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/Compteur.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/ClockDivider1000.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/System.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
|
@ -62,7 +80,7 @@
|
|||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LedTest"/>
|
||||
<Option Name="TopModule" Val="System"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
|
@ -81,9 +99,17 @@
|
|||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sim_1/new/test_Compteur.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="LedTest"/>
|
||||
<Option Name="TopModule" Val="System"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
|
@ -114,9 +140,7 @@
|
|||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
|
@ -124,9 +148,7 @@
|
|||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
|
載入中…
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