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Author SHA1 Message Date
Nahom
38f818afa1 cross assembleur semble etre ok 2021-05-14 16:32:46 +02:00
Nahom
57addecae2 Revert "Tests processeur OK" 
This reverts commit 9b69ceadef.
 2021-05-14 16:09:43 +02:00
53 changed files with 1484 additions and 810 deletions
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2
Makefile → compiler/Makefile
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@ -6,7 +6,7 @@ compiler: analyse_lexicale.lex analyse_syntaxique.y table_symboles.c table_fonct
gcc -w *.c -ly -o compiler
run: compiler
./compiler < test_file
./compiler < code_c
clean:
rm -f lex.yy.c compiler analyse_syntaxique.output analyse_syntaxique.tab.c analyse_syntaxique.tab.h

106
compiler/analyse_lexicale.lex Normal file
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@ -0,0 +1,106 @@
%{
#include "analyse_syntaxique.tab.h"
int yywrap(void){
return 1;
}
%}
ADD "+"
SUB "-"
MUL "*"
DIV "/"
tPO "("
tPF ")"
tAO "{"
tAF "}"
EOL "\n"
EOI ";"
SPACE " "
TAB "\t"
VIRGULE ","
AFFECTATION "="
EQUAL "=="
LT "<"
GT ">"
LTE "<="
GTE ">="
tINT "int"
tMAIN "main"
tPRINT "printf"
tRETURN "return"
tIF "if"
tELSE "else"
tWHILE "while"
tNOT "!"
tAND "&&"
tOR "||"
tDIFF "!="
tAPPERSAND "&"
DIGIT [0-9]
VARIABLE [A-Za-z0-9_]+
CONST "const"
DECIMAL {DIGIT}+
EXPONENTIEL {DIGIT}+"e"{DIGIT}+
ENTIER {DECIMAL}
ENTIEREXP {EXPONENTIEL}
OPERATION {ADD}|{SUB}|{MUL}|{DIV}
COMPARATEUR {EGAL}|{LT}|{GT}
SEPARATOR {SPACE}|{TAB}
%%
{ADD} {return tADD ;}
{SUB} {return tSUB ;}
{MUL} {return tMUL ;}
{DIV} {return tDIV ;}
{tPO} {return tPO ;}
{tPF} {return tPF ;}
{tAO} {return tAO ;}
{tAF} {return tAF ;}
{EOI} {return tPV ;}
{SEPARATOR} {}
{EOL} {}
{VIRGULE} {return tVIRGULE ;}
{AFFECTATION} {return tAFFECTATION ;}
{EQUAL} {return tEGAL ;}
{tDIFF} {return tDIFF ;}
{LT} {return tLT ;}
{GT} {return tGT ;}
{LTE} {return tLTE ;}
{GTE} {return tGTE ;}
{tNOT} {return tNOT ;}
{tMAIN} {return tMAIN ;}
{tINT} {return tINT ;}
{tPRINT} {return tPRINT ;}
{tRETURN} {return tRETURN ;}
{tOR} {return tOR ;}
{tAND} {return tAND ;}
{tIF} {return tIF ;}
{tELSE} {return tELSE ;}
{tWHILE} {return tWHILE ;}
{tAPPERSAND} {return tAPPERSAND;}
{CONST} {return tCONST ;}
{ENTIER} {yylval.nombre = atoi(yytext); return tENTIER ;}
{ENTIEREXP} {yylval.nombre = -1; return tENTIEREXP;}
{VARIABLE} {strcpy(yylval.id, yytext); return tVAR ;}
%%
//int main(void){
// yylex();
//}

230
compiler/analyse_syntaxique.y Normal file
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@ -0,0 +1,230 @@
%union {
int nombre;
char id[30];
}
%{
#include <stdio.h>
#include "table_symboles.h"
#include "table_fonctions.h"
#include "gen_assembleur.h"
enum Initialised_Variable init;
enum Symbole_Type type;
enum Return_Type return_type;
Table_Symboles table;
Table_Fonctions table_fonctions;
instructions_array array;
int whileCondition;
int return_value;
%}
%token<nombre> tENTIER
%token<nombre> tENTIEREXP
%type<nombre> E
%type<nombre> Return Instructions
%type<nombre> Cond
%type<nombre> While Else Invocation
%token tADD
%token tSUB
%token tMUL
%token tDIV
%token<nombre> tPO
%token tPF
%token tAO
%token tAF
%token tERROR
%token tAPPERSAND
%token tPV
%token tVIRGULE
%token tAFFECTATION
%token tEGAL
%token tDIFF
%token tLT
%token tGT
%token tGTE
%token tLTE
%token tMAIN
%token tINT
%token tPRINT
%token tRETURN
%token tOR
%token tAND
%token<nombre> tIF
%token tELSE
%token<nombre> tWHILE
%token tCONST
%token<id> tVAR
%token tNOT
%left tADD
%left tSUB
%left tMUL
%left tDIV
%right tEGAL
%%
/*C : Fonctions Main ;
Fonctions : ;
Fonctions : Fonction Fonctions ;
Fonction : tINT tVAR tPO Params tPF Body;*/
C : {generate_instruction_1(&array, JMP, -1);} Fonctions;
Fonctions: Main;
Fonctions: Fonction Fonctions;
Main : tINT tMAIN {update_jmp(&array, 0, array.index); add_function(&table_fonctions, "Main", RET_INT, array.index); table.depth++;} tPO Params tPF Body {print_table(&table);remove_symboles(&table); table.depth--;};
Fonction : Function_type tVAR {{add_function(&table_fonctions, $2, return_type, array.index); table.depth++;}} tPO Params tPF Body {print_table(&table);remove_symboles(&table); table.depth--;};
Function_type: tINT {type = TYPE_INT;} ;
Function_type: tINT tMUL {type = TYPE_INT_PTR;};
Params : {} ;
Params : Param SuiteParams ;
Param : Param_type tVAR {add_symbole_top(&table, $2, type, INITIALISED, table.depth);} ;
Param_type: tINT {type = TYPE_INT;} ;
Param_type: tINT tMUL {type = TYPE_INT_PTR;};
SuiteParams : tVIRGULE Param SuiteParams ;
SuiteParams : ;
Body : tAO Instructions Return tAF {} ;
Instructions : Instruction Instructions {$$ = array.index;};
Instructions : {$$ = array.index;};
Instruction : Aff ;
Instruction : If ;
Instruction : While ;
Instruction : Print ;
Instruction : Decl ;
Instruction : Invocation tPV ;
Decl : Type Valeur SuiteDecl tPV ;
SuiteDecl: tVIRGULE Valeur SuiteDecl ;
SuiteDecl: ;
Type : tINT {type = TYPE_INT;} ;
Type : tCONST tINT {type = TYPE_CONST_INT;} ;
Type : tINT tMUL {type = TYPE_INT_PTR;};
Valeur : tVAR {add_symbole_top(&table, $1, type, INITIALISED, table.depth);} tAFFECTATION E {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, varAddr, $4); free_temp(&table);};
Valeur : tVAR {add_symbole_top(&table, $1, type, NOT_INITIALISED, table.depth);};
Aff : tVAR tAFFECTATION E tPV {int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, varAddr, $3); free_temp(&table); };
Aff : tMUL tVAR tAFFECTATION E tPV {int varAddr = variable_exists(&table, $2); generate_instruction_2(&array, COP_STR, varAddr, $4); free_temp(&table); };
E : tENTIER {int vt = new_temp(&table); generate_instruction_2(&array, AFC, vt, $1); $$ = vt;};
E : tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $1); generate_instruction_2(&array, COP, vt, varAddr); $$ = vt;};
E : E tADD E {generate_instruction_3(&array, ADD, $1, $1, $3); free_temp(&table); $$ = $1;} ;
E : E tMUL E {generate_instruction_3(&array, MUL, $1, $1, $3); free_temp(&table); $$ = $1;} ;
E : E tSUB E {generate_instruction_3(&array, SOU, $1, $1, $3); free_temp(&table); $$ = $1;} ;
E : E tDIV E {generate_instruction_3(&array, DIV, $1, $1, $3); free_temp(&table); $$ = $1;} ;
E : tSUB E {printf("Variable negative\n");} ;
E : Invocation {
//int vt = new_temp(&table);
//generate_instruction_2(&array, COP, vt, $1);
remove_symboles(&table);
table.depth--;
$$ = $1;};
E : tPO E tPF {printf("Parenthèse\n"); $$ = $2; } ;
E : tAPPERSAND tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $2); generate_instruction_2(&array, LEA, vt, varAddr); $$ = vt;};
E : tMUL tVAR {int vt = new_temp(&table); int varAddr = variable_exists(&table, $2); generate_instruction_2(&array, COP, vt, varAddr); generate_instruction_2(&array, COP_LD, vt, vt); $$ = vt;};
If : tIF tPO Cond tPF {
//gen_jmpf(&table, &array, $3, -1);
generate_instruction_2(&array, JMF, $3, -1);
free_temp(&table);
$1 = array.index;
}
tAO {table.depth++;} Instructions {generate_instruction_1(&array, JMP, -1);} tAF {remove_symboles(&table); table.depth--;}
{
int adr_jmp = array.index;
update_jmf(&array, $1, adr_jmp);
}
Else {printf("updating jump\n"); update_jmp(&array, $8, $13);};
Else : tELSE tAO {table.depth++;} Instructions tAF {remove_symboles(&table); table.depth--;} {$$ = array.index;} ;
Else : {$$ = array.index;};
Else : tELSE If {$$ = array.index;} ;
While : tWHILE tPO {
$2 = array.index ;
} Cond tPF {
//gen_jmpf(&table, &array, $4, -1);
generate_instruction_2(&array, JMF, $4, -1);
free_temp(&table);
$1 = array.index;
}
tAO {table.depth++;} Instructions tAF {remove_symboles(&table); table.depth--;} {
int adr_jmp = array.index;
update_jmf(&array, $1, adr_jmp);
//gen_jmpf(&table, &array, $1, $2);
generate_instruction_1(&array, JMP, $2);
};
Cond : E tEGAL E {generate_instruction_3(&array, EQ, $1, $1, $3); free_temp(&table); $$ = $3;};
Cond : E tDIFF E {generate_instruction_3(&array, NEQ, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tLT E {generate_instruction_3(&array, LT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tGT E {generate_instruction_3(&array, GT, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tLTE E {generate_instruction_3(&array, LTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tGTE E {generate_instruction_3(&array, GTE, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tAND E {generate_instruction_3(&array, AND, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : E tOR E {generate_instruction_3(&array, OR, $1, $1, $3); free_temp(&table); $$ = $3;} ;
Cond : tNOT Cond {generate_instruction_2(&array, NOT, $2, $2); $$ = $2;} ;
Cond : E {$$ = $1; };
Invocation : tVAR tPO {table.depth++; prepare_function_call(&table); return_value = (table.indexAvailableBottom);} Args tPF
{int function_index = function_exists(&table_fonctions, $1);
int jmp_addr = (table_fonctions.array[function_index]).start_addr;
generate_instruction_2(&array, CALL, jmp_addr, table.indexAvailableTop);
$$ = return_value;
};
Args : Arg SuiteArgs ;
Args :
Arg : E {int arg_addr = prepare_argument_push(&table); generate_instruction_2(&array, COP, arg_addr, $1); free_temp(&table);};
SuiteArgs : tVIRGULE Arg SuiteArgs ;
SuiteArgs : ;
Print : tPRINT tPO E tPF tPV {generate_instruction_1(&array, PRI, $3); free_temp(&table);};
Return : tRETURN E tPV {$$ = generate_instruction_1(&array, RET, $2); free_temp(&table);};
%%
#include <stdio.h>
void main(void){
//TODO: rajouter gestion des erreurs
initialise_table(&table);
initialise_function_table(&table_fonctions);
initialise_asm(&array);
yyparse();
print_table(&table);
printf("\n");
print_fonction_table(&table_fonctions);
//remove_symboles(&table, 0);
//print_table(&table);
exportInstructions(&array);
}

16
compiler/code_c Normal file
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@ -0,0 +1,16 @@
int fonction1(int * a){
int b = *a;
printf(b);
return 1;
}
int main(){
int l = 21;
int * p = &l;
int c = fonction1(p);
printf(c);
p = &c;
*p = 2;
printf(c);
return 0;

357
compiler/gen_assembleur.c Normal file
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@ -0,0 +1,357 @@
#include "gen_assembleur.h"
#include <stdio.h>
#include <stdlib.h>
char * operationName(enum operation op){
switch(op){
case EQ:
return "EQ";
case NEQ:
return "NEQ";
case LT:
return "LT";
case GT:
return "GT";
case LTE:
return "LTE";
case GTE:
return "GTE";
case ADD:
return "ADD";
case SOU:
return "SOU";
case DIV:
return "DIV";
case MUL:
return "MUL";
case COP:
return "COP";
case AFC:
return "AFC";
case RET:
return "RET";
case JMF:
return "JPF";
case JMP:
return "JMP";
case AND:
return "AND";
case OR:
return "OR";
case NOT:
return "NOT";
case PRI:
return "PRI";
case LEA:
return "LEA";
case COP_LD:
return "COP_LD";
case COP_STR:
return "COP_STR";
case RET_FUN:
return "RET_FUN";
case CALL:
return "CALL";
default:
break;
}
return "";
}
void initialise_asm(instructions_array * array){
array->index = 0;
}
int add_instruction(instructions_array * array, instruction * instru){
if (array->index >= INSTRUCTION_TABLE_SIZE){
return 1;
}
array->array[array->index] = *instru;
array->index++;
return 0;
}
int new_temp(Table_Symboles * table){
int ret_addr ;
if(add_symbole_bottom(table) == -1) {
return -1;
}
ret_addr = table->indexAvailableBottom + 1;
return ret_addr;
}
int generate_instruction_0(instructions_array * array, enum operation op){
instruction instru;
char * opName = operationName(op);
instru.operation = op;
printf("%d\t %s\n", array->index, opName);
if (add_instruction(array, &instru) != 0){
//TODO: Error handling
exit(1);
}
return 0;
}
int generate_instruction_1(instructions_array * array, enum operation op, int arg1){
instruction instru;
char * opName = operationName(op);
instru.operation = op;
instru.reg1 = arg1;
printf("%d\t %s %d\n", array->index, opName, instru.reg1);
if (add_instruction(array, &instru) != 0){
//TODO: Error handling
exit(1);
}
return 0;
}
int generate_instruction_2(instructions_array * array, enum operation op, int arg1, int arg2){
instruction instru;
char * opName = operationName(op);
instru.operation = op;
instru.reg1 = arg1;
instru.reg2 = arg2;
printf("%d\t %s %d %d\n", array->index, opName, instru.reg1, instru.reg2);
if (add_instruction(array, &instru) != 0){
//TODO: Error handling
exit(1);
}
return 0;
}
int generate_instruction_3(instructions_array * array, enum operation op, int arg1, int arg2, int arg3){
instruction instru;
char * opName = operationName(op);
instru.operation = op;
instru.reg1 = arg1;
instru.reg2 = arg2;
instru.reg3 = arg3;
printf("%d\t %s %d %d %d\n", array->index, opName, instru.reg1, instru.reg2, instru.reg3);
if (add_instruction(array, &instru) != 0){
//TODO: Error handling
exit(1);
}
return 0;
}
void update_jmf(instructions_array * array, int instru_index, int adr_jmp){
array->array[instru_index - 1].reg2 = adr_jmp;
printf("%d\t JMP %d %d\n", (instru_index - 1), array->array[instru_index].reg1, array->array[instru_index].reg2);
}
void update_jmp(instructions_array * array, int instru_index, int adr_jmp){
array->array[instru_index].reg1 = adr_jmp;
printf("%d\t JMP %d\n", (instru_index - 1), array->array[instru_index].reg1);
}
void exportInstructions(instructions_array * array){
FILE *file;
file = fopen("memory_oriented_assembly.txt", "w");
instruction instru;
enum operation op;
for (int i = 0; i < array->index; i++){
instru = array->array[i];
op = instru.operation;
switch (op) {
//0 parameters
case RET_FUN:
fprintf(file, "%s\n", operationName(op));
break;
//1 parameter
case JMP:
case PRI:
case RET:
fprintf(file, "%s %d\n", operationName(op), instru.reg1);
break;
//2 parameters
case JMF:
case NOT:
case AFC:
case COP:
case LEA:
case CALL:
fprintf(file, "%s %d %d\n", operationName(op), instru.reg1, instru.reg2);
break;
case COP_LD:
fprintf(file, "%s %d [%d]\n", operationName(op), instru.reg1, instru.reg2);
break;
case COP_STR:
fprintf(file, "%s [%d] %d\n", operationName(op), instru.reg1, instru.reg2);
break;
//3 parameters
case ADD:
case SOU:
case DIV:
case MUL:
case AND:
case OR:
case EQ:
case NEQ:
case LT:
case LTE:
case GT:
case GTE:
fprintf(file, "%s %d %d %d\n", operationName(op), instru.reg1, instru.reg2, instru.reg3);
break;
default:
break;
}
}
fclose(file);
}
/*int gen_print(Table_Symboles * table, instructions_array * array, int arg1){
instruction instru;
instru.operation = PRI;
instru.reg1 = arg1;
printf("%d\t PRI %d\n", array->index, instru.reg1);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
free_temp(table);
}*/
/*void gen_arithmetique(instructions_array * array, enum operation op, int arg1, int arg2){
instruction instru;
instru.reg1 = arg1;
instru.reg2 = arg1;
instru.reg3 = arg2;
char * opName = operationName(op);
printf("%d\t %s %d %d %d\n", array->index, opName, arg1, arg1, arg2);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
}
int gen_var(Table_Symboles * table, instructions_array * array, char * varName){
int vt = new_temp(table);
int varAddr = variable_exists(table, varName);
//vérifier que non null
instruction instru;
instru.operation = COP;
instru.reg1 = vt;
instru.reg2 = varAddr;
printf("%d\t COP %d %d\n", array->index, vt, varAddr);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
return vt;
}
int gen_entier(Table_Symboles * table, instructions_array * array, int entier){
int vt = new_temp(table);
//vérifier que non null
instruction instru;
instru.operation = AFC;
instru.reg1 = vt;
instru.reg2 = entier;
printf("%d\t AFC %d %d\n", array->index, vt, entier);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
return vt;
}
int gen_condition(Table_Symboles * table, instructions_array * array, enum operation op, int arg1, int arg2){
char * opName = operationName(op);
instruction instru;
instru.operation = op;
instru.reg1 = arg1;
instru.reg2 = arg1;
if (op != NOT){
instru.reg3 = arg2;
printf("%d\t %s %d %d %d\n", array->index, opName, instru.reg1, instru.reg2, instru.reg3);
free_temp(table);
} else {
printf("%d\t %s %d %d \n", array->index, opName, instru.reg1, instru.reg2);
}
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
return instru.reg1;
}
int gen_return(Table_Symboles * table, instructions_array * array, int adr){
//vérifier que non null
instruction instru;
instru.operation = RET;
instru.reg1 = adr;
printf("%d\t RET %d\n", array->index, adr);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
//free_temp(table);
return adr;
}
int gen_jmpf(Table_Symboles * table, instructions_array * array, int cond, int dest){
//vérifier que non null
instruction instru;
instru.operation = JMF;
instru.reg1 = cond;
instru.reg2 = dest;
printf("%d\t JMPF %d %d\n", array->index, instru.reg1 , instru.reg2);
if (array->index < INSTRUCTION_TABLE_SIZE){
array->array[array->index] = instru;
array->index++;
}
//free_temp(table);
return cond;
}
*/

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compiler/gen_assembleur.h Normal file
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#ifndef GEN_ASSEMBLEUR_H
#define GEN_ASSEMBLEUR_H
#define INSTRUCTION_TABLE_SIZE 1000
#include "table_symboles.h"
enum operation{ADD, SOU, MUL, DIV, COP, AFC, RET, JMF, JMP, EQ, NEQ, LT, GT, LTE,
GTE, AND, OR, NOT, PRI, LEA, COP_LD, COP_STR, CALL, RET_FUN};
typedef struct instruction{
enum operation operation;
int reg1;
int reg2;
int reg3;
}instruction;
//table des instructions
typedef struct instructions_array{
instruction array[INSTRUCTION_TABLE_SIZE];
int index;
} instructions_array;
/**
*
* @param op operation
* @return returns the string that corresponds to the enum operation op
*/
char * operationName(enum operation op);
/**
* Initialises the instructions array
* @param array
*/
void initialise_asm(instructions_array * array);
//renvoie l'index (ou valeur?) de la premiere @ dispo
/**
* Fetch address of a temporary variable
* @param table
* @return first available temp address
*/
int new_temp(Table_Symboles * table);
/**
* Adds intruction to instruction array
* @param array
* @param intru
* @return 0 if instruction was added successfully, -1 if not
*/
int add_instruction(instructions_array * array, instruction * intru);
/**
* Generates intruction with no parameter
* @param array
* @param op
* @return
*/
int generate_instruction_0(instructions_array * array, enum operation op);
/**
* Generates intruction with one parameter
* @param array
* @param op
* @param arg1
* @return
*/
int generate_instruction_1(instructions_array * array, enum operation op, int arg1);
/**
* Generates intruction with two parameters
* @param array
* @param op
* @param arg1
* @param arg2
* @return
*/
int generate_instruction_2(instructions_array * array, enum operation op, int arg1, int arg2);
/**
* Generates intruction with three parameters
* @param array
* @param op
* @param arg1
* @param arg2
* @param arg3
* @return
*/
int generate_instruction_3(instructions_array * array, enum operation op, int arg1, int arg2, int arg3);
/**
* Updates the JMF instruction with the correct jump destination address
* @param array
* @param instru_index
* @param adr_jmp
*/
void update_jmf(instructions_array * array, int instru_index, int adr_jmp);
void update_jmp(instructions_array * array, int instru_index, int adr_jmp);
void exportInstructions(instructions_array * array);
/*
void gen_arithmetique(instructions_array * array, enum operation op, int arg1, int arg2);
int gen_var(Table_Symboles * table, instructions_array * array, char * varName);
int gen_entier(Table_Symboles * table, instructions_array * array, int entier);
int gen_return(Table_Symboles * table, instructions_array * array, int adr);
int gen_jmpf(Table_Symboles * table, instructions_array * array, int cond, int dest);
int gen_condition(Table_Symboles * table, instructions_array * array, enum operation op, int arg1, int arg2);
int gen_print(Table_Symboles * table, instructions_array * array, int arg1);
*/
#endif

26
compiler/memory_oriented_assembly.txt Normal file
View file

@ -0,0 +1,26 @@
JMP 8
COP 255 0
COP_LD 255 [255]
COP 1 255
COP 255 1
PRI 255
AFC 255 1
RET 255
AFC 255 21
COP 0 255
LEA 255 0
COP 1 255
COP 255 1
COP 5 255
CALL 1 6
COP 2 255
COP 255 2
PRI 255
LEA 255 2
COP 1 255
AFC 255 2
COP_STR [1] 255
COP 255 2
PRI 255
AFC 255 0
RET 255

59
compiler/table_fonctions.c Normal file
View file

@ -0,0 +1,59 @@
#include "table_fonctions.h"
#include <string.h>
#include <stdio.h>
void initialise_function_table(Table_Fonctions * table){
table->depth = 1;
}
void add_function(Table_Fonctions * table, char * function_name, enum Return_Type return_type, int start_addr){
Fonction fonction;
strcpy(fonction.function_name,function_name);
fonction.start_addr = start_addr;
fonction.type = return_type;
fonction.function_depth = table->depth;
table->array[table->depth] = fonction;
table->depth++;
}
void print_function(Fonction * fonction){
char * function_name = fonction->function_name;
int start_addr = fonction->start_addr;
int depth = fonction->function_depth;
int return_type = fonction->type;
char typeStr[20];
if (return_type == RET_INT){
strcpy(typeStr, "INT");
} else if (return_type == RET_INT_PTR){
strcpy(typeStr, "INT_PTR");
}
printf("%-20s\t\t %-12s\t\t %-12d\t %-12d\n", function_name, typeStr, start_addr, depth);
}
void print_fonction_table(Table_Fonctions * table) {
printf("%-20s\t\t %-12s\t\t %-12s\t %-20s\n", "Function Name", "Return Type", "Start Address", "Depth");
Fonction fonction;
for (int i = 1; i < table->depth; i++) {
fonction = table->array[i];
print_function(&fonction);
}
}
int function_exists(Table_Fonctions * table, char * func_name){
for (int i = 0; i < table->depth; i++){
if (strcmp(table->array[i].function_name, func_name) == 0){
return i;
}
}
return -1;
}
/*
int main(){
Table_Fonctions table;
initialise_function_table(&table);
add_function(&table, "Fonction1", 0, 7);
add_function(&table, "Fonction2", 1, 23);
print_fonction_table(&table);
return 1;
}*/

35
compiler/table_fonctions.h Normal file
View file

@ -0,0 +1,35 @@
//
// Created by Nahom Belay on 29/04/2021.
//
#ifndef PROJET_SYSTEME_TABLE_FONCTIONS_H
#define PROJET_SYSTEME_TABLE_FONCTIONS_H
#define FUNCTION_TABLE_SIZE 50
#define FUNCTION_NAME_SIZE 30
enum Return_Type {RET_INT , RET_INT_PTR};
typedef struct Fonction {
char function_name[FUNCTION_NAME_SIZE];
int start_addr ;
enum Return_Type type;
int function_depth;
} Fonction;
typedef struct Table_Fonctions {
Fonction array[FUNCTION_TABLE_SIZE];
int depth;
} Table_Fonctions;
void initialise_function_table(Table_Fonctions * table);
void add_function(Table_Fonctions * table, char * function_name, enum Return_Type return_type, int start_addr);
void print_fonction_table(Table_Fonctions * table);
int function_exists(Table_Fonctions * table, char * func_name);
#endif //PROJET_SYSTEME_TABLE_FONCTIONS_H

152
compiler/table_symboles.c Normal file
View file

@ -0,0 +1,152 @@
#include "table_symboles.h"
#include <stdio.h>
#include <string.h>
void initialise_table(Table_Symboles * table){
table->indexAvailableBottom = TABLE_SIZE - 1;
table->indexAvailableTop = 0;
table->depth = 0;
}
int variable_exists(Table_Symboles * table, char * varName){
for (int i = 0; i < table->indexAvailableTop; i++){
if (strcmp(varName, table->array[i].Variable_Name) == 0){
return i;
}
}
for (int i = (table->indexAvailableBottom + 1); i < TABLE_SIZE; i++){
if (strcmp(varName, table->array[i].Variable_Name) == 0){
return i;
}
}
return 0;
}
int add_symbole_top(Table_Symboles * table, char * varName, enum Symbole_Type type, enum Initialised_Variable init, int depth){
Symbole symbole;
strcpy(symbole.Variable_Name, varName);
symbole.addr = table->indexAvailableTop;
symbole.init = init;
symbole.type = type;
symbole.symbole_depth = table->depth;
if (table->indexAvailableTop >= table->indexAvailableBottom){
return -1;
} else if (variable_exists(table, varName) != 0){
return -2;
} else {
table->array[table->indexAvailableTop] = symbole;
table->indexAvailableTop++;
}
return 0;
}
int add_symbole_bottom(Table_Symboles * table){
Symbole symbole;
symbole.addr = table->indexAvailableBottom;
//symbole.symbole_depth = -1;
if (table->indexAvailableTop >= table->indexAvailableBottom){
return -1;
} else {
table->array[table->indexAvailableBottom] = symbole;
table->indexAvailableBottom--;
}
return 0;
}
int remove_symboles(Table_Symboles * table){
if (table->indexAvailableTop > 0){
while(table->indexAvailableTop > 0){
if (table->array[table->indexAvailableTop-1].symbole_depth == table->depth){
table->indexAvailableTop--;
} else {
break;
}
}
}
//TODO: vérifier qu'il n'y a pas de varaibles temporarires au moment de changement de profondeur
return 0;
}
void free_temp(Table_Symboles * table){
table->indexAvailableBottom++;
if (table->indexAvailableBottom >= TABLE_SIZE){
printf("Huge error\n");
table->indexAvailableBottom--;
}
}
int prepare_function_call(Table_Symboles * table){
prepare_argument_push(table);
prepare_argument_push(table);
}
int prepare_argument_push(Table_Symboles * table){
Symbole symbole;
symbole.addr = table->indexAvailableTop;
symbole.symbole_depth = table->depth;
if (table->indexAvailableTop < table->indexAvailableBottom){
table->array[table->indexAvailableTop] = symbole;
table->indexAvailableTop++;
return (table->indexAvailableTop) - 1 ;
}
}
int initialise_symbole(Table_Symboles * table, char * varName){
int index = variable_exists(table, varName);
if (index == -1){
return -1;
} else {
table->array[index].init = INITIALISED;
}
}
void print_symbole(Symbole * symbole){
char * var = symbole->Variable_Name;
int addr = symbole->addr;
enum Symbole_Type type = symbole->type;
char typeStr[20];
if (type == TYPE_INT){
strcpy(typeStr, "INT");
} else if (type == TYPE_CONST_INT){
strcpy(typeStr, "CONST_INT");
} else if (type == TYPE_INT_PTR) {
strcpy(typeStr, "INT_PTR");
} else {
strcpy(typeStr, "Error type");
}
enum Initialised_Variable init = symbole->init;
char initStr[20];
if (init == INITIALISED){
strcpy(initStr,"INITIALISED");
} else{
strcpy(initStr,"NOT_INITIALISED");
}
int depth = symbole->symbole_depth;
printf("%-20s\t\t %-12s\t\t %-12d\t %-20s\t %-12d\n", var, typeStr, addr, initStr, depth);
}
void print_table(Table_Symboles * table){
printf("%-20s\t\t %-12s\t\t %-12s\t %-20s\t %-12s\n", "Variable Name", "Type", "Address", "Initialised", "Depth");
int indexTop = table->indexAvailableTop;
int indexBottom = table->indexAvailableBottom;
Symbole symbole;
for (int i = 0; i < indexTop; i++){
symbole = table->array[i];
print_symbole(&symbole);
}
if (table->indexAvailableBottom != TABLE_SIZE - 1){
printf("%-20s\t\t %-12s\t\t %-12s\t %-20s\t %-12s\n", "...", "...", "...", "...", "...");
for (int i = (indexBottom + 1); i < TABLE_SIZE; i++){
symbole = table->array[i];
print_symbole(&symbole);
}
}
}

95
compiler/table_symboles.h Normal file
View file

@ -0,0 +1,95 @@
#ifndef TABLE_SYMBOLES_H
#define TABLE_SYMBOLES_H
#define TABLE_SIZE 256
#define VARIABLE_SIZE 30
enum Symbole_Type {TYPE_INT , TYPE_CONST_INT, TYPE_INT_PTR};
enum Initialised_Variable{INITIALISED , NOT_INITIALISED};
typedef struct Symboles {
char Variable_Name[VARIABLE_SIZE];
int addr ;
enum Symbole_Type type;
enum Initialised_Variable init;
int symbole_depth;
} Symbole;
typedef struct Table_Symboles {
Symbole array[TABLE_SIZE];
int indexAvailableTop;
int indexAvailableBottom;
int depth;
} Table_Symboles;
/**
* Initialises indexAvailableTop at 0 and indexAvailableBottom at TABLE_SIZE - 1
* @param table
*/
void initialise_table(Table_Symboles * table);
/**
* Adds a symbole at the top (regular varaibles)
* @param table
* @param varName
* @param type
* @param init
* @return if symbole added successfully, -1 if the table is full and -2 if the varaible already exists in the table
*/
int add_symbole_top(Table_Symboles * table, char * varName, enum Symbole_Type type , enum Initialised_Variable init, int depth);
/**
* Adds a symbole at the bottom (temp variables)
* @param table
* @return 0 if symbole added successfully, -1 if the table is full and -2 if the varaible already exists in the table
*/
int add_symbole_bottom(Table_Symboles * table);
/**
* Verifies if a varaible name is already present in the table to avoid duplicates
* @param table
* @param varName
* @return -1 if the varaible name exists, 0 if it doesn't
*/
int variable_exists(Table_Symboles * table, char * varName);
/**
* Removes symbole from table having certain depth
* @param table
* @return -1 if the symbole isn't in the table, 0 otherwise
*/
int remove_symboles(Table_Symboles * table);
void free_temp(Table_Symboles * table);
int prepare_function_call(Table_Symboles * table);
int prepare_argument_push(Table_Symboles * table);
/**
* Initialises an already exisiting symbole
* @param table
* @param varName
* @return -1 if the symbole isn't in the table, 0 otherwise
*/
int initialise_symbole(Table_Symboles * table, char * varName);
/**
* Prints a symbole with this format
* varName | Type | Address | Initialised/Not_Initialised
* @param symbole
*/
void print_symbole(Symbole * symbole);
/**
* Prints the table
* @param table
*/
void print_table(Table_Symboles * table);
#endif

0
interpreter/input.txt → interpreter/interpreter_input.txt
View file

27
xilinx/ALU/ALU.gise
View file

@ -49,13 +49,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620740667">
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/>
@ -80,14 +76,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1620740667" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620740667">
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/>
@ -100,15 +91,9 @@
<outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/>
</transform>
<transform xil_pn:end_ts="1620740670" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620740667">
<transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
@ -116,13 +101,9 @@
<outfile xil_pn:name="process_test_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1620740670" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620740670">
<transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="process_test_isim_beh.wdb"/>

6
xilinx/ALU/ALU.xise
View file

@ -311,8 +311,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test/uut/data_memory" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/process_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -330,7 +330,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bm_data" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.process_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>

2
xilinx/ALU/_xmsgs/pn_parser.xmsgs
View file

@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg>
</msg>
</messages>

14
xilinx/ALU/bm_instr.vhd
View file

@ -37,21 +37,9 @@ type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
--test afc cop
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
--test add
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
--test sub
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
--test mul
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
--test store
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
--test load
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
begin
OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

12
xilinx/ALU/fuse.log
View file

@ -1,7 +1,7 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_beh.prj" "work.process_test"
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Determining compilation order of HDL files
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 98520 KB
Fuse CPU Usage: 880 ms
Fuse CPU Usage: 760 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 18 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
Fuse Memory Usage: 1198916 KB
Fuse CPU Usage: 1010 ms
GCC CPU Usage: 140 ms
Fuse Memory Usage: 1723208 KB
Fuse CPU Usage: 850 ms
GCC CPU Usage: 120 ms

45
xilinx/ALU/iseconfig/ALU.projectmgr
View file

@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c5000000020000000000000000000000000200000064ffffffff000000810000000300000002000001c50000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>addr_instructions - bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
@ -50,7 +50,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000132000000010001000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
@ -79,31 +79,17 @@
<ClosedNode>/bm_data_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_data_test.vhd</ClosedNode>
<ClosedNode>/bm_instr_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|bm_instr_test.vhd</ClosedNode>
<ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
<ClosedNode>/processeur - Behavioral |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|processeur.vhd</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</SelectedItem>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001d9000000020000000000000000000000000200000064ffffffff000000810000000300000002000001d90000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>data_memory - bm_data - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd)</CurrentItem>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
@ -116,6 +102,19 @@
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>

4
xilinx/ALU/iseconfig/processeur.xreport
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@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2021-05-11T15:38:05</DateModified>
<DateModified>2021-05-10T10:47:06</DateModified>
<ModuleName>processeur</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
<DateInitialized>2021-05-10T09:34:56</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>

127
xilinx/ALU/isim.log
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@ -45,129 +45,4 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
# exit 0

13
xilinx/ALU/isim/isim_usage_statistics.html
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@ -2,4 +2,15 @@
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1010 ms, 1198916 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>

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25
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
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@ -2,9 +2,28 @@ Command line:
process_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 54129
-socket 43981
Tue May 11 16:30:48 2021
Mon May 10 12:31:07 2021
Elaboration Time: 0.02 sec
Elaboration Time: 0.01 sec
Current Memory Usage: 189.698 Meg
Total Signals : 109
Total Nets : 10695
Total Signal Drivers : 44
Total Blocks : 14
Total Primitive Blocks : 12
Total Processes : 31
Total Traceable Variables : 16
Total Scalar Nets and Variables : 11197
Total Line Count : 66
Total Simulation Time: 0.04 sec
Current Memory Usage: 265.2 Meg
Mon May 10 12:32:41 2021

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2
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
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@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
char *t14;
char *t15;
LAB0: xsi_set_current_line(57, ng0);
LAB0: xsi_set_current_line(45, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);

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476
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
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@ -298,223 +298,193 @@ LAB24: goto LAB2;
static void work_a_4150868852_3212880686_p_1(char *t0)
{
char t10[16];
char t19[16];
char t27[16];
char t35[16];
char t43[16];
char t51[16];
char t9[16];
char t18[16];
char t26[16];
char t34[16];
char t42[16];
unsigned char t1;
unsigned char t2;
unsigned char t3;
unsigned char t4;
unsigned char t5;
char *t5;
char *t6;
char *t7;
char *t8;
char *t10;
char *t11;
char *t12;
int t13;
unsigned int t14;
unsigned char t15;
int t12;
unsigned int t13;
unsigned char t14;
char *t15;
char *t16;
char *t17;
char *t19;
char *t20;
char *t21;
int t22;
unsigned char t23;
int t21;
unsigned char t22;
char *t23;
char *t24;
char *t25;
char *t27;
char *t28;
char *t29;
int t30;
unsigned char t31;
int t29;
unsigned char t30;
char *t31;
char *t32;
char *t33;
char *t35;
char *t36;
char *t37;
int t38;
unsigned char t39;
int t37;
unsigned char t38;
char *t39;
char *t40;
char *t41;
char *t43;
char *t44;
char *t45;
int t46;
unsigned char t47;
int t45;
unsigned char t46;
char *t47;
char *t48;
char *t49;
char *t50;
char *t51;
char *t52;
char *t53;
int t54;
unsigned char t55;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
char *t63;
char *t64;
char *t65;
char *t66;
char *t67;
LAB0: xsi_set_current_line(181, ng0);
t6 = (t0 + 2152U);
t7 = *((char **)t6);
t6 = (t0 + 17640U);
t8 = (t0 + 18323);
t5 = (t0 + 2152U);
t6 = *((char **)t5);
t5 = (t0 + 17640U);
t7 = (t0 + 18323);
t10 = (t9 + 0U);
t11 = (t10 + 0U);
t12 = (t11 + 0U);
*((int *)t12) = 0;
t12 = (t11 + 4U);
*((int *)t12) = 7;
t12 = (t11 + 8U);
*((int *)t12) = 1;
t13 = (7 - 0);
t14 = (t13 * 1);
t14 = (t14 + 1);
t12 = (t11 + 12U);
*((unsigned int *)t12) = t14;
t15 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t7, t6, t8, t10);
if (t15 == 1)
goto LAB17;
LAB18: t12 = (t0 + 2152U);
t16 = *((char **)t12);
t12 = (t0 + 17640U);
t17 = (t0 + 18331);
t20 = (t19 + 0U);
t21 = (t20 + 0U);
*((int *)t21) = 0;
t21 = (t20 + 4U);
*((int *)t21) = 7;
t21 = (t20 + 8U);
*((int *)t21) = 1;
t22 = (7 - 0);
t14 = (t22 * 1);
t14 = (t14 + 1);
t21 = (t20 + 12U);
*((unsigned int *)t21) = t14;
t23 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t16, t12, t17, t19);
t5 = t23;
LAB19: if (t5 == 1)
*((int *)t11) = 0;
t11 = (t10 + 4U);
*((int *)t11) = 7;
t11 = (t10 + 8U);
*((int *)t11) = 1;
t12 = (7 - 0);
t13 = (t12 * 1);
t13 = (t13 + 1);
t11 = (t10 + 12U);
*((unsigned int *)t11) = t13;
t14 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t5, t7, t9);
if (t14 == 1)
goto LAB14;
LAB15: t21 = (t0 + 2152U);
t24 = *((char **)t21);
t21 = (t0 + 17640U);
t25 = (t0 + 18339);
t28 = (t27 + 0U);
t29 = (t28 + 0U);
*((int *)t29) = 0;
t29 = (t28 + 4U);
*((int *)t29) = 7;
t29 = (t28 + 8U);
*((int *)t29) = 1;
t30 = (7 - 0);
t14 = (t30 * 1);
t14 = (t14 + 1);
t29 = (t28 + 12U);
*((unsigned int *)t29) = t14;
t31 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t24, t21, t25, t27);
t4 = t31;
LAB15: t11 = (t0 + 2152U);
t15 = *((char **)t11);
t11 = (t0 + 17640U);
t16 = (t0 + 18331);
t19 = (t18 + 0U);
t20 = (t19 + 0U);
*((int *)t20) = 0;
t20 = (t19 + 4U);
*((int *)t20) = 7;
t20 = (t19 + 8U);
*((int *)t20) = 1;
t21 = (7 - 0);
t13 = (t21 * 1);
t13 = (t13 + 1);
t20 = (t19 + 12U);
*((unsigned int *)t20) = t13;
t22 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t15, t11, t16, t18);
t4 = t22;
LAB16: if (t4 == 1)
goto LAB11;
LAB12: t29 = (t0 + 2152U);
t32 = *((char **)t29);
t29 = (t0 + 17640U);
t33 = (t0 + 18347);
t36 = (t35 + 0U);
t37 = (t36 + 0U);
*((int *)t37) = 0;
t37 = (t36 + 4U);
*((int *)t37) = 7;
t37 = (t36 + 8U);
*((int *)t37) = 1;
t38 = (7 - 0);
t14 = (t38 * 1);
t14 = (t14 + 1);
t37 = (t36 + 12U);
*((unsigned int *)t37) = t14;
t39 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t32, t29, t33, t35);
t3 = t39;
LAB12: t20 = (t0 + 2152U);
t23 = *((char **)t20);
t20 = (t0 + 17640U);
t24 = (t0 + 18339);
t27 = (t26 + 0U);
t28 = (t27 + 0U);
*((int *)t28) = 0;
t28 = (t27 + 4U);
*((int *)t28) = 7;
t28 = (t27 + 8U);
*((int *)t28) = 1;
t29 = (7 - 0);
t13 = (t29 * 1);
t13 = (t13 + 1);
t28 = (t27 + 12U);
*((unsigned int *)t28) = t13;
t30 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t23, t20, t24, t26);
t3 = t30;
LAB13: if (t3 == 1)
goto LAB8;
LAB9: t37 = (t0 + 2152U);
t40 = *((char **)t37);
t37 = (t0 + 17640U);
t41 = (t0 + 18355);
t44 = (t43 + 0U);
t45 = (t44 + 0U);
*((int *)t45) = 0;
t45 = (t44 + 4U);
*((int *)t45) = 7;
t45 = (t44 + 8U);
*((int *)t45) = 1;
t46 = (7 - 0);
t14 = (t46 * 1);
t14 = (t14 + 1);
t45 = (t44 + 12U);
*((unsigned int *)t45) = t14;
t47 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t40, t37, t41, t43);
t2 = t47;
LAB9: t28 = (t0 + 2152U);
t31 = *((char **)t28);
t28 = (t0 + 17640U);
t32 = (t0 + 18347);
t35 = (t34 + 0U);
t36 = (t35 + 0U);
*((int *)t36) = 0;
t36 = (t35 + 4U);
*((int *)t36) = 7;
t36 = (t35 + 8U);
*((int *)t36) = 1;
t37 = (7 - 0);
t13 = (t37 * 1);
t13 = (t13 + 1);
t36 = (t35 + 12U);
*((unsigned int *)t36) = t13;
t38 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t28, t32, t34);
t2 = t38;
LAB10: if (t2 == 1)
goto LAB5;
LAB6: t45 = (t0 + 2152U);
t48 = *((char **)t45);
t45 = (t0 + 17640U);
t49 = (t0 + 18363);
t52 = (t51 + 0U);
t53 = (t52 + 0U);
*((int *)t53) = 0;
t53 = (t52 + 4U);
*((int *)t53) = 7;
t53 = (t52 + 8U);
*((int *)t53) = 1;
t54 = (7 - 0);
t14 = (t54 * 1);
t14 = (t14 + 1);
t53 = (t52 + 12U);
*((unsigned int *)t53) = t14;
t55 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t48, t45, t49, t51);
t1 = t55;
LAB6: t36 = (t0 + 2152U);
t39 = *((char **)t36);
t36 = (t0 + 17640U);
t40 = (t0 + 18355);
t43 = (t42 + 0U);
t44 = (t43 + 0U);
*((int *)t44) = 0;
t44 = (t43 + 4U);
*((int *)t44) = 7;
t44 = (t43 + 8U);
*((int *)t44) = 1;
t45 = (7 - 0);
t13 = (t45 * 1);
t13 = (t13 + 1);
t44 = (t43 + 12U);
*((unsigned int *)t44) = t13;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t39, t36, t40, t42);
t1 = t46;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB20: t61 = (t0 + 2472U);
t62 = *((char **)t61);
t61 = (t0 + 10360);
t63 = (t61 + 56U);
t64 = *((char **)t63);
t65 = (t64 + 56U);
t66 = *((char **)t65);
memcpy(t66, t62, 8U);
xsi_driver_first_trans_fast(t61);
LAB17: t52 = (t0 + 2472U);
t53 = *((char **)t52);
t52 = (t0 + 10360);
t54 = (t52 + 56U);
t55 = *((char **)t54);
t56 = (t55 + 56U);
t57 = *((char **)t56);
memcpy(t57, t53, 8U);
xsi_driver_first_trans_fast(t52);
LAB2: t67 = (t0 + 10104);
*((int *)t67) = 1;
LAB2: t58 = (t0 + 10104);
*((int *)t58) = 1;
LAB1: return;
LAB3: t53 = (t0 + 1512U);
t56 = *((char **)t53);
t53 = (t0 + 10360);
t57 = (t53 + 56U);
t58 = *((char **)t57);
t59 = (t58 + 56U);
t60 = *((char **)t59);
memcpy(t60, t56, 8U);
xsi_driver_first_trans_fast(t53);
LAB3: t44 = (t0 + 1512U);
t47 = *((char **)t44);
t44 = (t0 + 10360);
t48 = (t44 + 56U);
t49 = *((char **)t48);
t50 = (t49 + 56U);
t51 = *((char **)t50);
memcpy(t51, t47, 8U);
xsi_driver_first_trans_fast(t44);
goto LAB2;
LAB5: t1 = (unsigned char)1;
@ -529,10 +499,7 @@ LAB11: t3 = (unsigned char)1;
LAB14: t4 = (unsigned char)1;
goto LAB16;
LAB17: t5 = (unsigned char)1;
goto LAB19;
LAB21: goto LAB2;
LAB18: goto LAB2;
}
@ -590,7 +557,7 @@ LAB0: xsi_set_current_line(197, ng0);
t1 = (t0 + 2792U);
t2 = *((char **)t1);
t1 = (t0 + 17704U);
t3 = (t0 + 18371);
t3 = (t0 + 18363);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
@ -610,7 +577,7 @@ LAB0: xsi_set_current_line(197, ng0);
LAB4: t17 = (t0 + 2792U);
t18 = *((char **)t17);
t17 = (t0 + 17704U);
t19 = (t0 + 18382);
t19 = (t0 + 18374);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
@ -630,7 +597,7 @@ LAB4: t17 = (t0 + 2792U);
LAB6: t32 = (t0 + 2792U);
t33 = *((char **)t32);
t32 = (t0 + 17704U);
t34 = (t0 + 18393);
t34 = (t0 + 18385);
t37 = (t36 + 0U);
t38 = (t37 + 0U);
*((int *)t38) = 0;
@ -648,7 +615,7 @@ LAB6: t32 = (t0 + 2792U);
goto LAB7;
LAB8:
LAB9: t47 = (t0 + 18404);
LAB9: t47 = (t0 + 18396);
t49 = (t0 + 10424);
t50 = (t49 + 56U);
t51 = *((char **)t50);
@ -661,7 +628,7 @@ LAB2: t54 = (t0 + 10120);
*((int *)t54) = 1;
LAB1: return;
LAB3: t7 = (t0 + 18379);
LAB3: t7 = (t0 + 18371);
t12 = (t0 + 10424);
t13 = (t12 + 56U);
t14 = *((char **)t13);
@ -671,7 +638,7 @@ LAB3: t7 = (t0 + 18379);
xsi_driver_first_trans_fast(t12);
goto LAB2;
LAB5: t23 = (t0 + 18390);
LAB5: t23 = (t0 + 18382);
t27 = (t0 + 10424);
t28 = (t27 + 56U);
t29 = *((char **)t28);
@ -681,7 +648,7 @@ LAB5: t23 = (t0 + 18390);
xsi_driver_first_trans_fast(t27);
goto LAB2;
LAB7: t38 = (t0 + 18401);
LAB7: t38 = (t0 + 18393);
t42 = (t0 + 10424);
t43 = (t42 + 56U);
t44 = *((char **)t43);
@ -739,7 +706,7 @@ LAB0: xsi_set_current_line(214, ng0);
t3 = (t0 + 2792U);
t4 = *((char **)t3);
t3 = (t0 + 17704U);
t5 = (t0 + 18407);
t5 = (t0 + 18399);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
@ -759,7 +726,7 @@ LAB0: xsi_set_current_line(214, ng0);
LAB9: t9 = (t0 + 2792U);
t13 = *((char **)t9);
t9 = (t0 + 17704U);
t14 = (t0 + 18415);
t14 = (t0 + 18407);
t17 = (t16 + 0U);
t18 = (t17 + 0U);
*((int *)t18) = 0;
@ -781,7 +748,7 @@ LAB10: if (t2 == 1)
LAB6: t18 = (t0 + 2792U);
t21 = *((char **)t18);
t18 = (t0 + 17704U);
t22 = (t0 + 18423);
t22 = (t0 + 18415);
t25 = (t24 + 0U);
t26 = (t25 + 0U);
*((int *)t26) = 0;
@ -862,7 +829,7 @@ LAB0: xsi_set_current_line(231, ng0);
t1 = (t0 + 4392U);
t2 = *((char **)t1);
t1 = (t0 + 17800U);
t3 = (t0 + 18431);
t3 = (t0 + 18423);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
@ -933,7 +900,7 @@ LAB0: xsi_set_current_line(233, ng0);
t1 = (t0 + 4392U);
t2 = *((char **)t1);
t1 = (t0 + 17800U);
t3 = (t0 + 18439);
t3 = (t0 + 18431);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
@ -1002,7 +969,7 @@ LAB0: xsi_set_current_line(235, ng0);
t1 = (t0 + 4392U);
t2 = *((char **)t1);
t1 = (t0 + 17800U);
t3 = (t0 + 18447);
t3 = (t0 + 18439);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
@ -1039,109 +1006,76 @@ LAB3: t7 = (t0 + 4232U);
static void work_a_4150868852_3212880686_p_7(char *t0)
{
char t6[16];
char t15[16];
unsigned char t1;
char t5[16];
char *t1;
char *t2;
char *t3;
char *t4;
char *t6;
char *t7;
char *t8;
int t9;
unsigned int t10;
unsigned char t11;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
int t18;
unsigned char t19;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
LAB0: xsi_set_current_line(236, ng0);
t2 = (t0 + 4392U);
t3 = *((char **)t2);
t2 = (t0 + 17800U);
t4 = (t0 + 18455);
t1 = (t0 + 4392U);
t2 = *((char **)t1);
t1 = (t0 + 17800U);
t3 = (t0 + 18447);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
t8 = (t7 + 0U);
*((int *)t8) = 0;
t8 = (t7 + 4U);
*((int *)t8) = 7;
t8 = (t7 + 8U);
*((int *)t8) = 1;
t9 = (7 - 0);
t10 = (t9 * 1);
t10 = (t10 + 1);
t8 = (t7 + 12U);
*((unsigned int *)t8) = t10;
t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6);
if (t11 == 1)
goto LAB5;
LAB6: t8 = (t0 + 4392U);
t12 = *((char **)t8);
t8 = (t0 + 17800U);
t13 = (t0 + 18463);
t16 = (t15 + 0U);
t17 = (t16 + 0U);
*((int *)t17) = 0;
t17 = (t16 + 4U);
*((int *)t17) = 7;
t17 = (t16 + 8U);
*((int *)t17) = 1;
t18 = (7 - 0);
t10 = (t18 * 1);
t10 = (t10 + 1);
t17 = (t16 + 12U);
*((unsigned int *)t17) = t10;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15);
t1 = t19;
LAB7: if (t1 != 0)
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 7;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (7 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4:
LAB8: t25 = (t0 + 4232U);
t26 = *((char **)t25);
t25 = (t0 + 10744);
t27 = (t25 + 56U);
t28 = *((char **)t27);
t29 = (t28 + 56U);
t30 = *((char **)t29);
memcpy(t30, t26, 8U);
xsi_driver_first_trans_fast(t25);
LAB5: t16 = (t0 + 4232U);
t17 = *((char **)t16);
t16 = (t0 + 10744);
t18 = (t16 + 56U);
t19 = *((char **)t18);
t20 = (t19 + 56U);
t21 = *((char **)t20);
memcpy(t21, t17, 8U);
xsi_driver_first_trans_fast(t16);
LAB2: t31 = (t0 + 10200);
*((int *)t31) = 1;
LAB2: t22 = (t0 + 10200);
*((int *)t22) = 1;
LAB1: return;
LAB3: t17 = (t0 + 5672U);
t20 = *((char **)t17);
t17 = (t0 + 10744);
t21 = (t17 + 56U);
t22 = *((char **)t21);
t23 = (t22 + 56U);
t24 = *((char **)t23);
memcpy(t24, t20, 8U);
xsi_driver_first_trans_fast(t17);
LAB3: t7 = (t0 + 5672U);
t11 = *((char **)t7);
t7 = (t0 + 10744);
t12 = (t7 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t11, 8U);
xsi_driver_first_trans_fast(t7);
goto LAB2;
LAB5: t1 = (unsigned char)1;
goto LAB7;
LAB9: goto LAB2;
LAB6: goto LAB2;
}
@ -1196,7 +1130,7 @@ LAB10: xsi_set_current_line(266, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t2 = (t0 + 17560U);
t5 = (t0 + 18479);
t5 = (t0 + 18463);
t8 = (t13 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
@ -1237,7 +1171,7 @@ LAB5: t3 = (t0 + 992U);
LAB7: goto LAB5;
LAB8: xsi_set_current_line(264, ng0);
t2 = (t0 + 18471);
t2 = (t0 + 18455);
t7 = (t0 + 10808);
t8 = (t7 + 56U);
t9 = *((char **)t8);

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xilinx/ALU/processeur.vhd
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@ -178,7 +178,7 @@ begin
QB => C_DIEX_IN
);
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
-- Instantiate pipeline DI_EX
@ -233,12 +233,12 @@ begin
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
A_EXMem_OUT;
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
B_EXMem_OUT;
-- Instantiate banc de données
data_memory: bm_data PORT MAP (
IN_addr => addr_dm_MUX,
IN_data => in_dm_MUX,
IN_data => B_MemRE_IN,
RW => RW_LC,
RST => RST,
CLK => CLK,
@ -249,7 +249,7 @@ begin
Mem_RE : pipeline PORT MAP (
OP_IN => OP_EXMem_OUT,
A_IN => A_EXMem_OUT,
B_IN => B_MemRE_IN,
B_IN => B_EXMem_OUT,
C_IN => x"00",
CLK => CLK,
A_OUT => A_MemRE_OUT,

4
xilinx/ALU/processeur_summary.html
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@ -72,9 +72,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>lun. mai 10 12:32:42 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lun. mai 10 10:45:43 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 05/11/2021 - 15:38:05</center>
<br><center><b>Date Generated:</b> 05/10/2021 - 10:47:06</center>
</BODY></HTML>

165
xilinx/ALU/tests/test_load.wcfg
View file

@ -1,165 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="37" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_data[7:0]</obj_property>
<obj_property name="ObjectShortName">in_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw</obj_property>
<obj_property name="ObjectShortName">rw</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[7:0]</obj_property>
<obj_property name="ObjectShortName">out_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_memory[0:255]</obj_property>
<obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
</wave_config>

165
xilinx/ALU/tests/test_store.wcfg
View file

@ -1,165 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="process_test" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="37" />
<wvobject fp_name="/process_test/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/process_test/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/process_test/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/addr_instructions/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[31:0]</obj_property>
<obj_property name="ObjectShortName">out_data[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/LI_LD/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/DI_EX/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/EX_Mem/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">in_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/in_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">in_data[7:0]</obj_property>
<obj_property name="ObjectShortName">in_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/rw" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rw</obj_property>
<obj_property name="ObjectShortName">rw</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/out_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">out_data[7:0]</obj_property>
<obj_property name="ObjectShortName">out_data[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/data_memory/data_memory" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_memory[0:255]</obj_property>
<obj_property name="ObjectShortName">data_memory[0:255]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_in[7:0]</obj_property>
<obj_property name="ObjectShortName">a_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_in[7:0]</obj_property>
<obj_property name="ObjectShortName">op_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_in[7:0]</obj_property>
<obj_property name="ObjectShortName">b_in[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/op_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op_out[7:0]</obj_property>
<obj_property name="ObjectShortName">op_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/a_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">a_out[7:0]</obj_property>
<obj_property name="ObjectShortName">a_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/Mem_RE/b_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">b_out[7:0]</obj_property>
<obj_property name="ObjectShortName">b_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/registres" type="array" db_ref_id="1">
<obj_property name="ElementShortName">registres[0:15]</obj_property>
<obj_property name="ObjectShortName">registres[0:15]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w_addr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">w_addr[3:0]</obj_property>
<obj_property name="ObjectShortName">w_addr[3:0]</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/w" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">w</obj_property>
<obj_property name="ObjectShortName">w</obj_property>
</wvobject>
<wvobject fp_name="/process_test/uut/banc_registres/data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data[7:0]</obj_property>
<obj_property name="ObjectShortName">data[7:0]</obj_property>
</wvobject>
</wave_config>