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alea ok

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Foussats Morgane 2021-05-18 16:40:36 +02:00
parent 271309e831
commit db6969e20e
70 changed files with 3532 additions and 807 deletions
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123
xilinx/ALU/ALU.gise
View file

@ -22,10 +22,15 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ALU.xise"/> <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ALU.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"> <files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/> <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
@ -37,7 +42,26 @@
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="process_test_beh.prj"/> <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="process_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="process_test_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="process_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="process_test_isim_beh.wdb"/> <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="process_test_isim_beh.wdb"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="processeur.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="processeur.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="processeur.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="processeur.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="processeur.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="processeur.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="processeur.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="processeur.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="processeur.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="processeur.xst"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="processeur_beh.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="processeur_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="processeur_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="processeur_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="processeur_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="processeur_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
@ -49,9 +73,13 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621346572">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/> <outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/> <outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/> <outfile xil_pn:name="bm.vhd"/>
@ -64,11 +92,11 @@
<outfile xil_pn:name="process_test.vhd"/> <outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/> <outfile xil_pn:name="processeur.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1620632845"> <transform xil_pn:end_ts="1621342541" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1621342541">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1620632845"> <transform xil_pn:end_ts="1621342541" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1621342541">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
@ -76,9 +104,14 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621346572">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="alu.vhd"/> <outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/> <outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/> <outfile xil_pn:name="bm.vhd"/>
@ -91,9 +124,14 @@
<outfile xil_pn:name="process_test.vhd"/> <outfile xil_pn:name="process_test.vhd"/>
<outfile xil_pn:name="processeur.vhd"/> <outfile xil_pn:name="processeur.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821"> <transform xil_pn:end_ts="1621346573" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1621346572">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/> <outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/> <outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
@ -101,13 +139,86 @@
<outfile xil_pn:name="process_test_isim_beh.exe"/> <outfile xil_pn:name="process_test_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/> <outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1620641823" xil_pn:in_ck="482655878171119177" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1620641822"> <transform xil_pn:end_ts="1621346668" xil_pn:in_ck="5586040975174613622" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="4561778380439837717" xil_pn:start_ts="1621346668">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="isim.cmd"/> <outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/> <outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="process_test_isim_beh.wdb"/> <outfile xil_pn:name="process_test_isim_beh.wdb"/>
</transform> </transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="7040476308402121676" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="9006895703308992987" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-182187785304845874" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347274" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="1575018628763906789" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347280" xil_pn:in_ck="-4461735689129086876" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5832519991426568012" xil_pn:start_ts="1621347274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="processeur.lso"/>
<outfile xil_pn:name="processeur.ngc"/>
<outfile xil_pn:name="processeur.ngr"/>
<outfile xil_pn:name="processeur.prj"/>
<outfile xil_pn:name="processeur.stx"/>
<outfile xil_pn:name="processeur.syr"/>
<outfile xil_pn:name="processeur.xst"/>
<outfile xil_pn:name="processeur_beh.prj"/>
<outfile xil_pn:name="processeur_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1621347302" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-7234637504262834621" xil_pn:start_ts="1621347302">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1621347306" xil_pn:in_ck="-3700998983167034415" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8547628868292314566" xil_pn:start_ts="1621347302">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="processeur.bld"/>
<outfile xil_pn:name="processeur.ngd"/>
<outfile xil_pn:name="processeur_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1621347309" xil_pn:in_ck="-3700998983167034414" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1621347306">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="processeur_map.map"/>
<outfile xil_pn:name="processeur_map.mrp"/>
</transform>
</transforms> </transforms>
</generated_project> </generated_project>

12
xilinx/ALU/ALU.xise
View file

@ -17,7 +17,7 @@
<files> <files>
<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -27,7 +27,7 @@
</file> </file>
<file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -37,11 +37,11 @@
</file> </file>
<file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -57,11 +57,11 @@
</file> </file>
<file xil_pn:name="pipeline.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="pipeline.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="processeur.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="processeur.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="process_test.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="process_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>

3
xilinx/ALU/_ngo/netlist.lst Normal file
View file

@ -0,0 +1,3 @@
/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280
/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280
OK

15
xilinx/ALU/_xmsgs/map.xmsgs Normal file
View file

@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="Map" num="116" delta="new" >The design is empty. No processing will be done.
</msg>
<msg type="user_fatal" file="Map" num="52" delta="new" >Problem encountered processing RPMs.
</msg>
</messages>

12
xilinx/ALU/_xmsgs/ngdbuild.xmsgs Normal file
View file

@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="578" delta="new" >Design contains no instances.
</msg>
</messages>

2
xilinx/ALU/_xmsgs/pn_parser.xmsgs
View file

@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
</msg> </msg>
</messages> </messages>

54
xilinx/ALU/_xmsgs/xst.xmsgs Normal file
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@ -0,0 +1,54 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Xst" num="0" delta="new" >Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">156</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">addr_instructions</arg>&gt; of block &lt;<arg fmt="%s" index="4">bm_instr</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">163</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">LI_LD</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">184</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">banc_registres</arg>&gt; of block &lt;<arg fmt="%s" index="4">br</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">200</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">DI_EX</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">221</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">UAL</arg>&gt; of block &lt;<arg fmt="%s" index="4">alu</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">237</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">EX_Mem</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">262</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">data_memory</arg>&gt; of block &lt;<arg fmt="%s" index="4">bm_data</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">272</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">Mem_RE</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">N</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">O</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">Z</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">C</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">237</arg>: Output port &lt;<arg fmt="%s" index="3">C_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">EX_Mem</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">272</arg>: Output port &lt;<arg fmt="%s" index="3">C_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">Mem_RE</arg>&gt; is unconnected or connected to loadless signal.
</msg>
</messages>

28
xilinx/ALU/bm_instr.vhd
View file

@ -34,12 +34,36 @@ architecture Behavioral of bm_instr is
type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0); type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
-- instruction "00000110 00000001 00000110 00000000" -- instruction "00000110 00000001 00000110 00000000"
--test afc --test afc
--signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
--test afc cop --test afc cop
signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
--test afc cop alea
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
--test add --test add
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
--test add alea
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
--test sub
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
--test mul
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
--test store
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
--test store alea
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
--test load
--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
begin begin
OUT_data <= instr_memory(to_integer(unsigned(IN_addr))); OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

BIN
xilinx/ALU/bm_instr_isim_beh.exe Executable file
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Binary file not shown.

8
xilinx/ALU/fuse.log
View file

@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
Starting static elaboration Starting static elaboration
Completed static elaboration Completed static elaboration
Fuse Memory Usage: 98520 KB Fuse Memory Usage: 98520 KB
Fuse CPU Usage: 760 ms Fuse CPU Usage: 840 ms
Compiling package standard Compiling package standard
Compiling package std_logic_1164 Compiling package std_logic_1164
Compiling package std_logic_arith Compiling package std_logic_arith
@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish... Waiting for 1 sub-compilation(s) to finish...
Compiled 18 VHDL Units Compiled 18 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
Fuse Memory Usage: 1723208 KB Fuse Memory Usage: 1723384 KB
Fuse CPU Usage: 850 ms Fuse CPU Usage: 980 ms
GCC CPU Usage: 120 ms GCC CPU Usage: 110 ms

16
xilinx/ALU/iseconfig/ALU.projectmgr
View file

@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode> <ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem></SelectedItem> <SelectedItem/>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem> <CurrentItem/>
</ItemView> </ItemView>
<ItemView guiview="File" > <ItemView guiview="File" >
<ClosedNodes> <ClosedNodes>
@ -81,13 +81,13 @@
<ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode> <ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem> <SelectedItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f80000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem> <CurrentItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" > <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes> <ClosedNodes>
@ -107,13 +107,13 @@
<ClosedNodesVersion>1</ClosedNodesVersion> <ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes> </ClosedNodes>
<SelectedItems> <SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem> <SelectedItem></SelectedItem>
</SelectedItems> </SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition> <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition> <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState> <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths> <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem> <CurrentItem></CurrentItem>
</ItemView> </ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" > <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes> <ClosedNodes>
@ -130,5 +130,5 @@
<CurrentItem/> <CurrentItem/>
</ItemView> </ItemView>
<SourceProcessView>000000ff0000000000000002000001a6000000db01000000040100000002</SourceProcessView> <SourceProcessView>000000ff0000000000000002000001a6000000db01000000040100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView> <CurrentView>Implementation</CurrentView>
</Project> </Project>

4
xilinx/ALU/iseconfig/processeur.xreport
View file

@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2021-05-10T10:47:06</DateModified> <DateModified>2021-05-18T16:14:30</DateModified>
<ModuleName>processeur</ModuleName> <ModuleName>processeur</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath> <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory> <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
<DateInitialized>2021-05-10T09:34:56</DateInitialized> <DateInitialized>2021-05-10T09:34:56</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering> <EnableMessageFiltering>false</EnableMessageFiltering>
</header> </header>

70
xilinx/ALU/isim.log
View file

@ -45,4 +45,74 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
# exit 0 # exit 0

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@ -2,14 +2,14 @@
<xtag-section name="ISimStatistics"> <xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 1723384 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>121</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10703</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>36</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 264171 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section> </xtag-section>

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
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@ -2,28 +2,28 @@ Command line:
process_test_isim_beh.exe process_test_isim_beh.exe
-simmode gui -simmode gui
-simrunnum 0 -simrunnum 0
-socket 43981 -socket 37953
Mon May 10 12:31:07 2021 Tue May 18 16:16:44 2021
Elaboration Time: 0.01 sec Elaboration Time: 0.01 sec
Current Memory Usage: 189.698 Meg Current Memory Usage: 189.723 Meg
Total Signals : 109 Total Signals : 121
Total Nets : 10695 Total Nets : 10703
Total Signal Drivers : 44 Total Signal Drivers : 49
Total Blocks : 14 Total Blocks : 14
Total Primitive Blocks : 12 Total Primitive Blocks : 12
Total Processes : 31 Total Processes : 36
Total Traceable Variables : 16 Total Traceable Variables : 16
Total Scalar Nets and Variables : 11197 Total Scalar Nets and Variables : 11205
Total Line Count : 66 Total Line Count : 92
Total Simulation Time: 0.04 sec Total Simulation Time: 0.03 sec
Current Memory Usage: 265.2 Meg Current Memory Usage: 265.224 Meg
Mon May 10 12:32:41 2021 Tue May 18 16:20:51 2021

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@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
char *t14; char *t14;
char *t15; char *t15;
LAB0: xsi_set_current_line(45, ng0); LAB0: xsi_set_current_line(67, ng0);
LAB3: t1 = (t0 + 1512U); LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1); t2 = *((char **)t1);

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xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c
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@ -34,67 +34,74 @@ static void work_a_3650175700_3212880686_p_0(char *t0)
char *t3; char *t3;
unsigned char t4; unsigned char t4;
char *t5; char *t5;
char *t6; unsigned char t6;
char *t7; char *t7;
char *t8; char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 3464U); LAB0: t1 = (t0 + 3624U);
t2 = *((char **)t1); t2 = *((char **)t1);
if (t2 == 0) if (t2 == 0)
goto LAB2; goto LAB2;
LAB3: goto *t2; LAB3: goto *t2;
LAB2: xsi_set_current_line(49, ng0); LAB2: xsi_set_current_line(50, ng0);
LAB6: t2 = (t0 + 3784); LAB6: t2 = (t0 + 3944);
*((int *)t2) = 1; *((int *)t2) = 1;
*((char **)t1) = &&LAB7; *((char **)t1) = &&LAB7;
LAB1: return; LAB1: return;
LAB4: t5 = (t0 + 3784); LAB4: t5 = (t0 + 3944);
*((int *)t5) = 0; *((int *)t5) = 0;
xsi_set_current_line(50, ng0);
t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 3864);
t5 = (t2 + 56U);
t6 = *((char **)t5);
t7 = (t6 + 56U);
t8 = *((char **)t7);
memcpy(t8, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(51, ng0); xsi_set_current_line(51, ng0);
t2 = (t0 + 1192U); t2 = (t0 + 1832U);
t3 = *((char **)t2); t3 = *((char **)t2);
t2 = (t0 + 3928); t4 = *((unsigned char *)t3);
t5 = (t2 + 56U); t6 = (t4 == (unsigned char)3);
t6 = *((char **)t5); if (t6 != 0)
t7 = (t6 + 56U); goto LAB8;
LAB10: xsi_set_current_line(57, ng0);
t2 = (t0 + 6674);
t5 = (t0 + 4024);
t7 = (t5 + 56U);
t8 = *((char **)t7); t8 = *((char **)t7);
memcpy(t8, t3, 8U); t9 = (t8 + 56U);
xsi_driver_first_trans_fast_port(t2); t10 = *((char **)t9);
xsi_set_current_line(52, ng0); memcpy(t10, t2, 8U);
t2 = (t0 + 1352U); xsi_driver_first_trans_fast_port(t5);
t3 = *((char **)t2); xsi_set_current_line(58, ng0);
t2 = (t0 + 3992); t2 = (t0 + 6682);
t5 = (t2 + 56U); t5 = (t0 + 4088);
t6 = *((char **)t5); t7 = (t5 + 56U);
t7 = (t6 + 56U);
t8 = *((char **)t7); t8 = *((char **)t7);
memcpy(t8, t3, 8U); t9 = (t8 + 56U);
xsi_driver_first_trans_fast_port(t2); t10 = *((char **)t9);
xsi_set_current_line(53, ng0); memcpy(t10, t2, 8U);
t2 = (t0 + 1512U); xsi_driver_first_trans_fast_port(t5);
t3 = *((char **)t2); xsi_set_current_line(59, ng0);
t2 = (t0 + 4056); t2 = (t0 + 6690);
t5 = (t2 + 56U); t5 = (t0 + 4152);
t6 = *((char **)t5); t7 = (t5 + 56U);
t7 = (t6 + 56U);
t8 = *((char **)t7); t8 = *((char **)t7);
memcpy(t8, t3, 8U); t9 = (t8 + 56U);
xsi_driver_first_trans_fast_port(t2); t10 = *((char **)t9);
goto LAB2; memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast_port(t5);
xsi_set_current_line(60, ng0);
t2 = (t0 + 6698);
t5 = (t0 + 4216);
t7 = (t5 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast_port(t5);
LAB9: goto LAB2;
LAB5: t3 = (t0 + 1632U); LAB5: t3 = (t0 + 1632U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
@ -105,6 +112,48 @@ LAB5: t3 = (t0 + 1632U);
LAB7: goto LAB5; LAB7: goto LAB5;
LAB8: xsi_set_current_line(52, ng0);
t2 = (t0 + 1032U);
t5 = *((char **)t2);
t2 = (t0 + 4024);
t7 = (t2 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t5, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(53, ng0);
t2 = (t0 + 1192U);
t3 = *((char **)t2);
t2 = (t0 + 4088);
t5 = (t2 + 56U);
t7 = *((char **)t5);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(54, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t2 = (t0 + 4152);
t5 = (t2 + 56U);
t7 = *((char **)t5);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
xsi_set_current_line(55, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t2 = (t0 + 4216);
t5 = (t2 + 56U);
t7 = *((char **)t5);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t3, 8U);
xsi_driver_first_trans_fast_port(t2);
goto LAB9;
} }

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xilinx/ALU/pipeline.vhd
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@ -35,6 +35,7 @@ entity pipeline is
B_IN : in STD_LOGIC_VECTOR (7 downto 0); B_IN : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC_VECTOR (7 downto 0); C_IN : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC; CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
A_OUT : out STD_LOGIC_VECTOR (7 downto 0); A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
B_OUT : out STD_LOGIC_VECTOR (7 downto 0); B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
@ -47,10 +48,17 @@ begin
process process
begin begin
wait until rising_edge(CLK); wait until rising_edge(CLK);
OP_OUT <= OP_IN; if (EN = '1') then
A_OUT <= A_IN; OP_OUT <= OP_IN;
B_OUT <= B_IN; A_OUT <= A_IN;
C_OUT <= C_IN; B_OUT <= B_IN;
end process; C_OUT <= C_IN;
else
OP_OUT <= "00000000";
A_OUT <= "00000000";
B_OUT <= "00000000";
C_OUT <= "00000000";
end if;
end process;
end Behavioral; end Behavioral;

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xilinx/ALU/processeur.bld Normal file
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@ -0,0 +1,42 @@
Release 13.4 ngdbuild O.87xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line:
/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc
processeur.ngd
Reading NGO file
"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc"
...
Loading design module
"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc"..
.
WARNING:NgdBuild:578 - Design contains no instances.
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Total memory usage is 398744 kilobytes
Writing NGD file "processeur.ngd" ...
Total REAL time to NGDBUILD completion: 1 sec
Total CPU time to NGDBUILD completion: 1 sec
Writing NGDBUILD log file "processeur.bld"...

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xst -intstyle ise -ifn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.xst" -ofn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc processeur.ngd
map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf

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work

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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$3cx5>443JF@86MCK148GIM609<0OAE=7178GIM5P11H@F<W1926?FJL19?0OAEN169@HNG6L;=0OAEN1E64?FJLI8N396MCKC36?FJLK8?0OAEK149@HNBQk2IGGIXPDHTJ@@3<KEAMT55LLJD[5=6>3JEFADZ[EE58GWCF\LN=7AALKDF4?II@AJKG46A!86zg[I2<XHX_:6^\DNLF7>TT\8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI;5\OTP@A3=T\H^^_95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;XGPe>vugjoxh{}109{g3ukp8<&? m|g207yEFwi2JKt?65F;095~U6<38=6<951265700=:;2<jv`=4;38j73=>2.9?7<=;|Q27?4128=1=>:9344967>?82n947>51;3xW42=:?0:;7?<47162?450>l0zY?k:182>4<7sZ;?6?8516827104=?09>59i;%02>40<,821>45m2983>7<729qC>=5+1g81<>"6k3:0(<l5269j5?6=3`;j6=44}|~DEE|i32=i=7987CDG}7uIJ[wpNO

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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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XILINX-XDB 0.1 STUB 0.1 ASCII
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vhdl work "pipeline.vhd"
vhdl work "br.vhd"
vhdl work "bm_instr.vhd"
vhdl work "bm.vhd"
vhdl work "alu.vhd"
vhdl work "processeur.vhd"

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Release 13.4 - xst O.87xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.03 secs
-->
Reading design: processeur.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "processeur.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "processeur"
Output Format : NGC
Target Device : xc6slx16-3-csg324
---- Source Options
Top Module Name : processeur
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
Parsing entity <pipeline>.
Parsing architecture <Behavioral> of entity <pipeline>.
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
Parsing entity <br>.
Parsing architecture <Behavioral> of entity <br>.
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
Parsing entity <bm_instr>.
Parsing architecture <Behavioral> of entity <bm_instr>.
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
Parsing entity <bm_data>.
Parsing architecture <Behavioral> of entity <bm_data>.
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
Parsing entity <alu>.
Parsing architecture <Behavioral> of entity <alu>.
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
Parsing entity <processeur>.
Parsing architecture <Behavioral> of entity <processeur>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <processeur> (architecture <Behavioral>) from library <work>.
Elaborating entity <bm_instr> (architecture <Behavioral>) from library <work>.
Elaborating entity <pipeline> (architecture <Behavioral>) from library <work>.
Elaborating entity <br> (architecture <Behavioral>) from library <work>.
Elaborating entity <alu> (architecture <Behavioral>) from library <work>.
Elaborating entity <bm_data> (architecture <Behavioral>) from library <work>.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance <addr_instructions> of block <bm_instr> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance <LI_LD> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance <banc_registres> of block <br> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance <DI_EX> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance <UAL> of block <alu> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance <EX_Mem> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance <data_memory> of block <bm_data> are unconnected in block <processeur>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance <Mem_RE> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <processeur>.
Related source file is "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd".
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <N> of the instance <UAL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <O> of the instance <UAL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <Z> of the instance <UAL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <C> of the instance <UAL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port <C_OUT> of the instance <EX_Mem> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port <C_OUT> of the instance <Mem_RE> is unconnected or connected to loadless signal.
Summary:
no macro.
Unit <processeur> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <processeur> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block processeur, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : processeur.ngc
Primitive and Black Box Usage:
------------------------------
Device utilization summary:
---------------------------
Selected Device : 6slx16csg324-3
Slice Logic Utilization:
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 0
Number with an unused Flip Flop: 0 out of 0
Number with an unused LUT: 0 out of 0
Number of fully used LUT-FF pairs: 0 out of 0
Number of unique control sets: 0
IO Utilization:
Number of IOs: 2
Number of bonded IOBs: 0 out of 232 0%
Specific Feature Utilization:
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Cross Clock Domains Report:
--------------------------
=========================================================================
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 2.94 secs
-->
Total memory usage is 389560 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 8 ( 0 filtered)
Number of infos : 7 ( 0 filtered)

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---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Company: -- Company:
-- Engineer: -- Engineer:
-- --
-- Create Date: 12:52:06 05/04/2021 -- Create Date: 12:52:06 05/04/2021
-- Design Name: -- Design Name:
-- Module Name: processeur - Behavioral -- Module Name: processeur - Behavioral
-- Project Name: -- Project Name:
-- Target Devices: -- Target Devices:
-- Tool versions: -- Tool versions:
-- Description: -- Description:
-- --
-- Dependencies: -- Dependencies:
-- --
-- Revision: -- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
-- Additional Comments: -- Additional Comments:
-- --
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using -- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values -- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL; --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code. -- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity processeur is entity processeur is
Port ( CLK: in STD_LOGIC ; Port ( CLK: in STD_LOGIC ;
RST : in STD_LOGIC); RST : in STD_LOGIC);
end processeur; end processeur;
architecture Behavioral of processeur is architecture Behavioral of processeur is
COMPONENT bm_instr COMPONENT bm_instr
PORT( PORT(
IN_addr : IN std_logic_vector(7 downto 0); IN_addr : IN std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(31 downto 0); OUT_data : OUT std_logic_vector(31 downto 0);
CLK : IN std_logic CLK : IN std_logic
); );
END COMPONENT; END COMPONENT;
COMPONENT pipeline COMPONENT pipeline
PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0); PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0);
A_IN : in STD_LOGIC_VECTOR (7 downto 0); A_IN : in STD_LOGIC_VECTOR (7 downto 0);
B_IN : in STD_LOGIC_VECTOR (7 downto 0); B_IN : in STD_LOGIC_VECTOR (7 downto 0);
C_IN : in STD_LOGIC_VECTOR (7 downto 0); C_IN : in STD_LOGIC_VECTOR (7 downto 0);
CLK : IN std_logic; CLK : IN std_logic;
OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); EN : in STD_LOGIC;
A_OUT : out STD_LOGIC_VECTOR (7 downto 0); OP_OUT : out STD_LOGIC_VECTOR (7 downto 0);
B_OUT : out STD_LOGIC_VECTOR (7 downto 0); A_OUT : out STD_LOGIC_VECTOR (7 downto 0);
C_OUT : out STD_LOGIC_VECTOR (7 downto 0) B_OUT : out STD_LOGIC_VECTOR (7 downto 0);
); C_OUT : out STD_LOGIC_VECTOR (7 downto 0)
END COMPONENT; );
END COMPONENT;
COMPONENT br
PORT( COMPONENT br
A_addr : IN std_logic_vector(3 downto 0); PORT(
B_addr : IN std_logic_vector(3 downto 0); A_addr : IN std_logic_vector(3 downto 0);
W_addr : IN std_logic_vector(3 downto 0); B_addr : IN std_logic_vector(3 downto 0);
W : IN std_logic; W_addr : IN std_logic_vector(3 downto 0);
Data : IN std_logic_vector(7 downto 0); W : IN std_logic;
RST : IN std_logic; Data : IN std_logic_vector(7 downto 0);
CLK : IN std_logic; RST : IN std_logic;
QA : OUT std_logic_vector(7 downto 0); CLK : IN std_logic;
QB : OUT std_logic_vector(7 downto 0) QA : OUT std_logic_vector(7 downto 0);
); QB : OUT std_logic_vector(7 downto 0)
END COMPONENT; );
END COMPONENT;
COMPONENT alu
PORT( COMPONENT alu
A : IN std_logic_vector(7 downto 0); PORT(
B : IN std_logic_vector(7 downto 0); A : IN std_logic_vector(7 downto 0);
Ctrl_Alu : IN std_logic_vector(2 downto 0); B : IN std_logic_vector(7 downto 0);
N : OUT std_logic; Ctrl_Alu : IN std_logic_vector(2 downto 0);
O : OUT std_logic; N : OUT std_logic;
Z : OUT std_logic; O : OUT std_logic;
C : OUT std_logic; Z : OUT std_logic;
S : OUT std_logic_vector(7 downto 0) C : OUT std_logic;
); S : OUT std_logic_vector(7 downto 0)
END COMPONENT; );
END COMPONENT;
COMPONENT bm_data
PORT( COMPONENT bm_data
IN_addr : IN std_logic_vector(7 downto 0); PORT(
IN_data : IN std_logic_vector(7 downto 0); IN_addr : IN std_logic_vector(7 downto 0);
RW : IN std_logic; IN_data : IN std_logic_vector(7 downto 0);
RST : IN std_logic; RW : IN std_logic;
CLK : IN std_logic; RST : IN std_logic;
OUT_data : OUT std_logic_vector(7 downto 0) CLK : IN std_logic;
); OUT_data : OUT std_logic_vector(7 downto 0)
END COMPONENT; );
END COMPONENT;
--Inputs
signal IP : std_logic_vector(7 downto 0) := (others => '0');
signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal OUT_data : std_logic_vector(31 downto 0);
signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
signal A_LIDI_OUT : std_logic_vector(7 downto 0);
signal B_LIDI_OUT : std_logic_vector(7 downto 0);
signal C_LIDI_OUT : std_logic_vector(7 downto 0);
signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
signal A_DIEX_OUT : std_logic_vector(7 downto 0);
signal B_DIEX_OUT : std_logic_vector(7 downto 0);
signal C_DIEX_OUT : std_logic_vector(7 downto 0);
signal O_ALU_OUT : std_logic;
signal N_ALU_OUT : std_logic;
signal Z_ALU_OUT : std_logic;
signal C_ALU_OUT : std_logic;
signal A_EXMem_OUT : std_logic_vector(7 downto 0);
signal B_EXMem_OUT : std_logic_vector(7 downto 0);
signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
signal A_MemRE_OUT : std_logic_vector(7 downto 0);
signal B_MemRE_OUT : std_logic_vector(7 downto 0);
signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
--AUX
signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
signal RW_LC : std_logic;
signal addr_dm_MUX : std_logic_vector(7 downto 0);
signal in_dm_MUX : std_logic_vector(7 downto 0);
signal out_dm_MUX : std_logic_vector(7 downto 0);
signal B_EXMem_IN : std_logic_vector(7 downto 0);
signal W_br_LC : std_logic;
signal S_IN_MUX : std_logic_vector(7 downto 0);
signal B_MemRE_IN : std_logic_vector(7 downto 0);
--alea
signal li_di_r_b : std_logic;
signal li_di_r_c : std_logic;
signal di_ex_w_a : std_logic;
signal ex_mem_w_a : std_logic;
signal alea : std_logic;
--Inputs begin
signal IP : std_logic_vector(7 downto 0) := (others => '0');
signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); -- Instantiate adresse des instructions
addr_instructions: bm_instr PORT MAP (
IN_addr => IP,
OUT_data => OUT_data,
CLK => CLK
);
signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); -- Instantiate pipeline LI_LD
signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); LI_LD : pipeline PORT MAP (
OP_IN => OUT_data(31 downto 24),
--Outputs A_IN => OUT_data(23 downto 16),
signal OUT_data : std_logic_vector(31 downto 0); B_IN => OUT_data(15 downto 8),
C_IN => OUT_data(7 downto 0),
signal OP_LIDI_OUT : std_logic_vector(7 downto 0); CLK => CLK,
signal A_LIDI_OUT : std_logic_vector(7 downto 0); EN => alea,
signal B_LIDI_OUT : std_logic_vector(7 downto 0); A_OUT => A_LIDI_OUT,
signal C_LIDI_OUT : std_logic_vector(7 downto 0); B_OUT => B_LIDI_OUT,
C_OUT => C_LIDI_OUT,
signal OP_DIEX_OUT : std_logic_vector(7 downto 0); OP_OUT => OP_LIDI_OUT
signal A_DIEX_OUT : std_logic_vector(7 downto 0); );
signal B_DIEX_OUT : std_logic_vector(7 downto 0); W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
signal C_DIEX_OUT : std_logic_vector(7 downto 0); '0';
signal O_ALU_OUT : std_logic;
signal N_ALU_OUT : std_logic;
signal Z_ALU_OUT : std_logic;
signal C_ALU_OUT : std_logic;
signal A_EXMem_OUT : std_logic_vector(7 downto 0);
signal B_EXMem_OUT : std_logic_vector(7 downto 0);
signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
signal A_MemRE_OUT : std_logic_vector(7 downto 0);
signal B_MemRE_OUT : std_logic_vector(7 downto 0);
signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
--AUX
signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
signal RW_LC : std_logic;
signal addr_dm_MUX : std_logic_vector(7 downto 0);
signal in_dm_MUX : std_logic_vector(7 downto 0);
signal out_dm_MUX : std_logic_vector(7 downto 0);
signal B_EXMem_IN : std_logic_vector(7 downto 0);
signal W_br_LC : std_logic;
signal S_IN_MUX : std_logic_vector(7 downto 0);
signal B_MemRE_IN : std_logic_vector(7 downto 0);
begin
-- Instantiate adresse des instructions
addr_instructions: bm_instr PORT MAP (
IN_addr => IP,
OUT_data => OUT_data,
CLK => CLK
);
-- Instantiate pipeline LI_LD
LI_LD : pipeline PORT MAP (
OP_IN => OUT_data(31 downto 24),
A_IN => OUT_data(23 downto 16),
B_IN => OUT_data(15 downto 8),
C_IN => OUT_data(7 downto 0),
CLK => CLK,
A_OUT => A_LIDI_OUT,
B_OUT => B_LIDI_OUT,
C_OUT => C_LIDI_OUT,
OP_OUT => OP_LIDI_OUT
);
W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
'0';
-- Instanciate banc de registre
banc_registres : br PORT MAP (
A_addr => B_LIDI_OUT(3 downto 0),
B_addr => C_LIDI_OUT(3 downto 0),
W_addr => A_MemRE_OUT(3 downto 0),
W => W_br_LC, --ATTENTION LC
Data => B_MemRE_OUT,
RST => RST,
CLK => CLK,
QA => QA_IN_MUX,
QB => C_DIEX_IN
);
B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
-- Instantiate pipeline DI_EX
DI_EX : pipeline PORT MAP (
OP_IN => OP_LIDI_OUT,
A_IN => A_LIDI_OUT,
B_IN => B_DIEX_IN,
C_IN => C_DIEX_IN,
CLK => CLK,
A_OUT => A_DIEX_OUT,
B_OUT => B_DIEX_OUT,
C_OUT => C_DIEX_OUT,
OP_OUT => OP_DIEX_OUT
);
Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else
"010" when OP_DIEX_OUT = x"03" else
"011" when OP_DIEX_OUT = x"02" else
"000";
-- Instantiate alu
UAL : alu PORT MAP (
A => B_DIEX_OUT,
B => C_DIEX_OUT,
Ctrl_Alu =>Ctr_AlU_LC,
N => N_ALU_OUT,
O => O_ALU_OUT,
Z => Z_ALU_OUT,
C => C_ALU_OUT,
S => S_IN_MUX
);
B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else
B_DIEX_OUT ;
--alea LI_DI
-- Instantiate pipeline EX_Mem li_di_r_b <= '1' when OUT_data(31 downto 24) = x"05" or OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" or OUT_data(31 downto 24) = x"08"
EX_Mem : pipeline PORT MAP ( else '0';
OP_IN => OP_DIEX_OUT, li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04"
A_IN => A_DIEX_OUT, else '0';
B_IN => B_EXMem_IN, -- Instanciate banc de registre
C_IN => x"00", banc_registres : br PORT MAP (
CLK => CLK, A_addr => B_LIDI_OUT(3 downto 0),
A_OUT => A_EXMem_OUT, B_addr => C_LIDI_OUT(3 downto 0),
B_OUT => B_EXMem_OUT, W_addr => A_MemRE_OUT(3 downto 0),
C_OUT => open, W => W_br_LC, --ATTENTION LC
OP_OUT => OP_EXMem_OUT Data => B_MemRE_OUT,
); RST => RST,
CLK => CLK,
RW_LC <= '0' when OP_EXMem_OUT = x"08" else QA => QA_IN_MUX,
'1'; QB => C_DIEX_IN
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else );
A_EXMem_OUT;
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
B_EXMem_OUT;
-- Instantiate banc de données -- Instantiate pipeline DI_EX
data_memory: bm_data PORT MAP ( DI_EX : pipeline PORT MAP (
IN_addr => addr_dm_MUX, OP_IN => OP_LIDI_OUT,
IN_data => B_MemRE_IN, A_IN => A_LIDI_OUT,
RW => RW_LC, B_IN => B_DIEX_IN,
RST => RST, C_IN => C_DIEX_IN,
CLK => CLK, CLK => CLK,
OUT_data => out_dm_MUX EN => '1',
); A_OUT => A_DIEX_OUT,
B_OUT => B_DIEX_OUT,
C_OUT => C_DIEX_OUT,
OP_OUT => OP_DIEX_OUT
);
Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else
"010" when OP_DIEX_OUT = x"03" else
"011" when OP_DIEX_OUT = x"02" else
"000";
-- alea DI_EX
di_ex_w_a <= '0' when OP_LIDI_OUT = x"08" or OP_LIDI_OUT = x"00"
else '1';
-- Instantiate alu
UAL : alu PORT MAP (
A => B_DIEX_OUT,
B => C_DIEX_OUT,
Ctrl_Alu =>Ctr_AlU_LC,
N => N_ALU_OUT,
O => O_ALU_OUT,
Z => Z_ALU_OUT,
C => C_ALU_OUT,
S => S_IN_MUX
);
B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else
B_DIEX_OUT ;
-- Instantiate pipeline EX_Mem
EX_Mem : pipeline PORT MAP (
OP_IN => OP_DIEX_OUT,
A_IN => A_DIEX_OUT,
B_IN => B_EXMem_IN,
C_IN => x"00",
CLK => CLK,
EN => '1',
A_OUT => A_EXMem_OUT,
B_OUT => B_EXMem_OUT,
C_OUT => open,
OP_OUT => OP_EXMem_OUT
);
RW_LC <= '0' when OP_EXMem_OUT = x"08" else
'1';
addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
A_EXMem_OUT;
in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08";
B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
B_EXMem_OUT;
-- alea ex_mem
ex_mem_w_a <= '0' when OP_DIEX_OUT = x"08" or OP_DIEX_OUT = x"00"
else '1';
-- Instantiate banc de données
data_memory: bm_data PORT MAP (
IN_addr => addr_dm_MUX,
IN_data => in_dm_MUX,
RW => RW_LC,
RST => RST,
CLK => CLK,
OUT_data => out_dm_MUX
);
-- Instantiate pipeline Mem_RE
Mem_RE : pipeline PORT MAP (
OP_IN => OP_EXMem_OUT,
A_IN => A_EXMem_OUT,
B_IN => B_MemRE_IN,
C_IN => x"00",
CLK => CLK,
EN => '1',
A_OUT => A_MemRE_OUT,
B_OUT => B_MemRE_OUT,
C_OUT => open,
OP_OUT => OP_MemRE_OUT
);
alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or
(li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or
(li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or
(li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else
'1';
-- Instantiate pipeline Mem_RE process
Mem_RE : pipeline PORT MAP (
OP_IN => OP_EXMem_OUT,
A_IN => A_EXMem_OUT,
B_IN => B_EXMem_OUT,
C_IN => x"00",
CLK => CLK,
A_OUT => A_MemRE_OUT,
B_OUT => B_MemRE_OUT,
C_OUT => open,
OP_OUT => OP_MemRE_OUT
);
process
begin begin
wait until rising_edge(CLK); wait until rising_edge(CLK);
if rst = '0' then if rst = '0' then
IP <= x"00"; IP <= x"00";
else else
IP <= IP + "00000001"; if alea = '1' then
IP <= IP + "00000001";
end if;
end if; end if;
end process; end process;
end Behavioral; end Behavioral;

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xilinx/ALU/processeur.xst Normal file
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn processeur.prj
-ofn processeur
-ofmt NGC
-p xc6slx16-3-csg324
-top processeur
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

404
xilinx/ALU/processeur_envsettings.html Normal file
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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:<br>/usr/local/insa/lib:<br>$LD_LIBRARY_PATH</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:<br>/usr/local/insa/lib:<br>$LD_LIBRARY_PATH</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>PATH</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:<br>/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:<br>/usr/local/insa/shared/opam/system/bin:<br>/usr/local/insa/lustre-v4-III-dc-linux64/bin:<br>/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:<br>/usr/local/insa/anaconda/bin:<br>/usr/local/insa/bin:<br>/usr/local/insa/sbin:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/sbin:<br>/usr/bin:<br>/sbin:<br>/bin:<br>/usr/games:<br>/usr/local/games:<br>/usr/local/insa/tina/bin:<br>/snap/bin</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:<br>/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:<br>/usr/local/insa/shared/opam/system/bin:<br>/usr/local/insa/lustre-v4-III-dc-linux64/bin:<br>/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:<br>/usr/local/insa/anaconda/bin:<br>/usr/local/insa/bin:<br>/usr/local/insa/sbin:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/sbin:<br>/usr/bin:<br>/sbin:<br>/bin:<br>/usr/games:<br>/usr/local/games:<br>/usr/local/insa/tina/bin:<br>/snap/bin</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic</td>
<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>processeur.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>processeur</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx16-3-csg324</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>processeur</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>Speed</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-power</td>
<td>Power Reduction</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>As_Optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>AllClockNets</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-dsp_utilization_ratio</td>
<td>DSP Utilization Ratio</td>
<td>100</td>
<td>100</td>
</tr>
<tr>
<td>-reduce_control_sets</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>Yes</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_dsp48</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>100000</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>16</td>
<td>16</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>No</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>No</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>Auto</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>Yes</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc6slx16-csg324-3</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4277.214 MHz</td>
<td>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4276.892 MHz</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>Host</td>
<td>insa-11291</td>
<td>insa-11291</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Name</td>
<td>Ubuntu</td>
<td>Ubuntu</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>Ubuntu 18.04.5 LTS</td>
<td>Ubuntu 18.04.5 LTS</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
</TABLE>
</BODY> </HTML>

23
xilinx/ALU/processeur_map.map Normal file
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@ -0,0 +1,23 @@
Release 13.4 Map O.87xd (lin64)
Xilinx Map Application Log File for Design 'processeur'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue May 18 16:15:07 2021
ERROR:Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.
Design Summary
--------------
Number of errors : 2
Number of warnings : 0

31
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@ -0,0 +1,31 @@
Release 13.4 Map O.87xd (lin64)
Xilinx Mapping Report File for Design 'processeur'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf
Target Device : xc6slx16
Target Package : csg324
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue May 18 16:15:07 2021
Design Summary
--------------
Number of errors : 2
Number of warnings : 0
Section 1 - Errors
------------------
ERROR:Map:116 - The design is empty. No processing will be done.
ERROR:Map:52 - Problem encountered processing RPMs.
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------

67
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@ -0,0 +1,67 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="13.4">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Tue May 18 16:15:05 2021">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:/usr/local/insa/lib:$LD_LIBRARY_PATH"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:/usr/local/insa/shared/opam/system/bin:/usr/local/insa/lustre-v4-III-dc-linux64/bin:/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:/usr/local/insa/anaconda/bin:/usr/local/insa/bin:/usr/local/insa/sbin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/usr/local/insa/tina/bin:/snap/bin"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 18.04.5 LTS"/>
</item>
<item stringID="User_EnvHost" value="insa-11291"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz"/>
<item stringID="speed" value="4276.892 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx16-csg324-3"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="1"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"/>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"/>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>

29
xilinx/ALU/processeur_summary.html
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@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status (05/18/2021 - 16:15:09)</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ALU.xise</TD> <TD>ALU.xise</TD>
@ -13,18 +13,20 @@
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>processeur</TD> <TD>processeur</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD> <TD>Mapped (Failed)</TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-3csg324</TD> <TD>xc6slx16-3csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD> <TD>
<font color="red"; face="Arial"><b>X </b></font>
<A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/*.xmsgs?&DataKey=Error'>2 Errors (2 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD> <TD ALIGN=LEFT><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/*.xmsgs?&DataKey=Warning'>9 Warnings (9 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@ -41,7 +43,10 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD> <TD>
<A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD> <TD>&nbsp;&nbsp;</TD>
</TR> </TR>
@ -49,7 +54,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
</TABLE>
@ -61,9 +68,9 @@
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>mar. mai 18 16:14:40 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/xst.xmsgs?&DataKey=Warning'>8 Warnings (8 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/xst.xmsgs?&DataKey=Info'>7 Infos (7 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.bld'>Translation Report</A></TD><TD>Current</TD><TD>mar. mai 18 16:15:06 2021</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>mar. mai 18 16:15:09 2021</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/map.xmsgs?&DataKey=Error'>2 Errors (2 new)</A></TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
@ -72,9 +79,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>lun. mai 10 10:45:43 2021</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. mai 18 16:15:36 2021</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 05/10/2021 - 10:47:06</center> <br><center><b>Date Generated:</b> 05/18/2021 - 16:16:17</center>
</BODY></HTML> </BODY></HTML>

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xilinx/ALU/processeur_xst.xrpt Normal file
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@ -0,0 +1,129 @@
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="13.4">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Tue May 18 16:14:37 2021">
<section stringID="User_Env">
<table stringID="User_EnvVar">
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<row stringID="row" value="0">
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<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:/usr/local/insa/lib:$LD_LIBRARY_PATH"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic"/>
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<row stringID="row" value="2">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:/usr/local/insa/shared/opam/system/bin:/usr/local/insa/lustre-v4-III-dc-linux64/bin:/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:/usr/local/insa/anaconda/bin:/usr/local/insa/bin:/usr/local/insa/sbin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/usr/local/insa/tina/bin:/snap/bin"/>
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<item stringID="variable" value="XILINX"/>
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</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Ubuntu"/>
<item stringID="User_EnvOsrelease" value="Ubuntu 18.04.5 LTS"/>
</item>
<item stringID="User_EnvHost" value="insa-11291"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz"/>
<item stringID="speed" value="4277.214 MHz"/>
</row>
</table>
</section>
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<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
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<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
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<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE"/>
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</document>

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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Tue May 18 16:14:35 2021">
<section name="Project Information" visible="false">
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<property name="ProjectIteration" value="0" type="project"/>
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<property name="ProjectCreationTimestamp" value="2021-04-13T10:09:14" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/process_test" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2021-04-13T10:09:14" type="design"/>
<property name="PROP_intWbtProjectID" value="E745AC3463D83535AAF1ABA5736091BC" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.process_test" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xc6slx16" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
<property name="PROP_DevPackage" value="csg324" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="11" type="source"/>
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