diff --git a/xilinx/ALU/ALU.gise b/xilinx/ALU/ALU.gise index 7a6fa15..e76ce05 100644 --- a/xilinx/ALU/ALU.gise +++ b/xilinx/ALU/ALU.gise @@ -22,10 +22,15 @@ + + + + + @@ -37,7 +42,26 @@ + + + + + + + + + + + + + + + + + + + @@ -49,9 +73,13 @@ - + + + + + @@ -64,11 +92,11 @@ - + - + @@ -76,9 +104,14 @@ - + + + + + + @@ -91,9 +124,14 @@ - + + + + + + @@ -101,13 +139,86 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/ALU/ALU.xise b/xilinx/ALU/ALU.xise index ecd5fc7..99ead22 100644 --- a/xilinx/ALU/ALU.xise +++ b/xilinx/ALU/ALU.xise @@ -17,7 +17,7 @@ - + @@ -27,7 +27,7 @@ - + @@ -37,11 +37,11 @@ - + - + @@ -57,11 +57,11 @@ - + - + diff --git a/xilinx/ALU/_ngo/netlist.lst b/xilinx/ALU/_ngo/netlist.lst new file mode 100644 index 0000000..52fad93 --- /dev/null +++ b/xilinx/ALU/_ngo/netlist.lst @@ -0,0 +1,3 @@ +/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280 +/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280 +OK diff --git a/xilinx/ALU/_xmsgs/map.xmsgs b/xilinx/ALU/_xmsgs/map.xmsgs new file mode 100644 index 0000000..36d6790 --- /dev/null +++ b/xilinx/ALU/_xmsgs/map.xmsgs @@ -0,0 +1,15 @@ + + + +The design is empty. No processing will be done. + + +Problem encountered processing RPMs. + + + + diff --git a/xilinx/ALU/_xmsgs/ngdbuild.xmsgs b/xilinx/ALU/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..e7f0f74 --- /dev/null +++ b/xilinx/ALU/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,12 @@ + + + +Design contains no instances. + + + + diff --git a/xilinx/ALU/_xmsgs/pn_parser.xmsgs b/xilinx/ALU/_xmsgs/pn_parser.xmsgs index 0e8e45c..e6bbd48 100644 --- a/xilinx/ALU/_xmsgs/pn_parser.xmsgs +++ b/xilinx/ALU/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work diff --git a/xilinx/ALU/_xmsgs/xst.xmsgs b/xilinx/ALU/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..2d3bb0e --- /dev/null +++ b/xilinx/ALU/_xmsgs/xst.xmsgs @@ -0,0 +1,54 @@ + + + +Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance <addr_instructions> of block <bm_instr> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance <LI_LD> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance <banc_registres> of block <br> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance <DI_EX> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance <UAL> of block <alu> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance <EX_Mem> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance <data_memory> of block <bm_data> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance <Mem_RE> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <N> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <O> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <Z> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <C> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port <C_OUT> of the instance <EX_Mem> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port <C_OUT> of the instance <Mem_RE> is unconnected or connected to loadless signal. + + + + diff --git a/xilinx/ALU/bm_instr.vhd b/xilinx/ALU/bm_instr.vhd index a51c05d..fb4057e 100644 --- a/xilinx/ALU/bm_instr.vhd +++ b/xilinx/ALU/bm_instr.vhd @@ -34,12 +34,36 @@ architecture Behavioral of bm_instr is type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0); -- instruction "00000110 00000001 00000110 00000000" --test afc ---signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); +signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); --test afc cop -signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); +--test afc cop alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); --test add --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); +--test add alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); +--test sub + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000"); + +--test mul + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000"); + +--test store + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000"); + +--test store alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000"); + +--test load + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000"); + + begin OUT_data <= instr_memory(to_integer(unsigned(IN_addr))); diff --git a/xilinx/ALU/bm_instr_isim_beh.exe b/xilinx/ALU/bm_instr_isim_beh.exe new file mode 100755 index 0000000..beb9ccd Binary files /dev/null and b/xilinx/ALU/bm_instr_isim_beh.exe differ diff --git a/xilinx/ALU/fuse.log b/xilinx/ALU/fuse.log index 8225c6d..c467397 100644 --- a/xilinx/ALU/fuse.log +++ b/xilinx/ALU/fuse.log @@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU Starting static elaboration Completed static elaboration Fuse Memory Usage: 98520 KB -Fuse CPU Usage: 760 ms +Fuse CPU Usage: 840 ms Compiling package standard Compiling package std_logic_1164 Compiling package std_logic_arith @@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 18 VHDL Units Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe -Fuse Memory Usage: 1723208 KB -Fuse CPU Usage: 850 ms -GCC CPU Usage: 120 ms +Fuse Memory Usage: 1723384 KB +Fuse CPU Usage: 980 ms +GCC CPU Usage: 110 ms diff --git a/xilinx/ALU/iseconfig/ALU.projectmgr b/xilinx/ALU/iseconfig/ALU.projectmgr index 322e466..3ce4206 100644 --- a/xilinx/ALU/iseconfig/ALU.projectmgr +++ b/xilinx/ALU/iseconfig/ALU.projectmgr @@ -23,13 +23,13 @@ Design Utilities - + 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000 false - + @@ -81,13 +81,13 @@ /br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd - processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd) + process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd) 0 0 - 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f80000000100000003000000000000000100000003 true - processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd) + process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd) @@ -107,13 +107,13 @@ 1 - Simulate Behavioral Model + 0 0 000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000 false - Simulate Behavioral Model + @@ -130,5 +130,5 @@ 000000ff0000000000000002000001a6000000db01000000040100000002 - Behavioral Simulation + Implementation diff --git a/xilinx/ALU/iseconfig/processeur.xreport b/xilinx/ALU/iseconfig/processeur.xreport index a144ac5..0981d4a 100644 --- a/xilinx/ALU/iseconfig/processeur.xreport +++ b/xilinx/ALU/iseconfig/processeur.xreport @@ -1,11 +1,11 @@
- 2021-05-10T10:47:06 + 2021-05-18T16:14:30 processeur Unknown /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport - /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU + /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/ 2021-05-10T09:34:56 false
diff --git a/xilinx/ALU/isim.log b/xilinx/ALU/isim.log index ac9885d..69c11ff 100644 --- a/xilinx/ALU/isim.log +++ b/xilinx/ALU/isim.log @@ -45,4 +45,74 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 # exit 0 diff --git a/xilinx/ALU/isim/isim_usage_statistics.html b/xilinx/ALU/isim/isim_usage_statistics.html index 8db4a1e..be08e85 100644 --- a/xilinx/ALU/isim/isim_usage_statistics.html +++ b/xilinx/ALU/isim/isim_usage_statistics.html @@ -2,14 +2,14 @@ ISim Statistics Xilinx HDL Libraries Used=ieee -Fuse Resource Usage=850 ms, 1723208 KB +Fuse Resource Usage=980 ms, 1723384 KB -Total Signals=109 -Total Nets=10695 +Total Signals=121 +Total Nets=10703 Total Blocks=14 -Total Processes=31 +Total Processes=36 Total Simulation Time=1 us -Simulation Resource Usage=0.04 sec, 264146 KB +Simulation Resource Usage=0.03 sec, 264171 KB Simulation Mode=gui Hardware CoSim=0 diff --git a/xilinx/ALU/isim/lockfile1 b/xilinx/ALU/isim/lockfile1 new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat index 286651d..c8d812b 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat index b00d7b6..d65ad9e 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat index 56ad3f8..1da5dba 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat differ diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat index 8385230..f3ae6ed 100644 Binary files a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat and b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg index c4844f4..536614a 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg new file mode 100644 index 0000000..91cda93 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log index 43b3bf6..86c6e6a 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log @@ -2,28 +2,28 @@ Command line: process_test_isim_beh.exe -simmode gui -simrunnum 0 - -socket 43981 + -socket 37953 -Mon May 10 12:31:07 2021 +Tue May 18 16:16:44 2021 Elaboration Time: 0.01 sec - Current Memory Usage: 189.698 Meg + Current Memory Usage: 189.723 Meg - Total Signals : 109 - Total Nets : 10695 - Total Signal Drivers : 44 + Total Signals : 121 + Total Nets : 10703 + Total Signal Drivers : 49 Total Blocks : 14 Total Primitive Blocks : 12 - Total Processes : 31 + Total Processes : 36 Total Traceable Variables : 16 - Total Scalar Nets and Variables : 11197 -Total Line Count : 66 + Total Scalar Nets and Variables : 11205 +Total Line Count : 92 - Total Simulation Time: 0.04 sec + Total Simulation Time: 0.03 sec - Current Memory Usage: 265.2 Meg + Current Memory Usage: 265.224 Meg -Mon May 10 12:32:41 2021 +Tue May 18 16:20:51 2021 diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat index b6daf1e..2d79219 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat new file mode 100644 index 0000000..f395b69 Binary files /dev/null and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe index b761c0b..e7c0761 100755 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 index d89b164..6b6e6b4 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1 differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat index 9380503..4eb95f1 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat index dab3502..762b5df 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1229531095_2372691052.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat index d0b248f..af53ca4 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1466808984_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c index a5b42f6..0600382 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c @@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0) char *t14; char *t15; -LAB0: xsi_set_current_line(45, ng0); +LAB0: xsi_set_current_line(67, ng0); LAB3: t1 = (t0 + 1512U); t2 = *((char **)t1); diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat index 8b36ff9..0e870ab 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o index 921e541..9f0b3a3 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c index 4990355..e98aa6a 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c @@ -34,67 +34,74 @@ static void work_a_3650175700_3212880686_p_0(char *t0) char *t3; unsigned char t4; char *t5; - char *t6; + unsigned char t6; char *t7; char *t8; + char *t9; + char *t10; -LAB0: t1 = (t0 + 3464U); +LAB0: t1 = (t0 + 3624U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; -LAB2: xsi_set_current_line(49, ng0); +LAB2: xsi_set_current_line(50, ng0); -LAB6: t2 = (t0 + 3784); +LAB6: t2 = (t0 + 3944); *((int *)t2) = 1; *((char **)t1) = &&LAB7; LAB1: return; -LAB4: t5 = (t0 + 3784); +LAB4: t5 = (t0 + 3944); *((int *)t5) = 0; - xsi_set_current_line(50, ng0); - t2 = (t0 + 1032U); - t3 = *((char **)t2); - t2 = (t0 + 3864); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); - t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); xsi_set_current_line(51, ng0); - t2 = (t0 + 1192U); + t2 = (t0 + 1832U); t3 = *((char **)t2); - t2 = (t0 + 3928); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)3); + if (t6 != 0) + goto LAB8; + +LAB10: xsi_set_current_line(57, ng0); + t2 = (t0 + 6674); + t5 = (t0 + 4024); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - xsi_set_current_line(52, ng0); - t2 = (t0 + 1352U); - t3 = *((char **)t2); - t2 = (t0 + 3992); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(58, ng0); + t2 = (t0 + 6682); + t5 = (t0 + 4088); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - xsi_set_current_line(53, ng0); - t2 = (t0 + 1512U); - t3 = *((char **)t2); - t2 = (t0 + 4056); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(59, ng0); + t2 = (t0 + 6690); + t5 = (t0 + 4152); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - goto LAB2; + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(60, ng0); + t2 = (t0 + 6698); + t5 = (t0 + 4216); + t7 = (t5 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + +LAB9: goto LAB2; LAB5: t3 = (t0 + 1632U); t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); @@ -105,6 +112,48 @@ LAB5: t3 = (t0 + 1632U); LAB7: goto LAB5; +LAB8: xsi_set_current_line(52, ng0); + t2 = (t0 + 1032U); + t5 = *((char **)t2); + t2 = (t0 + 4024); + t7 = (t2 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t5, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(53, ng0); + t2 = (t0 + 1192U); + t3 = *((char **)t2); + t2 = (t0 + 4088); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(54, ng0); + t2 = (t0 + 1352U); + t3 = *((char **)t2); + t2 = (t0 + 4152); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(55, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t2 = (t0 + 4216); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + goto LAB9; + } diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat index 767be67..7f21f68 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o index 5d6c345..7ce73b3 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat index 01c7692..a7f58df 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c index d7ee46a..09c37d9 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c @@ -99,11 +99,11 @@ static void work_a_4150868852_3212880686_p_0(char *t0) char *t73; char *t74; -LAB0: xsi_set_current_line(166, ng0); +LAB0: xsi_set_current_line(175, ng0); t7 = (t0 + 4872U); t8 = *((char **)t7); - t7 = (t0 + 17848U); - t9 = (t0 + 18267); + t7 = (t0 + 22008U); + t9 = (t0 + 22435); t12 = (t11 + 0U); t13 = (t12 + 0U); *((int *)t13) = 0; @@ -122,8 +122,8 @@ LAB0: xsi_set_current_line(166, ng0); LAB21: t13 = (t0 + 4872U); t17 = *((char **)t13); - t13 = (t0 + 17848U); - t18 = (t0 + 18275); + t13 = (t0 + 22008U); + t18 = (t0 + 22443); t21 = (t20 + 0U); t22 = (t21 + 0U); *((int *)t22) = 0; @@ -144,8 +144,8 @@ LAB22: if (t6 == 1) LAB18: t22 = (t0 + 4872U); t25 = *((char **)t22); - t22 = (t0 + 17848U); - t26 = (t0 + 18283); + t22 = (t0 + 22008U); + t26 = (t0 + 22451); t29 = (t28 + 0U); t30 = (t29 + 0U); *((int *)t30) = 0; @@ -166,8 +166,8 @@ LAB19: if (t5 == 1) LAB15: t30 = (t0 + 4872U); t33 = *((char **)t30); - t30 = (t0 + 17848U); - t34 = (t0 + 18291); + t30 = (t0 + 22008U); + t34 = (t0 + 22459); t37 = (t36 + 0U); t38 = (t37 + 0U); *((int *)t38) = 0; @@ -188,8 +188,8 @@ LAB16: if (t4 == 1) LAB12: t38 = (t0 + 4872U); t41 = *((char **)t38); - t38 = (t0 + 17848U); - t42 = (t0 + 18299); + t38 = (t0 + 22008U); + t42 = (t0 + 22467); t45 = (t44 + 0U); t46 = (t45 + 0U); *((int *)t46) = 0; @@ -210,8 +210,8 @@ LAB13: if (t3 == 1) LAB9: t46 = (t0 + 4872U); t49 = *((char **)t46); - t46 = (t0 + 17848U); - t50 = (t0 + 18307); + t46 = (t0 + 22008U); + t50 = (t0 + 22475); t53 = (t52 + 0U); t54 = (t53 + 0U); *((int *)t54) = 0; @@ -232,8 +232,8 @@ LAB10: if (t2 == 1) LAB6: t54 = (t0 + 4872U); t57 = *((char **)t54); - t54 = (t0 + 17848U); - t58 = (t0 + 18315); + t54 = (t0 + 22008U); + t58 = (t0 + 22483); t61 = (t60 + 0U); t62 = (t61 + 0U); *((int *)t62) = 0; @@ -253,7 +253,7 @@ LAB7: if (t1 != 0) goto LAB3; LAB4: -LAB23: t69 = (t0 + 10296); +LAB23: t69 = (t0 + 12896); t70 = (t69 + 56U); t71 = *((char **)t70); t72 = (t71 + 56U); @@ -261,11 +261,11 @@ LAB23: t69 = (t0 + 10296); *((unsigned char *)t73) = (unsigned char)2; xsi_driver_first_trans_fast(t69); -LAB2: t74 = (t0 + 10088); +LAB2: t74 = (t0 + 12608); *((int *)t74) = 1; LAB1: return; -LAB3: t62 = (t0 + 10296); +LAB3: t62 = (t0 + 12896); t65 = (t62 + 56U); t66 = *((char **)t65); t67 = (t66 + 56U); @@ -298,193 +298,343 @@ LAB24: goto LAB2; static void work_a_4150868852_3212880686_p_1(char *t0) { - char t9[16]; - char t18[16]; - char t26[16]; - char t34[16]; - char t42[16]; + char t11[16]; + char t17[16]; + char t25[16]; + char t31[16]; + char t39[16]; + char t45[16]; + char t53[16]; + char t59[16]; + char t67[16]; + char t73[16]; + char t81[16]; + char t87[16]; unsigned char t1; unsigned char t2; unsigned char t3; unsigned char t4; - char *t5; + unsigned char t5; char *t6; char *t7; - char *t10; - char *t11; - int t12; - unsigned int t13; - unsigned char t14; - char *t15; - char *t16; + unsigned int t8; + unsigned int t9; + unsigned int t10; + char *t12; + char *t13; + int t14; + unsigned int t15; + char *t18; char *t19; - char *t20; - int t21; - unsigned char t22; - char *t23; - char *t24; + int t20; + unsigned char t21; + char *t22; + unsigned int t23; + unsigned int t24; + char *t26; char *t27; - char *t28; - int t29; - unsigned char t30; - char *t31; + int t28; + unsigned int t29; char *t32; - char *t35; + char *t33; + int t34; + unsigned char t35; char *t36; - int t37; - unsigned char t38; - char *t39; + unsigned int t37; + unsigned int t38; char *t40; - char *t43; - char *t44; - int t45; - unsigned char t46; + char *t41; + int t42; + unsigned int t43; + char *t46; char *t47; - char *t48; - char *t49; + int t48; + unsigned char t49; char *t50; - char *t51; - char *t52; - char *t53; + unsigned int t51; + unsigned int t52; char *t54; char *t55; - char *t56; - char *t57; - char *t58; + int t56; + unsigned int t57; + char *t60; + char *t61; + int t62; + unsigned char t63; + char *t64; + unsigned int t65; + unsigned int t66; + char *t68; + char *t69; + int t70; + unsigned int t71; + char *t74; + char *t75; + int t76; + unsigned char t77; + char *t78; + unsigned int t79; + unsigned int t80; + char *t82; + char *t83; + int t84; + unsigned int t85; + char *t88; + char *t89; + int t90; + unsigned char t91; + char *t92; + char *t93; + char *t94; + char *t95; + char *t96; + char *t97; + char *t98; + char *t99; + char *t100; + char *t101; -LAB0: xsi_set_current_line(181, ng0); - t5 = (t0 + 2152U); - t6 = *((char **)t5); - t5 = (t0 + 17640U); - t7 = (t0 + 18323); - t10 = (t9 + 0U); - t11 = (t10 + 0U); - *((int *)t11) = 0; - t11 = (t10 + 4U); - *((int *)t11) = 7; - t11 = (t10 + 8U); - *((int *)t11) = 1; - t12 = (7 - 0); - t13 = (t12 * 1); - t13 = (t13 + 1); - t11 = (t10 + 12U); - *((unsigned int *)t11) = t13; - t14 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t5, t7, t9); - if (t14 == 1) +LAB0: xsi_set_current_line(179, ng0); + t6 = (t0 + 1992U); + t7 = *((char **)t6); + t8 = (31 - 31); + t9 = (t8 * 1U); + t10 = (0 + t9); + t6 = (t7 + t10); + t12 = (t11 + 0U); + t13 = (t12 + 0U); + *((int *)t13) = 31; + t13 = (t12 + 4U); + *((int *)t13) = 24; + t13 = (t12 + 8U); + *((int *)t13) = -1; + t14 = (24 - 31); + t15 = (t14 * -1); + t15 = (t15 + 1); + t13 = (t12 + 12U); + *((unsigned int *)t13) = t15; + t13 = (t0 + 22491); + t18 = (t17 + 0U); + t19 = (t18 + 0U); + *((int *)t19) = 0; + t19 = (t18 + 4U); + *((int *)t19) = 7; + t19 = (t18 + 8U); + *((int *)t19) = 1; + t20 = (7 - 0); + t15 = (t20 * 1); + t15 = (t15 + 1); + t19 = (t18 + 12U); + *((unsigned int *)t19) = t15; + t21 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t11, t13, t17); + if (t21 == 1) + goto LAB17; + +LAB18: t19 = (t0 + 1992U); + t22 = *((char **)t19); + t15 = (31 - 31); + t23 = (t15 * 1U); + t24 = (0 + t23); + t19 = (t22 + t24); + t26 = (t25 + 0U); + t27 = (t26 + 0U); + *((int *)t27) = 31; + t27 = (t26 + 4U); + *((int *)t27) = 24; + t27 = (t26 + 8U); + *((int *)t27) = -1; + t28 = (24 - 31); + t29 = (t28 * -1); + t29 = (t29 + 1); + t27 = (t26 + 12U); + *((unsigned int *)t27) = t29; + t27 = (t0 + 22499); + t32 = (t31 + 0U); + t33 = (t32 + 0U); + *((int *)t33) = 0; + t33 = (t32 + 4U); + *((int *)t33) = 7; + t33 = (t32 + 8U); + *((int *)t33) = 1; + t34 = (7 - 0); + t29 = (t34 * 1); + t29 = (t29 + 1); + t33 = (t32 + 12U); + *((unsigned int *)t33) = t29; + t35 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t19, t25, t27, t31); + t5 = t35; + +LAB19: if (t5 == 1) goto LAB14; -LAB15: t11 = (t0 + 2152U); - t15 = *((char **)t11); - t11 = (t0 + 17640U); - t16 = (t0 + 18331); - t19 = (t18 + 0U); - t20 = (t19 + 0U); - *((int *)t20) = 0; - t20 = (t19 + 4U); - *((int *)t20) = 7; - t20 = (t19 + 8U); - *((int *)t20) = 1; - t21 = (7 - 0); - t13 = (t21 * 1); - t13 = (t13 + 1); - t20 = (t19 + 12U); - *((unsigned int *)t20) = t13; - t22 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t15, t11, t16, t18); - t4 = t22; +LAB15: t33 = (t0 + 1992U); + t36 = *((char **)t33); + t29 = (31 - 31); + t37 = (t29 * 1U); + t38 = (0 + t37); + t33 = (t36 + t38); + t40 = (t39 + 0U); + t41 = (t40 + 0U); + *((int *)t41) = 31; + t41 = (t40 + 4U); + *((int *)t41) = 24; + t41 = (t40 + 8U); + *((int *)t41) = -1; + t42 = (24 - 31); + t43 = (t42 * -1); + t43 = (t43 + 1); + t41 = (t40 + 12U); + *((unsigned int *)t41) = t43; + t41 = (t0 + 22507); + t46 = (t45 + 0U); + t47 = (t46 + 0U); + *((int *)t47) = 0; + t47 = (t46 + 4U); + *((int *)t47) = 7; + t47 = (t46 + 8U); + *((int *)t47) = 1; + t48 = (7 - 0); + t43 = (t48 * 1); + t43 = (t43 + 1); + t47 = (t46 + 12U); + *((unsigned int *)t47) = t43; + t49 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t33, t39, t41, t45); + t4 = t49; LAB16: if (t4 == 1) goto LAB11; -LAB12: t20 = (t0 + 2152U); - t23 = *((char **)t20); - t20 = (t0 + 17640U); - t24 = (t0 + 18339); - t27 = (t26 + 0U); - t28 = (t27 + 0U); - *((int *)t28) = 0; - t28 = (t27 + 4U); - *((int *)t28) = 7; - t28 = (t27 + 8U); - *((int *)t28) = 1; - t29 = (7 - 0); - t13 = (t29 * 1); - t13 = (t13 + 1); - t28 = (t27 + 12U); - *((unsigned int *)t28) = t13; - t30 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t23, t20, t24, t26); - t3 = t30; +LAB12: t47 = (t0 + 1992U); + t50 = *((char **)t47); + t43 = (31 - 31); + t51 = (t43 * 1U); + t52 = (0 + t51); + t47 = (t50 + t52); + t54 = (t53 + 0U); + t55 = (t54 + 0U); + *((int *)t55) = 31; + t55 = (t54 + 4U); + *((int *)t55) = 24; + t55 = (t54 + 8U); + *((int *)t55) = -1; + t56 = (24 - 31); + t57 = (t56 * -1); + t57 = (t57 + 1); + t55 = (t54 + 12U); + *((unsigned int *)t55) = t57; + t55 = (t0 + 22515); + t60 = (t59 + 0U); + t61 = (t60 + 0U); + *((int *)t61) = 0; + t61 = (t60 + 4U); + *((int *)t61) = 7; + t61 = (t60 + 8U); + *((int *)t61) = 1; + t62 = (7 - 0); + t57 = (t62 * 1); + t57 = (t57 + 1); + t61 = (t60 + 12U); + *((unsigned int *)t61) = t57; + t63 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t47, t53, t55, t59); + t3 = t63; LAB13: if (t3 == 1) goto LAB8; -LAB9: t28 = (t0 + 2152U); - t31 = *((char **)t28); - t28 = (t0 + 17640U); - t32 = (t0 + 18347); - t35 = (t34 + 0U); - t36 = (t35 + 0U); - *((int *)t36) = 0; - t36 = (t35 + 4U); - *((int *)t36) = 7; - t36 = (t35 + 8U); - *((int *)t36) = 1; - t37 = (7 - 0); - t13 = (t37 * 1); - t13 = (t13 + 1); - t36 = (t35 + 12U); - *((unsigned int *)t36) = t13; - t38 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t28, t32, t34); - t2 = t38; +LAB9: t61 = (t0 + 1992U); + t64 = *((char **)t61); + t57 = (31 - 31); + t65 = (t57 * 1U); + t66 = (0 + t65); + t61 = (t64 + t66); + t68 = (t67 + 0U); + t69 = (t68 + 0U); + *((int *)t69) = 31; + t69 = (t68 + 4U); + *((int *)t69) = 24; + t69 = (t68 + 8U); + *((int *)t69) = -1; + t70 = (24 - 31); + t71 = (t70 * -1); + t71 = (t71 + 1); + t69 = (t68 + 12U); + *((unsigned int *)t69) = t71; + t69 = (t0 + 22523); + t74 = (t73 + 0U); + t75 = (t74 + 0U); + *((int *)t75) = 0; + t75 = (t74 + 4U); + *((int *)t75) = 7; + t75 = (t74 + 8U); + *((int *)t75) = 1; + t76 = (7 - 0); + t71 = (t76 * 1); + t71 = (t71 + 1); + t75 = (t74 + 12U); + *((unsigned int *)t75) = t71; + t77 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t61, t67, t69, t73); + t2 = t77; LAB10: if (t2 == 1) goto LAB5; -LAB6: t36 = (t0 + 2152U); - t39 = *((char **)t36); - t36 = (t0 + 17640U); - t40 = (t0 + 18355); - t43 = (t42 + 0U); - t44 = (t43 + 0U); - *((int *)t44) = 0; - t44 = (t43 + 4U); - *((int *)t44) = 7; - t44 = (t43 + 8U); - *((int *)t44) = 1; - t45 = (7 - 0); - t13 = (t45 * 1); - t13 = (t13 + 1); - t44 = (t43 + 12U); - *((unsigned int *)t44) = t13; - t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t39, t36, t40, t42); - t1 = t46; +LAB6: t75 = (t0 + 1992U); + t78 = *((char **)t75); + t71 = (31 - 31); + t79 = (t71 * 1U); + t80 = (0 + t79); + t75 = (t78 + t80); + t82 = (t81 + 0U); + t83 = (t82 + 0U); + *((int *)t83) = 31; + t83 = (t82 + 4U); + *((int *)t83) = 24; + t83 = (t82 + 8U); + *((int *)t83) = -1; + t84 = (24 - 31); + t85 = (t84 * -1); + t85 = (t85 + 1); + t83 = (t82 + 12U); + *((unsigned int *)t83) = t85; + t83 = (t0 + 22531); + t88 = (t87 + 0U); + t89 = (t88 + 0U); + *((int *)t89) = 0; + t89 = (t88 + 4U); + *((int *)t89) = 7; + t89 = (t88 + 8U); + *((int *)t89) = 1; + t90 = (7 - 0); + t85 = (t90 * 1); + t85 = (t85 + 1); + t89 = (t88 + 12U); + *((unsigned int *)t89) = t85; + t91 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t75, t81, t83, t87); + t1 = t91; LAB7: if (t1 != 0) goto LAB3; LAB4: -LAB17: t52 = (t0 + 2472U); - t53 = *((char **)t52); - t52 = (t0 + 10360); - t54 = (t52 + 56U); - t55 = *((char **)t54); - t56 = (t55 + 56U); - t57 = *((char **)t56); - memcpy(t57, t53, 8U); - xsi_driver_first_trans_fast(t52); +LAB20: t96 = (t0 + 12960); + t97 = (t96 + 56U); + t98 = *((char **)t97); + t99 = (t98 + 56U); + t100 = *((char **)t99); + *((unsigned char *)t100) = (unsigned char)2; + xsi_driver_first_trans_fast(t96); -LAB2: t58 = (t0 + 10104); - *((int *)t58) = 1; +LAB2: t101 = (t0 + 12624); + *((int *)t101) = 1; LAB1: return; -LAB3: t44 = (t0 + 1512U); - t47 = *((char **)t44); - t44 = (t0 + 10360); - t48 = (t44 + 56U); - t49 = *((char **)t48); - t50 = (t49 + 56U); - t51 = *((char **)t50); - memcpy(t51, t47, 8U); - xsi_driver_first_trans_fast(t44); +LAB3: t89 = (t0 + 12960); + t92 = (t89 + 56U); + t93 = *((char **)t92); + t94 = (t93 + 56U); + t95 = *((char **)t94); + *((unsigned char *)t95) = (unsigned char)3; + xsi_driver_first_trans_fast(t89); goto LAB2; LAB5: t1 = (unsigned char)1; @@ -499,11 +649,506 @@ LAB11: t3 = (unsigned char)1; LAB14: t4 = (unsigned char)1; goto LAB16; -LAB18: goto LAB2; +LAB17: t5 = (unsigned char)1; + goto LAB19; + +LAB21: goto LAB2; } static void work_a_4150868852_3212880686_p_2(char *t0) +{ + char t9[16]; + char t15[16]; + char t23[16]; + char t29[16]; + char t37[16]; + char t43[16]; + char t51[16]; + char t57[16]; + unsigned char t1; + unsigned char t2; + unsigned char t3; + char *t4; + char *t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + char *t10; + char *t11; + int t12; + unsigned int t13; + char *t16; + char *t17; + int t18; + unsigned char t19; + char *t20; + unsigned int t21; + unsigned int t22; + char *t24; + char *t25; + int t26; + unsigned int t27; + char *t30; + char *t31; + int t32; + unsigned char t33; + char *t34; + unsigned int t35; + unsigned int t36; + char *t38; + char *t39; + int t40; + unsigned int t41; + char *t44; + char *t45; + int t46; + unsigned char t47; + char *t48; + unsigned int t49; + unsigned int t50; + char *t52; + char *t53; + int t54; + unsigned int t55; + char *t58; + char *t59; + int t60; + unsigned char t61; + char *t62; + char *t63; + char *t64; + char *t65; + char *t66; + char *t67; + char *t68; + char *t69; + char *t70; + char *t71; + +LAB0: xsi_set_current_line(181, ng0); + t4 = (t0 + 1992U); + t5 = *((char **)t4); + t6 = (31 - 31); + t7 = (t6 * 1U); + t8 = (0 + t7); + t4 = (t5 + t8); + t10 = (t9 + 0U); + t11 = (t10 + 0U); + *((int *)t11) = 31; + t11 = (t10 + 4U); + *((int *)t11) = 24; + t11 = (t10 + 8U); + *((int *)t11) = -1; + t12 = (24 - 31); + t13 = (t12 * -1); + t13 = (t13 + 1); + t11 = (t10 + 12U); + *((unsigned int *)t11) = t13; + t11 = (t0 + 22539); + t16 = (t15 + 0U); + t17 = (t16 + 0U); + *((int *)t17) = 0; + t17 = (t16 + 4U); + *((int *)t17) = 7; + t17 = (t16 + 8U); + *((int *)t17) = 1; + t18 = (7 - 0); + t13 = (t18 * 1); + t13 = (t13 + 1); + t17 = (t16 + 12U); + *((unsigned int *)t17) = t13; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t4, t9, t11, t15); + if (t19 == 1) + goto LAB11; + +LAB12: t17 = (t0 + 1992U); + t20 = *((char **)t17); + t13 = (31 - 31); + t21 = (t13 * 1U); + t22 = (0 + t21); + t17 = (t20 + t22); + t24 = (t23 + 0U); + t25 = (t24 + 0U); + *((int *)t25) = 31; + t25 = (t24 + 4U); + *((int *)t25) = 24; + t25 = (t24 + 8U); + *((int *)t25) = -1; + t26 = (24 - 31); + t27 = (t26 * -1); + t27 = (t27 + 1); + t25 = (t24 + 12U); + *((unsigned int *)t25) = t27; + t25 = (t0 + 22547); + t30 = (t29 + 0U); + t31 = (t30 + 0U); + *((int *)t31) = 0; + t31 = (t30 + 4U); + *((int *)t31) = 7; + t31 = (t30 + 8U); + *((int *)t31) = 1; + t32 = (7 - 0); + t27 = (t32 * 1); + t27 = (t27 + 1); + t31 = (t30 + 12U); + *((unsigned int *)t31) = t27; + t33 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t17, t23, t25, t29); + t3 = t33; + +LAB13: if (t3 == 1) + goto LAB8; + +LAB9: t31 = (t0 + 1992U); + t34 = *((char **)t31); + t27 = (31 - 31); + t35 = (t27 * 1U); + t36 = (0 + t35); + t31 = (t34 + t36); + t38 = (t37 + 0U); + t39 = (t38 + 0U); + *((int *)t39) = 31; + t39 = (t38 + 4U); + *((int *)t39) = 24; + t39 = (t38 + 8U); + *((int *)t39) = -1; + t40 = (24 - 31); + t41 = (t40 * -1); + t41 = (t41 + 1); + t39 = (t38 + 12U); + *((unsigned int *)t39) = t41; + t39 = (t0 + 22555); + t44 = (t43 + 0U); + t45 = (t44 + 0U); + *((int *)t45) = 0; + t45 = (t44 + 4U); + *((int *)t45) = 7; + t45 = (t44 + 8U); + *((int *)t45) = 1; + t46 = (7 - 0); + t41 = (t46 * 1); + t41 = (t41 + 1); + t45 = (t44 + 12U); + *((unsigned int *)t45) = t41; + t47 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t31, t37, t39, t43); + t2 = t47; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t45 = (t0 + 1992U); + t48 = *((char **)t45); + t41 = (31 - 31); + t49 = (t41 * 1U); + t50 = (0 + t49); + t45 = (t48 + t50); + t52 = (t51 + 0U); + t53 = (t52 + 0U); + *((int *)t53) = 31; + t53 = (t52 + 4U); + *((int *)t53) = 24; + t53 = (t52 + 8U); + *((int *)t53) = -1; + t54 = (24 - 31); + t55 = (t54 * -1); + t55 = (t55 + 1); + t53 = (t52 + 12U); + *((unsigned int *)t53) = t55; + t53 = (t0 + 22563); + t58 = (t57 + 0U); + t59 = (t58 + 0U); + *((int *)t59) = 0; + t59 = (t58 + 4U); + *((int *)t59) = 7; + t59 = (t58 + 8U); + *((int *)t59) = 1; + t60 = (7 - 0); + t55 = (t60 * 1); + t55 = (t55 + 1); + t59 = (t58 + 12U); + *((unsigned int *)t59) = t55; + t61 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t45, t51, t53, t57); + t1 = t61; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB14: t66 = (t0 + 13024); + t67 = (t66 + 56U); + t68 = *((char **)t67); + t69 = (t68 + 56U); + t70 = *((char **)t69); + *((unsigned char *)t70) = (unsigned char)2; + xsi_driver_first_trans_fast(t66); + +LAB2: t71 = (t0 + 12640); + *((int *)t71) = 1; + +LAB1: return; +LAB3: t59 = (t0 + 13024); + t62 = (t59 + 56U); + t63 = *((char **)t62); + t64 = (t63 + 56U); + t65 = *((char **)t64); + *((unsigned char *)t65) = (unsigned char)3; + xsi_driver_first_trans_fast(t59); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB11: t3 = (unsigned char)1; + goto LAB13; + +LAB15: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_3(char *t0) +{ + char t10[16]; + char t19[16]; + char t27[16]; + char t35[16]; + char t43[16]; + char t51[16]; + unsigned char t1; + unsigned char t2; + unsigned char t3; + unsigned char t4; + unsigned char t5; + char *t6; + char *t7; + char *t8; + char *t11; + char *t12; + int t13; + unsigned int t14; + unsigned char t15; + char *t16; + char *t17; + char *t20; + char *t21; + int t22; + unsigned char t23; + char *t24; + char *t25; + char *t28; + char *t29; + int t30; + unsigned char t31; + char *t32; + char *t33; + char *t36; + char *t37; + int t38; + unsigned char t39; + char *t40; + char *t41; + char *t44; + char *t45; + int t46; + unsigned char t47; + char *t48; + char *t49; + char *t52; + char *t53; + int t54; + unsigned char t55; + char *t56; + char *t57; + char *t58; + char *t59; + char *t60; + char *t61; + char *t62; + char *t63; + char *t64; + char *t65; + char *t66; + char *t67; + +LAB0: xsi_set_current_line(196, ng0); + t6 = (t0 + 2152U); + t7 = *((char **)t6); + t6 = (t0 + 21800U); + t8 = (t0 + 22571); + t11 = (t10 + 0U); + t12 = (t11 + 0U); + *((int *)t12) = 0; + t12 = (t11 + 4U); + *((int *)t12) = 7; + t12 = (t11 + 8U); + *((int *)t12) = 1; + t13 = (7 - 0); + t14 = (t13 * 1); + t14 = (t14 + 1); + t12 = (t11 + 12U); + *((unsigned int *)t12) = t14; + t15 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t7, t6, t8, t10); + if (t15 == 1) + goto LAB17; + +LAB18: t12 = (t0 + 2152U); + t16 = *((char **)t12); + t12 = (t0 + 21800U); + t17 = (t0 + 22579); + t20 = (t19 + 0U); + t21 = (t20 + 0U); + *((int *)t21) = 0; + t21 = (t20 + 4U); + *((int *)t21) = 7; + t21 = (t20 + 8U); + *((int *)t21) = 1; + t22 = (7 - 0); + t14 = (t22 * 1); + t14 = (t14 + 1); + t21 = (t20 + 12U); + *((unsigned int *)t21) = t14; + t23 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t16, t12, t17, t19); + t5 = t23; + +LAB19: if (t5 == 1) + goto LAB14; + +LAB15: t21 = (t0 + 2152U); + t24 = *((char **)t21); + t21 = (t0 + 21800U); + t25 = (t0 + 22587); + t28 = (t27 + 0U); + t29 = (t28 + 0U); + *((int *)t29) = 0; + t29 = (t28 + 4U); + *((int *)t29) = 7; + t29 = (t28 + 8U); + *((int *)t29) = 1; + t30 = (7 - 0); + t14 = (t30 * 1); + t14 = (t14 + 1); + t29 = (t28 + 12U); + *((unsigned int *)t29) = t14; + t31 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t24, t21, t25, t27); + t4 = t31; + +LAB16: if (t4 == 1) + goto LAB11; + +LAB12: t29 = (t0 + 2152U); + t32 = *((char **)t29); + t29 = (t0 + 21800U); + t33 = (t0 + 22595); + t36 = (t35 + 0U); + t37 = (t36 + 0U); + *((int *)t37) = 0; + t37 = (t36 + 4U); + *((int *)t37) = 7; + t37 = (t36 + 8U); + *((int *)t37) = 1; + t38 = (7 - 0); + t14 = (t38 * 1); + t14 = (t14 + 1); + t37 = (t36 + 12U); + *((unsigned int *)t37) = t14; + t39 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t32, t29, t33, t35); + t3 = t39; + +LAB13: if (t3 == 1) + goto LAB8; + +LAB9: t37 = (t0 + 2152U); + t40 = *((char **)t37); + t37 = (t0 + 21800U); + t41 = (t0 + 22603); + t44 = (t43 + 0U); + t45 = (t44 + 0U); + *((int *)t45) = 0; + t45 = (t44 + 4U); + *((int *)t45) = 7; + t45 = (t44 + 8U); + *((int *)t45) = 1; + t46 = (7 - 0); + t14 = (t46 * 1); + t14 = (t14 + 1); + t45 = (t44 + 12U); + *((unsigned int *)t45) = t14; + t47 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t40, t37, t41, t43); + t2 = t47; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t45 = (t0 + 2152U); + t48 = *((char **)t45); + t45 = (t0 + 21800U); + t49 = (t0 + 22611); + t52 = (t51 + 0U); + t53 = (t52 + 0U); + *((int *)t53) = 0; + t53 = (t52 + 4U); + *((int *)t53) = 7; + t53 = (t52 + 8U); + *((int *)t53) = 1; + t54 = (7 - 0); + t14 = (t54 * 1); + t14 = (t14 + 1); + t53 = (t52 + 12U); + *((unsigned int *)t53) = t14; + t55 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t48, t45, t49, t51); + t1 = t55; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB20: t61 = (t0 + 2472U); + t62 = *((char **)t61); + t61 = (t0 + 13088); + t63 = (t61 + 56U); + t64 = *((char **)t63); + t65 = (t64 + 56U); + t66 = *((char **)t65); + memcpy(t66, t62, 8U); + xsi_driver_first_trans_fast(t61); + +LAB2: t67 = (t0 + 12656); + *((int *)t67) = 1; + +LAB1: return; +LAB3: t53 = (t0 + 1512U); + t56 = *((char **)t53); + t53 = (t0 + 13088); + t57 = (t53 + 56U); + t58 = *((char **)t57); + t59 = (t58 + 56U); + t60 = *((char **)t59); + memcpy(t60, t56, 8U); + xsi_driver_first_trans_fast(t53); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB11: t3 = (unsigned char)1; + goto LAB13; + +LAB14: t4 = (unsigned char)1; + goto LAB16; + +LAB17: t5 = (unsigned char)1; + goto LAB19; + +LAB21: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_4(char *t0) { char t5[16]; char t21[16]; @@ -553,11 +1198,11 @@ static void work_a_4150868852_3212880686_p_2(char *t0) char *t53; char *t54; -LAB0: xsi_set_current_line(197, ng0); +LAB0: xsi_set_current_line(213, ng0); t1 = (t0 + 2792U); t2 = *((char **)t1); - t1 = (t0 + 17704U); - t3 = (t0 + 18363); + t1 = (t0 + 21864U); + t3 = (t0 + 22619); t6 = (t5 + 0U); t7 = (t6 + 0U); *((int *)t7) = 0; @@ -576,8 +1221,8 @@ LAB0: xsi_set_current_line(197, ng0); LAB4: t17 = (t0 + 2792U); t18 = *((char **)t17); - t17 = (t0 + 17704U); - t19 = (t0 + 18374); + t17 = (t0 + 21864U); + t19 = (t0 + 22630); t22 = (t21 + 0U); t23 = (t22 + 0U); *((int *)t23) = 0; @@ -596,8 +1241,8 @@ LAB4: t17 = (t0 + 2792U); LAB6: t32 = (t0 + 2792U); t33 = *((char **)t32); - t32 = (t0 + 17704U); - t34 = (t0 + 18385); + t32 = (t0 + 21864U); + t34 = (t0 + 22641); t37 = (t36 + 0U); t38 = (t37 + 0U); *((int *)t38) = 0; @@ -615,8 +1260,8 @@ LAB6: t32 = (t0 + 2792U); goto LAB7; LAB8: -LAB9: t47 = (t0 + 18396); - t49 = (t0 + 10424); +LAB9: t47 = (t0 + 22652); + t49 = (t0 + 13152); t50 = (t49 + 56U); t51 = *((char **)t50); t52 = (t51 + 56U); @@ -624,12 +1269,12 @@ LAB9: t47 = (t0 + 18396); memcpy(t53, t47, 3U); xsi_driver_first_trans_fast(t49); -LAB2: t54 = (t0 + 10120); +LAB2: t54 = (t0 + 12672); *((int *)t54) = 1; LAB1: return; -LAB3: t7 = (t0 + 18371); - t12 = (t0 + 10424); +LAB3: t7 = (t0 + 22627); + t12 = (t0 + 13152); t13 = (t12 + 56U); t14 = *((char **)t13); t15 = (t14 + 56U); @@ -638,8 +1283,8 @@ LAB3: t7 = (t0 + 18371); xsi_driver_first_trans_fast(t12); goto LAB2; -LAB5: t23 = (t0 + 18382); - t27 = (t0 + 10424); +LAB5: t23 = (t0 + 22638); + t27 = (t0 + 13152); t28 = (t27 + 56U); t29 = *((char **)t28); t30 = (t29 + 56U); @@ -648,8 +1293,8 @@ LAB5: t23 = (t0 + 18382); xsi_driver_first_trans_fast(t27); goto LAB2; -LAB7: t38 = (t0 + 18393); - t42 = (t0 + 10424); +LAB7: t38 = (t0 + 22649); + t42 = (t0 + 13152); t43 = (t42 + 56U); t44 = *((char **)t43); t45 = (t44 + 56U); @@ -662,7 +1307,109 @@ LAB10: goto LAB2; } -static void work_a_4150868852_3212880686_p_3(char *t0) +static void work_a_4150868852_3212880686_p_5(char *t0) +{ + char t6[16]; + char t15[16]; + unsigned char t1; + char *t2; + char *t3; + char *t4; + char *t7; + char *t8; + int t9; + unsigned int t10; + unsigned char t11; + char *t12; + char *t13; + char *t16; + char *t17; + int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + +LAB0: xsi_set_current_line(218, ng0); + t2 = (t0 + 2152U); + t3 = *((char **)t2); + t2 = (t0 + 21800U); + t4 = (t0 + 22655); + t7 = (t6 + 0U); + t8 = (t7 + 0U); + *((int *)t8) = 0; + t8 = (t7 + 4U); + *((int *)t8) = 7; + t8 = (t7 + 8U); + *((int *)t8) = 1; + t9 = (7 - 0); + t10 = (t9 * 1); + t10 = (t10 + 1); + t8 = (t7 + 12U); + *((unsigned int *)t8) = t10; + t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6); + if (t11 == 1) + goto LAB5; + +LAB6: t8 = (t0 + 2152U); + t12 = *((char **)t8); + t8 = (t0 + 21800U); + t13 = (t0 + 22663); + t16 = (t15 + 0U); + t17 = (t16 + 0U); + *((int *)t17) = 0; + t17 = (t16 + 4U); + *((int *)t17) = 7; + t17 = (t16 + 8U); + *((int *)t17) = 1; + t18 = (7 - 0); + t10 = (t18 * 1); + t10 = (t10 + 1); + t17 = (t16 + 12U); + *((unsigned int *)t17) = t10; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15); + t1 = t19; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 13216); + t25 = (t24 + 56U); + t26 = *((char **)t25); + t27 = (t26 + 56U); + t28 = *((char **)t27); + *((unsigned char *)t28) = (unsigned char)3; + xsi_driver_first_trans_fast(t24); + +LAB2: t29 = (t0 + 12688); + *((int *)t29) = 1; + +LAB1: return; +LAB3: t17 = (t0 + 13216); + t20 = (t17 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + *((unsigned char *)t23) = (unsigned char)2; + xsi_driver_first_trans_fast(t17); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_6(char *t0) { char t7[16]; char t16[16]; @@ -702,11 +1449,11 @@ static void work_a_4150868852_3212880686_p_3(char *t0) char *t39; char *t40; -LAB0: xsi_set_current_line(214, ng0); +LAB0: xsi_set_current_line(232, ng0); t3 = (t0 + 2792U); t4 = *((char **)t3); - t3 = (t0 + 17704U); - t5 = (t0 + 18399); + t3 = (t0 + 21864U); + t5 = (t0 + 22671); t8 = (t7 + 0U); t9 = (t8 + 0U); *((int *)t9) = 0; @@ -725,8 +1472,8 @@ LAB0: xsi_set_current_line(214, ng0); LAB9: t9 = (t0 + 2792U); t13 = *((char **)t9); - t9 = (t0 + 17704U); - t14 = (t0 + 18407); + t9 = (t0 + 21864U); + t14 = (t0 + 22679); t17 = (t16 + 0U); t18 = (t17 + 0U); *((int *)t18) = 0; @@ -747,8 +1494,8 @@ LAB10: if (t2 == 1) LAB6: t18 = (t0 + 2792U); t21 = *((char **)t18); - t18 = (t0 + 17704U); - t22 = (t0 + 18415); + t18 = (t0 + 21864U); + t22 = (t0 + 22687); t25 = (t24 + 0U); t26 = (t25 + 0U); *((int *)t26) = 0; @@ -770,7 +1517,7 @@ LAB7: if (t1 != 0) LAB4: LAB11: t34 = (t0 + 3112U); t35 = *((char **)t34); - t34 = (t0 + 10488); + t34 = (t0 + 13280); t36 = (t34 + 56U); t37 = *((char **)t36); t38 = (t37 + 56U); @@ -778,13 +1525,13 @@ LAB11: t34 = (t0 + 3112U); memcpy(t39, t35, 8U); xsi_driver_first_trans_fast(t34); -LAB2: t40 = (t0 + 10136); +LAB2: t40 = (t0 + 12704); *((int *)t40) = 1; LAB1: return; LAB3: t26 = (t0 + 6152U); t29 = *((char **)t26); - t26 = (t0 + 10488); + t26 = (t0 + 13280); t30 = (t26 + 56U); t31 = *((char **)t30); t32 = (t31 + 56U); @@ -803,207 +1550,6 @@ LAB12: goto LAB2; } -static void work_a_4150868852_3212880686_p_4(char *t0) -{ - char t5[16]; - char *t1; - char *t2; - char *t3; - char *t6; - char *t7; - int t8; - unsigned int t9; - unsigned char t10; - char *t11; - char *t12; - char *t13; - char *t14; - char *t15; - char *t16; - char *t17; - char *t18; - char *t19; - char *t20; - -LAB0: xsi_set_current_line(231, ng0); - t1 = (t0 + 4392U); - t2 = *((char **)t1); - t1 = (t0 + 17800U); - t3 = (t0 + 18423); - t6 = (t5 + 0U); - t7 = (t6 + 0U); - *((int *)t7) = 0; - t7 = (t6 + 4U); - *((int *)t7) = 7; - t7 = (t6 + 8U); - *((int *)t7) = 1; - t8 = (7 - 0); - t9 = (t8 * 1); - t9 = (t9 + 1); - t7 = (t6 + 12U); - *((unsigned int *)t7) = t9; - t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); - if (t10 != 0) - goto LAB3; - -LAB4: -LAB5: t15 = (t0 + 10552); - t16 = (t15 + 56U); - t17 = *((char **)t16); - t18 = (t17 + 56U); - t19 = *((char **)t18); - *((unsigned char *)t19) = (unsigned char)3; - xsi_driver_first_trans_fast(t15); - -LAB2: t20 = (t0 + 10152); - *((int *)t20) = 1; - -LAB1: return; -LAB3: t7 = (t0 + 10552); - t11 = (t7 + 56U); - t12 = *((char **)t11); - t13 = (t12 + 56U); - t14 = *((char **)t13); - *((unsigned char *)t14) = (unsigned char)2; - xsi_driver_first_trans_fast(t7); - goto LAB2; - -LAB6: goto LAB2; - -} - -static void work_a_4150868852_3212880686_p_5(char *t0) -{ - char t5[16]; - char *t1; - char *t2; - char *t3; - char *t6; - char *t7; - int t8; - unsigned int t9; - unsigned char t10; - char *t11; - char *t12; - char *t13; - char *t14; - char *t15; - char *t16; - char *t17; - char *t18; - char *t19; - char *t20; - char *t21; - char *t22; - -LAB0: xsi_set_current_line(233, ng0); - t1 = (t0 + 4392U); - t2 = *((char **)t1); - t1 = (t0 + 17800U); - t3 = (t0 + 18431); - t6 = (t5 + 0U); - t7 = (t6 + 0U); - *((int *)t7) = 0; - t7 = (t6 + 4U); - *((int *)t7) = 7; - t7 = (t6 + 8U); - *((int *)t7) = 1; - t8 = (7 - 0); - t9 = (t8 * 1); - t9 = (t9 + 1); - t7 = (t6 + 12U); - *((unsigned int *)t7) = t9; - t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); - if (t10 != 0) - goto LAB3; - -LAB4: -LAB5: t16 = (t0 + 4072U); - t17 = *((char **)t16); - t16 = (t0 + 10616); - t18 = (t16 + 56U); - t19 = *((char **)t18); - t20 = (t19 + 56U); - t21 = *((char **)t20); - memcpy(t21, t17, 8U); - xsi_driver_first_trans_fast(t16); - -LAB2: t22 = (t0 + 10168); - *((int *)t22) = 1; - -LAB1: return; -LAB3: t7 = (t0 + 4232U); - t11 = *((char **)t7); - t7 = (t0 + 10616); - t12 = (t7 + 56U); - t13 = *((char **)t12); - t14 = (t13 + 56U); - t15 = *((char **)t14); - memcpy(t15, t11, 8U); - xsi_driver_first_trans_fast(t7); - goto LAB2; - -LAB6: goto LAB2; - -} - -static void work_a_4150868852_3212880686_p_6(char *t0) -{ - char t5[16]; - char *t1; - char *t2; - char *t3; - char *t6; - char *t7; - int t8; - unsigned int t9; - unsigned char t10; - char *t11; - char *t12; - char *t13; - char *t14; - char *t15; - char *t16; - -LAB0: xsi_set_current_line(235, ng0); - t1 = (t0 + 4392U); - t2 = *((char **)t1); - t1 = (t0 + 17800U); - t3 = (t0 + 18439); - t6 = (t5 + 0U); - t7 = (t6 + 0U); - *((int *)t7) = 0; - t7 = (t6 + 4U); - *((int *)t7) = 7; - t7 = (t6 + 8U); - *((int *)t7) = 1; - t8 = (7 - 0); - t9 = (t8 * 1); - t9 = (t9 + 1); - t7 = (t6 + 12U); - *((unsigned int *)t7) = t9; - t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); - if (t10 != 0) - goto LAB3; - -LAB4: -LAB2: t16 = (t0 + 10184); - *((int *)t16) = 1; - -LAB1: return; -LAB3: t7 = (t0 + 4232U); - t11 = *((char **)t7); - t7 = (t0 + 10680); - t12 = (t7 + 56U); - t13 = *((char **)t12); - t14 = (t13 + 56U); - t15 = *((char **)t14); - memcpy(t15, t11, 8U); - xsi_driver_first_trans_fast(t7); - goto LAB2; - -} - static void work_a_4150868852_3212880686_p_7(char *t0) { char t5[16]; @@ -1025,14 +1571,12 @@ static void work_a_4150868852_3212880686_p_7(char *t0) char *t18; char *t19; char *t20; - char *t21; - char *t22; -LAB0: xsi_set_current_line(236, ng0); +LAB0: xsi_set_current_line(250, ng0); t1 = (t0 + 4392U); t2 = *((char **)t1); - t1 = (t0 + 17800U); - t3 = (t0 + 18447); + t1 = (t0 + 21960U); + t3 = (t0 + 22695); t6 = (t5 + 0U); t7 = (t6 + 0U); *((int *)t7) = 0; @@ -1050,9 +1594,80 @@ LAB0: xsi_set_current_line(236, ng0); goto LAB3; LAB4: -LAB5: t16 = (t0 + 4232U); +LAB5: t15 = (t0 + 13344); + t16 = (t15 + 56U); t17 = *((char **)t16); - t16 = (t0 + 10744); + t18 = (t17 + 56U); + t19 = *((char **)t18); + *((unsigned char *)t19) = (unsigned char)3; + xsi_driver_first_trans_fast(t15); + +LAB2: t20 = (t0 + 12720); + *((int *)t20) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 13344); + t11 = (t7 + 56U); + t12 = *((char **)t11); + t13 = (t12 + 56U); + t14 = *((char **)t13); + *((unsigned char *)t14) = (unsigned char)2; + xsi_driver_first_trans_fast(t7); + goto LAB2; + +LAB6: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_8(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + char *t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + +LAB0: xsi_set_current_line(252, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 21960U); + t3 = (t0 + 22703); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB5: t16 = (t0 + 4072U); + t17 = *((char **)t16); + t16 = (t0 + 13408); t18 = (t16 + 56U); t19 = *((char **)t18); t20 = (t19 + 56U); @@ -1060,13 +1675,13 @@ LAB5: t16 = (t0 + 4232U); memcpy(t21, t17, 8U); xsi_driver_first_trans_fast(t16); -LAB2: t22 = (t0 + 10200); +LAB2: t22 = (t0 + 12736); *((int *)t22) = 1; LAB1: return; -LAB3: t7 = (t0 + 5672U); +LAB3: t7 = (t0 + 4232U); t11 = *((char **)t7); - t7 = (t0 + 10744); + t7 = (t0 + 13408); t12 = (t7 + 56U); t13 = *((char **)t12); t14 = (t13 + 56U); @@ -1079,7 +1694,606 @@ LAB6: goto LAB2; } -static void work_a_4150868852_3212880686_p_8(char *t0) +static void work_a_4150868852_3212880686_p_9(char *t0) +{ + char t5[16]; + char *t1; + char *t2; + char *t3; + char *t6; + char *t7; + int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(254, ng0); + t1 = (t0 + 4392U); + t2 = *((char **)t1); + t1 = (t0 + 21960U); + t3 = (t0 + 22711); + t6 = (t5 + 0U); + t7 = (t6 + 0U); + *((int *)t7) = 0; + t7 = (t6 + 4U); + *((int *)t7) = 7; + t7 = (t6 + 8U); + *((int *)t7) = 1; + t8 = (7 - 0); + t9 = (t8 * 1); + t9 = (t9 + 1); + t7 = (t6 + 12U); + *((unsigned int *)t7) = t9; + t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5); + if (t10 != 0) + goto LAB3; + +LAB4: +LAB2: t16 = (t0 + 12752); + *((int *)t16) = 1; + +LAB1: return; +LAB3: t7 = (t0 + 4232U); + t11 = *((char **)t7); + t7 = (t0 + 13472); + t12 = (t7 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t11, 8U); + xsi_driver_first_trans_fast(t7); + goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_10(char *t0) +{ + char t6[16]; + char t15[16]; + unsigned char t1; + char *t2; + char *t3; + char *t4; + char *t7; + char *t8; + int t9; + unsigned int t10; + unsigned char t11; + char *t12; + char *t13; + char *t16; + char *t17; + int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + char *t30; + char *t31; + +LAB0: xsi_set_current_line(255, ng0); + t2 = (t0 + 4392U); + t3 = *((char **)t2); + t2 = (t0 + 21960U); + t4 = (t0 + 22719); + t7 = (t6 + 0U); + t8 = (t7 + 0U); + *((int *)t8) = 0; + t8 = (t7 + 4U); + *((int *)t8) = 7; + t8 = (t7 + 8U); + *((int *)t8) = 1; + t9 = (7 - 0); + t10 = (t9 * 1); + t10 = (t10 + 1); + t8 = (t7 + 12U); + *((unsigned int *)t8) = t10; + t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6); + if (t11 == 1) + goto LAB5; + +LAB6: t8 = (t0 + 4392U); + t12 = *((char **)t8); + t8 = (t0 + 21960U); + t13 = (t0 + 22727); + t16 = (t15 + 0U); + t17 = (t16 + 0U); + *((int *)t17) = 0; + t17 = (t16 + 4U); + *((int *)t17) = 7; + t17 = (t16 + 8U); + *((int *)t17) = 1; + t18 = (7 - 0); + t10 = (t18 * 1); + t10 = (t10 + 1); + t17 = (t16 + 12U); + *((unsigned int *)t17) = t10; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15); + t1 = t19; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t25 = (t0 + 4232U); + t26 = *((char **)t25); + t25 = (t0 + 13536); + t27 = (t25 + 56U); + t28 = *((char **)t27); + t29 = (t28 + 56U); + t30 = *((char **)t29); + memcpy(t30, t26, 8U); + xsi_driver_first_trans_fast(t25); + +LAB2: t31 = (t0 + 12768); + *((int *)t31) = 1; + +LAB1: return; +LAB3: t17 = (t0 + 5672U); + t20 = *((char **)t17); + t17 = (t0 + 13536); + t21 = (t17 + 56U); + t22 = *((char **)t21); + t23 = (t22 + 56U); + t24 = *((char **)t23); + memcpy(t24, t20, 8U); + xsi_driver_first_trans_fast(t17); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_11(char *t0) +{ + char t6[16]; + char t15[16]; + unsigned char t1; + char *t2; + char *t3; + char *t4; + char *t7; + char *t8; + int t9; + unsigned int t10; + unsigned char t11; + char *t12; + char *t13; + char *t16; + char *t17; + int t18; + unsigned char t19; + char *t20; + char *t21; + char *t22; + char *t23; + char *t24; + char *t25; + char *t26; + char *t27; + char *t28; + char *t29; + +LAB0: xsi_set_current_line(259, ng0); + t2 = (t0 + 2792U); + t3 = *((char **)t2); + t2 = (t0 + 21864U); + t4 = (t0 + 22735); + t7 = (t6 + 0U); + t8 = (t7 + 0U); + *((int *)t8) = 0; + t8 = (t7 + 4U); + *((int *)t8) = 7; + t8 = (t7 + 8U); + *((int *)t8) = 1; + t9 = (7 - 0); + t10 = (t9 * 1); + t10 = (t10 + 1); + t8 = (t7 + 12U); + *((unsigned int *)t8) = t10; + t11 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t3, t2, t4, t6); + if (t11 == 1) + goto LAB5; + +LAB6: t8 = (t0 + 2792U); + t12 = *((char **)t8); + t8 = (t0 + 21864U); + t13 = (t0 + 22743); + t16 = (t15 + 0U); + t17 = (t16 + 0U); + *((int *)t17) = 0; + t17 = (t16 + 4U); + *((int *)t17) = 7; + t17 = (t16 + 8U); + *((int *)t17) = 1; + t18 = (7 - 0); + t10 = (t18 * 1); + t10 = (t10 + 1); + t17 = (t16 + 12U); + *((unsigned int *)t17) = t10; + t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t12, t8, t13, t15); + t1 = t19; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB8: t24 = (t0 + 13600); + t25 = (t24 + 56U); + t26 = *((char **)t25); + t27 = (t26 + 56U); + t28 = *((char **)t27); + *((unsigned char *)t28) = (unsigned char)3; + xsi_driver_first_trans_fast(t24); + +LAB2: t29 = (t0 + 12784); + *((int *)t29) = 1; + +LAB1: return; +LAB3: t17 = (t0 + 13600); + t20 = (t17 + 56U); + t21 = *((char **)t20); + t22 = (t21 + 56U); + t23 = *((char **)t22); + *((unsigned char *)t23) = (unsigned char)2; + xsi_driver_first_trans_fast(t17); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB9: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_12(char *t0) +{ + char t17[16]; + char t36[16]; + char t55[16]; + char t74[16]; + unsigned char t1; + unsigned char t2; + unsigned char t3; + unsigned char t4; + unsigned char t5; + char *t6; + char *t7; + unsigned char t8; + unsigned char t9; + char *t10; + unsigned char t11; + unsigned char t12; + char *t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + char *t18; + char *t19; + int t20; + unsigned int t21; + char *t22; + unsigned char t23; + unsigned char t24; + unsigned char t25; + char *t26; + char *t27; + unsigned char t28; + unsigned char t29; + char *t30; + unsigned char t31; + unsigned char t32; + char *t33; + unsigned int t34; + unsigned int t35; + char *t37; + char *t38; + int t39; + unsigned int t40; + char *t41; + unsigned char t42; + unsigned char t43; + unsigned char t44; + char *t45; + char *t46; + unsigned char t47; + unsigned char t48; + char *t49; + unsigned char t50; + unsigned char t51; + char *t52; + unsigned int t53; + unsigned int t54; + char *t56; + char *t57; + int t58; + unsigned int t59; + char *t60; + unsigned char t61; + unsigned char t62; + unsigned char t63; + char *t64; + char *t65; + unsigned char t66; + unsigned char t67; + char *t68; + unsigned char t69; + unsigned char t70; + char *t71; + unsigned int t72; + unsigned int t73; + char *t75; + char *t76; + int t77; + unsigned int t78; + char *t79; + unsigned char t80; + char *t81; + char *t82; + char *t83; + char *t84; + char *t85; + char *t86; + char *t87; + char *t88; + char *t89; + char *t90; + char *t91; + +LAB0: xsi_set_current_line(285, ng0); + t6 = (t0 + 6472U); + t7 = *((char **)t6); + t8 = *((unsigned char *)t7); + t9 = (t8 == (unsigned char)3); + if (t9 == 1) + goto LAB17; + +LAB18: t5 = (unsigned char)0; + +LAB19: if (t5 == 1) + goto LAB14; + +LAB15: t4 = (unsigned char)0; + +LAB16: if (t4 == 1) + goto LAB11; + +LAB12: t26 = (t0 + 6632U); + t27 = *((char **)t26); + t28 = *((unsigned char *)t27); + t29 = (t28 == (unsigned char)3); + if (t29 == 1) + goto LAB23; + +LAB24: t25 = (unsigned char)0; + +LAB25: if (t25 == 1) + goto LAB20; + +LAB21: t24 = (unsigned char)0; + +LAB22: t3 = t24; + +LAB13: if (t3 == 1) + goto LAB8; + +LAB9: t45 = (t0 + 6472U); + t46 = *((char **)t45); + t47 = *((unsigned char *)t46); + t48 = (t47 == (unsigned char)3); + if (t48 == 1) + goto LAB29; + +LAB30: t44 = (unsigned char)0; + +LAB31: if (t44 == 1) + goto LAB26; + +LAB27: t43 = (unsigned char)0; + +LAB28: t2 = t43; + +LAB10: if (t2 == 1) + goto LAB5; + +LAB6: t64 = (t0 + 6632U); + t65 = *((char **)t64); + t66 = *((unsigned char *)t65); + t67 = (t66 == (unsigned char)3); + if (t67 == 1) + goto LAB35; + +LAB36: t63 = (unsigned char)0; + +LAB37: if (t63 == 1) + goto LAB32; + +LAB33: t62 = (unsigned char)0; + +LAB34: t1 = t62; + +LAB7: if (t1 != 0) + goto LAB3; + +LAB4: +LAB38: t86 = (t0 + 13664); + t87 = (t86 + 56U); + t88 = *((char **)t87); + t89 = (t88 + 56U); + t90 = *((char **)t89); + *((unsigned char *)t90) = (unsigned char)3; + xsi_driver_first_trans_fast(t86); + +LAB2: t91 = (t0 + 12800); + *((int *)t91) = 1; + +LAB1: return; +LAB3: t81 = (t0 + 13664); + t82 = (t81 + 56U); + t83 = *((char **)t82); + t84 = (t83 + 56U); + t85 = *((char **)t84); + *((unsigned char *)t85) = (unsigned char)2; + xsi_driver_first_trans_fast(t81); + goto LAB2; + +LAB5: t1 = (unsigned char)1; + goto LAB7; + +LAB8: t2 = (unsigned char)1; + goto LAB10; + +LAB11: t3 = (unsigned char)1; + goto LAB13; + +LAB14: t6 = (t0 + 1992U); + t13 = *((char **)t6); + t14 = (31 - 15); + t15 = (t14 * 1U); + t16 = (0 + t15); + t6 = (t13 + t16); + t18 = (t17 + 0U); + t19 = (t18 + 0U); + *((int *)t19) = 15; + t19 = (t18 + 4U); + *((int *)t19) = 8; + t19 = (t18 + 8U); + *((int *)t19) = -1; + t20 = (8 - 15); + t21 = (t20 * -1); + t21 = (t21 + 1); + t19 = (t18 + 12U); + *((unsigned int *)t19) = t21; + t19 = (t0 + 2312U); + t22 = *((char **)t19); + t19 = (t0 + 21816U); + t23 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t6, t17, t22, t19); + t4 = t23; + goto LAB16; + +LAB17: t6 = (t0 + 6792U); + t10 = *((char **)t6); + t11 = *((unsigned char *)t10); + t12 = (t11 == (unsigned char)3); + t5 = t12; + goto LAB19; + +LAB20: t26 = (t0 + 1992U); + t33 = *((char **)t26); + t21 = (31 - 7); + t34 = (t21 * 1U); + t35 = (0 + t34); + t26 = (t33 + t35); + t37 = (t36 + 0U); + t38 = (t37 + 0U); + *((int *)t38) = 7; + t38 = (t37 + 4U); + *((int *)t38) = 0; + t38 = (t37 + 8U); + *((int *)t38) = -1; + t39 = (0 - 7); + t40 = (t39 * -1); + t40 = (t40 + 1); + t38 = (t37 + 12U); + *((unsigned int *)t38) = t40; + t38 = (t0 + 2312U); + t41 = *((char **)t38); + t38 = (t0 + 21816U); + t42 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t26, t36, t41, t38); + t24 = t42; + goto LAB22; + +LAB23: t26 = (t0 + 6792U); + t30 = *((char **)t26); + t31 = *((unsigned char *)t30); + t32 = (t31 == (unsigned char)3); + t25 = t32; + goto LAB25; + +LAB26: t45 = (t0 + 1992U); + t52 = *((char **)t45); + t40 = (31 - 15); + t53 = (t40 * 1U); + t54 = (0 + t53); + t45 = (t52 + t54); + t56 = (t55 + 0U); + t57 = (t56 + 0U); + *((int *)t57) = 15; + t57 = (t56 + 4U); + *((int *)t57) = 8; + t57 = (t56 + 8U); + *((int *)t57) = -1; + t58 = (8 - 15); + t59 = (t58 * -1); + t59 = (t59 + 1); + t57 = (t56 + 12U); + *((unsigned int *)t57) = t59; + t57 = (t0 + 2952U); + t60 = *((char **)t57); + t57 = (t0 + 21880U); + t61 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t45, t55, t60, t57); + t43 = t61; + goto LAB28; + +LAB29: t45 = (t0 + 6952U); + t49 = *((char **)t45); + t50 = *((unsigned char *)t49); + t51 = (t50 == (unsigned char)3); + t44 = t51; + goto LAB31; + +LAB32: t64 = (t0 + 1992U); + t71 = *((char **)t64); + t59 = (31 - 7); + t72 = (t59 * 1U); + t73 = (0 + t72); + t64 = (t71 + t73); + t75 = (t74 + 0U); + t76 = (t75 + 0U); + *((int *)t76) = 7; + t76 = (t75 + 4U); + *((int *)t76) = 0; + t76 = (t75 + 8U); + *((int *)t76) = -1; + t77 = (0 - 7); + t78 = (t77 * -1); + t78 = (t78 + 1); + t76 = (t75 + 12U); + *((unsigned int *)t76) = t78; + t76 = (t0 + 2952U); + t79 = *((char **)t76); + t76 = (t0 + 21880U); + t80 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t64, t74, t79, t76); + t62 = t80; + goto LAB34; + +LAB35: t64 = (t0 + 6952U); + t68 = *((char **)t64); + t69 = *((unsigned char *)t68); + t70 = (t69 == (unsigned char)3); + t63 = t70; + goto LAB37; + +LAB39: goto LAB2; + +} + +static void work_a_4150868852_3212880686_p_13(char *t0) { char t12[16]; char t13[16]; @@ -1097,28 +2311,30 @@ static void work_a_4150868852_3212880686_p_8(char *t0) int t14; unsigned int t15; unsigned int t16; - char *t17; + unsigned char t17; char *t18; char *t19; char *t20; + char *t21; + char *t22; -LAB0: t1 = (t0 + 9768U); +LAB0: t1 = (t0 + 12288U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; -LAB2: xsi_set_current_line(262, ng0); +LAB2: xsi_set_current_line(293, ng0); -LAB6: t2 = (t0 + 10216); +LAB6: t2 = (t0 + 12816); *((int *)t2) = 1; *((char **)t1) = &&LAB7; LAB1: return; -LAB4: t5 = (t0 + 10216); +LAB4: t5 = (t0 + 12816); *((int *)t5) = 0; - xsi_set_current_line(263, ng0); + xsi_set_current_line(294, ng0); t2 = (t0 + 1192U); t3 = *((char **)t2); t4 = *((unsigned char *)t3); @@ -1126,39 +2342,16 @@ LAB4: t5 = (t0 + 10216); if (t6 != 0) goto LAB8; -LAB10: xsi_set_current_line(266, ng0); - t2 = (t0 + 1352U); +LAB10: xsi_set_current_line(297, ng0); + t2 = (t0 + 7112U); t3 = *((char **)t2); - t2 = (t0 + 17560U); - t5 = (t0 + 18463); - t8 = (t13 + 0U); - t9 = (t8 + 0U); - *((int *)t9) = 0; - t9 = (t8 + 4U); - *((int *)t9) = 7; - t9 = (t8 + 8U); - *((int *)t9) = 1; - t14 = (7 - 0); - t15 = (t14 * 1); - t15 = (t15 + 1); - t9 = (t8 + 12U); - *((unsigned int *)t9) = t15; - t9 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t12, t3, t2, t5, t13); - t10 = (t12 + 12U); - t15 = *((unsigned int *)t10); - t16 = (1U * t15); - t4 = (8U != t16); - if (t4 == 1) + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)3); + if (t6 != 0) goto LAB11; -LAB12: t11 = (t0 + 10808); - t17 = (t11 + 56U); - t18 = *((char **)t17); - t19 = (t18 + 56U); - t20 = *((char **)t19); - memcpy(t20, t9, 8U); - xsi_driver_first_trans_fast(t11); - +LAB13: +LAB12: LAB9: goto LAB2; LAB5: t3 = (t0 + 992U); @@ -1170,9 +2363,9 @@ LAB5: t3 = (t0 + 992U); LAB7: goto LAB5; -LAB8: xsi_set_current_line(264, ng0); - t2 = (t0 + 18455); - t7 = (t0 + 10808); +LAB8: xsi_set_current_line(295, ng0); + t2 = (t0 + 22751); + t7 = (t0 + 13728); t8 = (t7 + 56U); t9 = *((char **)t8); t10 = (t9 + 56U); @@ -1181,15 +2374,49 @@ LAB8: xsi_set_current_line(264, ng0); xsi_driver_first_trans_fast(t7); goto LAB9; -LAB11: xsi_size_not_matching(8U, t16, 0); +LAB11: xsi_set_current_line(298, ng0); + t2 = (t0 + 1352U); + t5 = *((char **)t2); + t2 = (t0 + 21720U); + t7 = (t0 + 22759); + t9 = (t13 + 0U); + t10 = (t9 + 0U); + *((int *)t10) = 0; + t10 = (t9 + 4U); + *((int *)t10) = 7; + t10 = (t9 + 8U); + *((int *)t10) = 1; + t14 = (7 - 0); + t15 = (t14 * 1); + t15 = (t15 + 1); + t10 = (t9 + 12U); + *((unsigned int *)t10) = t15; + t10 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t12, t5, t2, t7, t13); + t11 = (t12 + 12U); + t15 = *((unsigned int *)t11); + t16 = (1U * t15); + t17 = (8U != t16); + if (t17 == 1) + goto LAB14; + +LAB15: t18 = (t0 + 13728); + t19 = (t18 + 56U); + t20 = *((char **)t19); + t21 = (t20 + 56U); + t22 = *((char **)t21); + memcpy(t22, t10, 8U); + xsi_driver_first_trans_fast(t18); goto LAB12; +LAB14: xsi_size_not_matching(8U, t16, 0); + goto LAB15; + } extern void work_a_4150868852_3212880686_init() { - static char *pe[] = {(void *)work_a_4150868852_3212880686_p_0,(void *)work_a_4150868852_3212880686_p_1,(void *)work_a_4150868852_3212880686_p_2,(void *)work_a_4150868852_3212880686_p_3,(void *)work_a_4150868852_3212880686_p_4,(void *)work_a_4150868852_3212880686_p_5,(void *)work_a_4150868852_3212880686_p_6,(void *)work_a_4150868852_3212880686_p_7,(void *)work_a_4150868852_3212880686_p_8}; + static char *pe[] = {(void *)work_a_4150868852_3212880686_p_0,(void *)work_a_4150868852_3212880686_p_1,(void *)work_a_4150868852_3212880686_p_2,(void *)work_a_4150868852_3212880686_p_3,(void *)work_a_4150868852_3212880686_p_4,(void *)work_a_4150868852_3212880686_p_5,(void *)work_a_4150868852_3212880686_p_6,(void *)work_a_4150868852_3212880686_p_7,(void *)work_a_4150868852_3212880686_p_8,(void *)work_a_4150868852_3212880686_p_9,(void *)work_a_4150868852_3212880686_p_10,(void *)work_a_4150868852_3212880686_p_11,(void *)work_a_4150868852_3212880686_p_12,(void *)work_a_4150868852_3212880686_p_13}; xsi_register_didat("work_a_4150868852_3212880686", "isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat"); xsi_register_executes(pe); } diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat index e84fb20..9f3b29b 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.didat differ diff --git a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o index ef6a22d..133b7fc 100644 Binary files a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o and b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o differ diff --git a/xilinx/ALU/isim/work/alu.vdb b/xilinx/ALU/isim/work/alu.vdb index 3d69e0f..7fd0bbf 100644 Binary files a/xilinx/ALU/isim/work/alu.vdb and b/xilinx/ALU/isim/work/alu.vdb differ diff --git a/xilinx/ALU/isim/work/bm_data.vdb b/xilinx/ALU/isim/work/bm_data.vdb index c50550a..a700e50 100644 Binary files a/xilinx/ALU/isim/work/bm_data.vdb and b/xilinx/ALU/isim/work/bm_data.vdb differ diff --git a/xilinx/ALU/isim/work/bm_instr.vdb b/xilinx/ALU/isim/work/bm_instr.vdb index a590406..4e2ada0 100644 Binary files a/xilinx/ALU/isim/work/bm_instr.vdb and b/xilinx/ALU/isim/work/bm_instr.vdb differ diff --git a/xilinx/ALU/isim/work/br.vdb b/xilinx/ALU/isim/work/br.vdb index cb363ad..93049cb 100644 Binary files a/xilinx/ALU/isim/work/br.vdb and b/xilinx/ALU/isim/work/br.vdb differ diff --git a/xilinx/ALU/isim/work/pipeline.vdb b/xilinx/ALU/isim/work/pipeline.vdb index 14165e2..e941c5e 100644 Binary files a/xilinx/ALU/isim/work/pipeline.vdb and b/xilinx/ALU/isim/work/pipeline.vdb differ diff --git a/xilinx/ALU/isim/work/process_test.vdb b/xilinx/ALU/isim/work/process_test.vdb index 7e7008d..2c456ec 100644 Binary files a/xilinx/ALU/isim/work/process_test.vdb and b/xilinx/ALU/isim/work/process_test.vdb differ diff --git a/xilinx/ALU/isim/work/processeur.vdb b/xilinx/ALU/isim/work/processeur.vdb index 37a8687..35fcc84 100644 Binary files a/xilinx/ALU/isim/work/processeur.vdb and b/xilinx/ALU/isim/work/processeur.vdb differ diff --git a/xilinx/ALU/pipeline.vhd b/xilinx/ALU/pipeline.vhd index 7159219..44f2934 100644 --- a/xilinx/ALU/pipeline.vhd +++ b/xilinx/ALU/pipeline.vhd @@ -35,6 +35,7 @@ entity pipeline is B_IN : in STD_LOGIC_VECTOR (7 downto 0); C_IN : in STD_LOGIC_VECTOR (7 downto 0); CLK : in STD_LOGIC; + EN : in STD_LOGIC; OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); A_OUT : out STD_LOGIC_VECTOR (7 downto 0); B_OUT : out STD_LOGIC_VECTOR (7 downto 0); @@ -47,10 +48,17 @@ begin process begin wait until rising_edge(CLK); - OP_OUT <= OP_IN; - A_OUT <= A_IN; - B_OUT <= B_IN; - C_OUT <= C_IN; - end process; + if (EN = '1') then + OP_OUT <= OP_IN; + A_OUT <= A_IN; + B_OUT <= B_IN; + C_OUT <= C_IN; + else + OP_OUT <= "00000000"; + A_OUT <= "00000000"; + B_OUT <= "00000000"; + C_OUT <= "00000000"; + end if; + end process; end Behavioral; diff --git a/xilinx/ALU/process_test_isim_beh.wdb b/xilinx/ALU/process_test_isim_beh.wdb index 6c339fb..9119173 100644 Binary files a/xilinx/ALU/process_test_isim_beh.wdb and b/xilinx/ALU/process_test_isim_beh.wdb differ diff --git a/xilinx/ALU/process_test_isim_beh1.wdb b/xilinx/ALU/process_test_isim_beh1.wdb new file mode 100644 index 0000000..d98a43d Binary files /dev/null and b/xilinx/ALU/process_test_isim_beh1.wdb differ diff --git a/xilinx/ALU/processeur.bld b/xilinx/ALU/processeur.bld new file mode 100644 index 0000000..b942f95 --- /dev/null +++ b/xilinx/ALU/processeur.bld @@ -0,0 +1,42 @@ +Release 13.4 ngdbuild O.87xd (lin64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. + +Command Line: +/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild +-intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc +processeur.ngd + +Reading NGO file +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc" +... +Loading design module +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc".. +. +WARNING:NgdBuild:578 - Design contains no instances. +Gathering constraint information from source properties... +Done. + +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 1 + +Total memory usage is 398744 kilobytes + +Writing NGD file "processeur.ngd" ... +Total REAL time to NGDBUILD completion: 1 sec +Total CPU time to NGDBUILD completion: 1 sec + +Writing NGDBUILD log file "processeur.bld"... diff --git a/xilinx/ALU/processeur.cmd_log b/xilinx/ALU/processeur.cmd_log new file mode 100644 index 0000000..3bfc27e --- /dev/null +++ b/xilinx/ALU/processeur.cmd_log @@ -0,0 +1,3 @@ +xst -intstyle ise -ifn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.xst" -ofn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc processeur.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf diff --git a/xilinx/ALU/processeur.lso b/xilinx/ALU/processeur.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/xilinx/ALU/processeur.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/ALU/processeur.ngc b/xilinx/ALU/processeur.ngc new file mode 100644 index 0000000..c06ba6d --- /dev/null +++ b/xilinx/ALU/processeur.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$3cx5>443JF@86MCK148GIM609<0OAE=7178GIM5P11H@F3JEFADZ[EE58GWCF\LN=7AALKDF4?II@AJKG46A!86zg[I2TT\8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI;5\OTP@A3=T\H^^_95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;XGPe>vugjoxh{}109{g3ukp8<&? m|g207yEFwi2JKt?65F;095~U6<38=6<951265700=:;22.9?7<=;|Q27?4128=1=>:9344967>?82n947>51;3xW42=:?0:;7?<47162?450>l0zY?k:182>4<7sZ;?6?8516827104=?09>59i;%02>40<,821>45m2983>7<729qC>=5+1g81<>"6k3:0(753-Xnzd}foo8#5+420).?o6!golg,bjst{h~x#O{}e`w,twimm}Uxu~zjm.rqkocsWzsxxhcj/ykomk~(IE_$|alerqfqw(ioj;0>h59smz22fu`;;>&?<>4BTKO@ZRFZNO_M_MG3:AOO1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK826?FJLI8=0OAEN1E04?FJLI8N?;6MCK@3G<0=DDBH:96MCKB36?FJLL8?0OAEKVb9@HNBQWMC]EIK:;BNHB]>BUKVY^ONK\SGWO<>C_XHDOII?>;DZSEKBBLVHHHRHFLD37?@^WIGNNHRM@NRVQELHS[8;0IU^NNEGG[LUBWOCGI55IIMGMEHCc3OCGICOBE^PLKQcI)0>roSA:4P@PW2>VTLFDN?6\\T038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA3=T\H^^_95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kgb>^c`VZye`Xjrrklj4674??oqe?84>;o15>3=#;:08>6s\19803?4?289?:>;9:30;<5=T:;0857?51265700=:;2h<6]>8;1:>4<6;=<89;4=29a1?a5f290:6;9:30;3c=#=39i7E?n;wV2f?6=93;1>v]>9;14>7>=9:>=?88523:4b>"4938?7[=;:3yv60<63|8=6=5r$3;90>"6m3:0(52;296~N482.9j7=n;%0g>6=#:j0846*>f;08 76=;h1b:7>5;h0a>5<<{?0;6o5r}of94?7|ugo1<7?t}|~DEE|980n>ihm6g4~DED|8tJK\vsO@ \ No newline at end of file diff --git a/xilinx/ALU/processeur.ngr b/xilinx/ALU/processeur.ngr new file mode 100644 index 0000000..a2895f4 --- /dev/null +++ b/xilinx/ALU/processeur.ngr @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0:x0f=(`fgn#kazsrcww*Drzlk~#}|`jdv\w|usmd%{~bdjt^qzwqcjm&rb`d`w/@NV+uthklyxix|!viff?3ukp8!1!QWQG&7&8*J_NGF1d9[WQYNEYFNAH@[AUKLJZEHFZ^YMD@[S028\VRXZ]FT\_A_ESVZ2>^cjVCo==5Wdl]Neoiu^lxxeb`>0:ZgiZKnffx]i}foo18\vr>3QyK@akemc8twidmzyny?>;ya5wi~6>$9&o~i<25CDue:9344967>?8rd:>7?4n0192>"693o0q^=51585>453>:?=6?<7819g53<7280:w^:51585>453>:?=6?<7819uB<<7280:6=u\4;37>3<6;=<89;4=29:3?!b==2.<6<5m1783>7<729qGj7?t$6823>{K9909w)o50:la>75=831vqpsO@By`>g37>=i>qMNM{1CDU}zHI \ No newline at end of file diff --git a/xilinx/ALU/processeur.prj b/xilinx/ALU/processeur.prj new file mode 100644 index 0000000..8bfc086 --- /dev/null +++ b/xilinx/ALU/processeur.prj @@ -0,0 +1,6 @@ +vhdl work "pipeline.vhd" +vhdl work "br.vhd" +vhdl work "bm_instr.vhd" +vhdl work "bm.vhd" +vhdl work "alu.vhd" +vhdl work "processeur.vhd" diff --git a/xilinx/ALU/processeur.stx b/xilinx/ALU/processeur.stx new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ALU/processeur.syr b/xilinx/ALU/processeur.syr new file mode 100644 index 0000000..ceb40e4 --- /dev/null +++ b/xilinx/ALU/processeur.syr @@ -0,0 +1,303 @@ +Release 13.4 - xst O.87xd (lin64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Reading design: processeur.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "processeur.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "processeur" +Output Format : NGC +Target Device : xc6slx16-3-csg324 + +---- Source Options +Top Module Name : processeur +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + +INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL + +========================================================================= +* HDL Parsing * +========================================================================= +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work +Parsing entity
. +Parsing architecture of entity
. +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work +Parsing entity . +Parsing architecture of entity . + +========================================================================= +* HDL Elaboration * +========================================================================= + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity
(architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance of block
are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd". +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block processeur, actual ratio is 0. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Found no macro +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : processeur.ngc + +Primitive and Black Box Usage: +------------------------------ + +Device utilization summary: +--------------------------- + +Selected Device : 6slx16csg324-3 + + +Slice Logic Utilization: + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 0 + Number with an unused Flip Flop: 0 out of 0 + Number with an unused LUT: 0 out of 0 + Number of fully used LUT-FF pairs: 0 out of 0 + Number of unique control sets: 0 + +IO Utilization: + Number of IOs: 2 + Number of bonded IOBs: 0 out of 232 0% + +Specific Feature Utilization: + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -3 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: No path found + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +========================================================================= + + +Total REAL time to Xst completion: 4.00 secs +Total CPU time to Xst completion: 2.94 secs + +--> + + +Total memory usage is 389560 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 8 ( 0 filtered) +Number of infos : 7 ( 0 filtered) + diff --git a/xilinx/ALU/processeur.vhd b/xilinx/ALU/processeur.vhd index 04b95cd..536a9c6 100644 --- a/xilinx/ALU/processeur.vhd +++ b/xilinx/ALU/processeur.vhd @@ -1,271 +1,303 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:52:06 05/04/2021 --- Design Name: --- Module Name: processeur - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; + ---------------------------------------------------------------------------------- + -- Company: + -- Engineer: + -- + -- Create Date: 12:52:06 05/04/2021 + -- Design Name: + -- Module Name: processeur - Behavioral + -- Project Name: + -- Target Devices: + -- Tool versions: + -- Description: + -- + -- Dependencies: + -- + -- Revision: + -- Revision 0.01 - File Created + -- Additional Comments: + -- + ---------------------------------------------------------------------------------- + library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; + use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; + -- Uncomment the following library declaration if using + -- arithmetic functions with Signed or Unsigned values + --use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; + -- Uncomment the following library declaration if instantiating + -- any Xilinx primitives in this code. + --library UNISIM; + --use UNISIM.VComponents.all; -entity processeur is - Port ( CLK: in STD_LOGIC ; - RST : in STD_LOGIC); -end processeur; + entity processeur is + Port ( CLK: in STD_LOGIC ; + RST : in STD_LOGIC); + end processeur; -architecture Behavioral of processeur is - COMPONENT bm_instr - PORT( - IN_addr : IN std_logic_vector(7 downto 0); - OUT_data : OUT std_logic_vector(31 downto 0); - CLK : IN std_logic - ); - END COMPONENT; - - COMPONENT pipeline - PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0); - A_IN : in STD_LOGIC_VECTOR (7 downto 0); - B_IN : in STD_LOGIC_VECTOR (7 downto 0); - C_IN : in STD_LOGIC_VECTOR (7 downto 0); - CLK : IN std_logic; - OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); - A_OUT : out STD_LOGIC_VECTOR (7 downto 0); - B_OUT : out STD_LOGIC_VECTOR (7 downto 0); - C_OUT : out STD_LOGIC_VECTOR (7 downto 0) - ); - END COMPONENT; - - COMPONENT br - PORT( - A_addr : IN std_logic_vector(3 downto 0); - B_addr : IN std_logic_vector(3 downto 0); - W_addr : IN std_logic_vector(3 downto 0); - W : IN std_logic; - Data : IN std_logic_vector(7 downto 0); - RST : IN std_logic; - CLK : IN std_logic; - QA : OUT std_logic_vector(7 downto 0); - QB : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - COMPONENT alu - PORT( - A : IN std_logic_vector(7 downto 0); - B : IN std_logic_vector(7 downto 0); - Ctrl_Alu : IN std_logic_vector(2 downto 0); - N : OUT std_logic; - O : OUT std_logic; - Z : OUT std_logic; - C : OUT std_logic; - S : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - COMPONENT bm_data - PORT( - IN_addr : IN std_logic_vector(7 downto 0); - IN_data : IN std_logic_vector(7 downto 0); - RW : IN std_logic; - RST : IN std_logic; - CLK : IN std_logic; - OUT_data : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; + architecture Behavioral of processeur is + COMPONENT bm_instr + PORT( + IN_addr : IN std_logic_vector(7 downto 0); + OUT_data : OUT std_logic_vector(31 downto 0); + CLK : IN std_logic + ); + END COMPONENT; + + COMPONENT pipeline + PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0); + A_IN : in STD_LOGIC_VECTOR (7 downto 0); + B_IN : in STD_LOGIC_VECTOR (7 downto 0); + C_IN : in STD_LOGIC_VECTOR (7 downto 0); + CLK : IN std_logic; + EN : in STD_LOGIC; + OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); + A_OUT : out STD_LOGIC_VECTOR (7 downto 0); + B_OUT : out STD_LOGIC_VECTOR (7 downto 0); + C_OUT : out STD_LOGIC_VECTOR (7 downto 0) + ); + END COMPONENT; + + COMPONENT br + PORT( + A_addr : IN std_logic_vector(3 downto 0); + B_addr : IN std_logic_vector(3 downto 0); + W_addr : IN std_logic_vector(3 downto 0); + W : IN std_logic; + Data : IN std_logic_vector(7 downto 0); + RST : IN std_logic; + CLK : IN std_logic; + QA : OUT std_logic_vector(7 downto 0); + QB : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + COMPONENT alu + PORT( + A : IN std_logic_vector(7 downto 0); + B : IN std_logic_vector(7 downto 0); + Ctrl_Alu : IN std_logic_vector(2 downto 0); + N : OUT std_logic; + O : OUT std_logic; + Z : OUT std_logic; + C : OUT std_logic; + S : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + COMPONENT bm_data + PORT( + IN_addr : IN std_logic_vector(7 downto 0); + IN_data : IN std_logic_vector(7 downto 0); + RW : IN std_logic; + RST : IN std_logic; + CLK : IN std_logic; + OUT_data : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + --Inputs + signal IP : std_logic_vector(7 downto 0) := (others => '0'); + signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); + + signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); + + --Outputs + signal OUT_data : std_logic_vector(31 downto 0); + + signal OP_LIDI_OUT : std_logic_vector(7 downto 0); + signal A_LIDI_OUT : std_logic_vector(7 downto 0); + signal B_LIDI_OUT : std_logic_vector(7 downto 0); + signal C_LIDI_OUT : std_logic_vector(7 downto 0); + + signal OP_DIEX_OUT : std_logic_vector(7 downto 0); + signal A_DIEX_OUT : std_logic_vector(7 downto 0); + signal B_DIEX_OUT : std_logic_vector(7 downto 0); + signal C_DIEX_OUT : std_logic_vector(7 downto 0); + + signal O_ALU_OUT : std_logic; + signal N_ALU_OUT : std_logic; + signal Z_ALU_OUT : std_logic; + signal C_ALU_OUT : std_logic; + + signal A_EXMem_OUT : std_logic_vector(7 downto 0); + signal B_EXMem_OUT : std_logic_vector(7 downto 0); + signal OP_EXMem_OUT : std_logic_vector(7 downto 0); + + signal A_MemRE_OUT : std_logic_vector(7 downto 0); + signal B_MemRE_OUT : std_logic_vector(7 downto 0); + signal OP_MemRE_OUT : std_logic_vector(7 downto 0); + + --AUX + + signal Ctr_ALU_LC : std_logic_vector(2 downto 0); + signal RW_LC : std_logic; + signal addr_dm_MUX : std_logic_vector(7 downto 0); + signal in_dm_MUX : std_logic_vector(7 downto 0); + signal out_dm_MUX : std_logic_vector(7 downto 0); + signal B_EXMem_IN : std_logic_vector(7 downto 0); + signal W_br_LC : std_logic; + signal S_IN_MUX : std_logic_vector(7 downto 0); + signal B_MemRE_IN : std_logic_vector(7 downto 0); + + --alea + signal li_di_r_b : std_logic; + signal li_di_r_c : std_logic; + signal di_ex_w_a : std_logic; + signal ex_mem_w_a : std_logic; + signal alea : std_logic; - --Inputs - signal IP : std_logic_vector(7 downto 0) := (others => '0'); - signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); + begin + + -- Instantiate adresse des instructions + addr_instructions: bm_instr PORT MAP ( + IN_addr => IP, + OUT_data => OUT_data, + CLK => CLK + ); - signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); - signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); - - --Outputs - signal OUT_data : std_logic_vector(31 downto 0); - - signal OP_LIDI_OUT : std_logic_vector(7 downto 0); - signal A_LIDI_OUT : std_logic_vector(7 downto 0); - signal B_LIDI_OUT : std_logic_vector(7 downto 0); - signal C_LIDI_OUT : std_logic_vector(7 downto 0); - - signal OP_DIEX_OUT : std_logic_vector(7 downto 0); - signal A_DIEX_OUT : std_logic_vector(7 downto 0); - signal B_DIEX_OUT : std_logic_vector(7 downto 0); - signal C_DIEX_OUT : std_logic_vector(7 downto 0); - - signal O_ALU_OUT : std_logic; - signal N_ALU_OUT : std_logic; - signal Z_ALU_OUT : std_logic; - signal C_ALU_OUT : std_logic; - - signal A_EXMem_OUT : std_logic_vector(7 downto 0); - signal B_EXMem_OUT : std_logic_vector(7 downto 0); - signal OP_EXMem_OUT : std_logic_vector(7 downto 0); - - signal A_MemRE_OUT : std_logic_vector(7 downto 0); - signal B_MemRE_OUT : std_logic_vector(7 downto 0); - signal OP_MemRE_OUT : std_logic_vector(7 downto 0); - - --AUX - - signal Ctr_ALU_LC : std_logic_vector(2 downto 0); - signal RW_LC : std_logic; - signal addr_dm_MUX : std_logic_vector(7 downto 0); - signal in_dm_MUX : std_logic_vector(7 downto 0); - signal out_dm_MUX : std_logic_vector(7 downto 0); - signal B_EXMem_IN : std_logic_vector(7 downto 0); - signal W_br_LC : std_logic; - signal S_IN_MUX : std_logic_vector(7 downto 0); - signal B_MemRE_IN : std_logic_vector(7 downto 0); - -begin - - -- Instantiate adresse des instructions - addr_instructions: bm_instr PORT MAP ( - IN_addr => IP, - OUT_data => OUT_data, - CLK => CLK - ); - - -- Instantiate pipeline LI_LD - LI_LD : pipeline PORT MAP ( - OP_IN => OUT_data(31 downto 24), - A_IN => OUT_data(23 downto 16), - B_IN => OUT_data(15 downto 8), - C_IN => OUT_data(7 downto 0), - CLK => CLK, - A_OUT => A_LIDI_OUT, - B_OUT => B_LIDI_OUT, - C_OUT => C_LIDI_OUT, - OP_OUT => OP_LIDI_OUT - ); - W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else - '0'; - -- Instanciate banc de registre - banc_registres : br PORT MAP ( - A_addr => B_LIDI_OUT(3 downto 0), - B_addr => C_LIDI_OUT(3 downto 0), - W_addr => A_MemRE_OUT(3 downto 0), - W => W_br_LC, --ATTENTION LC - Data => B_MemRE_OUT, - RST => RST, - CLK => CLK, - QA => QA_IN_MUX, - QB => C_DIEX_IN - ); - - B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ; - - - -- Instantiate pipeline DI_EX - DI_EX : pipeline PORT MAP ( - OP_IN => OP_LIDI_OUT, - A_IN => A_LIDI_OUT, - B_IN => B_DIEX_IN, - C_IN => C_DIEX_IN, - CLK => CLK, - A_OUT => A_DIEX_OUT, - B_OUT => B_DIEX_OUT, - C_OUT => C_DIEX_OUT, - OP_OUT => OP_DIEX_OUT - ); - - Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else - "010" when OP_DIEX_OUT = x"03" else - "011" when OP_DIEX_OUT = x"02" else - "000"; - - -- Instantiate alu - UAL : alu PORT MAP ( - A => B_DIEX_OUT, - B => C_DIEX_OUT, - Ctrl_Alu =>Ctr_AlU_LC, - N => N_ALU_OUT, - O => O_ALU_OUT, - Z => Z_ALU_OUT, - C => C_ALU_OUT, - S => S_IN_MUX - ); - - B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else - B_DIEX_OUT ; + -- Instantiate pipeline LI_LD + LI_LD : pipeline PORT MAP ( + OP_IN => OUT_data(31 downto 24), + A_IN => OUT_data(23 downto 16), + B_IN => OUT_data(15 downto 8), + C_IN => OUT_data(7 downto 0), + CLK => CLK, + EN => alea, + A_OUT => A_LIDI_OUT, + B_OUT => B_LIDI_OUT, + C_OUT => C_LIDI_OUT, + OP_OUT => OP_LIDI_OUT + ); + W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else + '0'; - - -- Instantiate pipeline EX_Mem - EX_Mem : pipeline PORT MAP ( - OP_IN => OP_DIEX_OUT, - A_IN => A_DIEX_OUT, - B_IN => B_EXMem_IN, - C_IN => x"00", - CLK => CLK, - A_OUT => A_EXMem_OUT, - B_OUT => B_EXMem_OUT, - C_OUT => open, - OP_OUT => OP_EXMem_OUT - ); - - RW_LC <= '0' when OP_EXMem_OUT = x"08" else - '1'; - addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else - A_EXMem_OUT; - in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; - B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else - B_EXMem_OUT; - -- Instantiate banc de données - data_memory: bm_data PORT MAP ( - IN_addr => addr_dm_MUX, - IN_data => B_MemRE_IN, - RW => RW_LC, - RST => RST, - CLK => CLK, - OUT_data => out_dm_MUX - ); + --alea LI_DI + li_di_r_b <= '1' when OUT_data(31 downto 24) = x"05" or OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" or OUT_data(31 downto 24) = x"08" + else '0'; + li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" + else '0'; + -- Instanciate banc de registre + banc_registres : br PORT MAP ( + A_addr => B_LIDI_OUT(3 downto 0), + B_addr => C_LIDI_OUT(3 downto 0), + W_addr => A_MemRE_OUT(3 downto 0), + W => W_br_LC, --ATTENTION LC + Data => B_MemRE_OUT, + RST => RST, + CLK => CLK, + QA => QA_IN_MUX, + QB => C_DIEX_IN + ); + + B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ; + + + -- Instantiate pipeline DI_EX + DI_EX : pipeline PORT MAP ( + OP_IN => OP_LIDI_OUT, + A_IN => A_LIDI_OUT, + B_IN => B_DIEX_IN, + C_IN => C_DIEX_IN, + CLK => CLK, + EN => '1', + A_OUT => A_DIEX_OUT, + B_OUT => B_DIEX_OUT, + C_OUT => C_DIEX_OUT, + OP_OUT => OP_DIEX_OUT + ); + + Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else + "010" when OP_DIEX_OUT = x"03" else + "011" when OP_DIEX_OUT = x"02" else + "000"; + -- alea DI_EX + di_ex_w_a <= '0' when OP_LIDI_OUT = x"08" or OP_LIDI_OUT = x"00" + else '1'; + -- Instantiate alu + UAL : alu PORT MAP ( + A => B_DIEX_OUT, + B => C_DIEX_OUT, + Ctrl_Alu =>Ctr_AlU_LC, + N => N_ALU_OUT, + O => O_ALU_OUT, + Z => Z_ALU_OUT, + C => C_ALU_OUT, + S => S_IN_MUX + ); + + B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else + B_DIEX_OUT ; + + + -- Instantiate pipeline EX_Mem + EX_Mem : pipeline PORT MAP ( + OP_IN => OP_DIEX_OUT, + A_IN => A_DIEX_OUT, + B_IN => B_EXMem_IN, + C_IN => x"00", + CLK => CLK, + EN => '1', + A_OUT => A_EXMem_OUT, + B_OUT => B_EXMem_OUT, + C_OUT => open, + OP_OUT => OP_EXMem_OUT + ); + + RW_LC <= '0' when OP_EXMem_OUT = x"08" else + '1'; + addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else + A_EXMem_OUT; + in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; + B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else + B_EXMem_OUT; + + -- alea ex_mem + ex_mem_w_a <= '0' when OP_DIEX_OUT = x"08" or OP_DIEX_OUT = x"00" + else '1'; + -- Instantiate banc de données + data_memory: bm_data PORT MAP ( + IN_addr => addr_dm_MUX, + IN_data => in_dm_MUX, + RW => RW_LC, + RST => RST, + CLK => CLK, + OUT_data => out_dm_MUX + ); + + -- Instantiate pipeline Mem_RE + Mem_RE : pipeline PORT MAP ( + OP_IN => OP_EXMem_OUT, + A_IN => A_EXMem_OUT, + B_IN => B_MemRE_IN, + C_IN => x"00", + CLK => CLK, + EN => '1', + A_OUT => A_MemRE_OUT, + B_OUT => B_MemRE_OUT, + C_OUT => open, + OP_OUT => OP_MemRE_OUT + ); + + alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or + (li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or + (li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or + (li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else + '1'; - -- Instantiate pipeline Mem_RE - Mem_RE : pipeline PORT MAP ( - OP_IN => OP_EXMem_OUT, - A_IN => A_EXMem_OUT, - B_IN => B_EXMem_OUT, - C_IN => x"00", - CLK => CLK, - A_OUT => A_MemRE_OUT, - B_OUT => B_MemRE_OUT, - C_OUT => open, - OP_OUT => OP_MemRE_OUT - ); - process + process begin wait until rising_edge(CLK); if rst = '0' then IP <= x"00"; else - IP <= IP + "00000001"; + if alea = '1' then + IP <= IP + "00000001"; + end if; end if; end process; - -end Behavioral; - + + end Behavioral; diff --git a/xilinx/ALU/processeur.xst b/xilinx/ALU/processeur.xst new file mode 100644 index 0000000..b644f1c --- /dev/null +++ b/xilinx/ALU/processeur.xst @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn processeur.prj +-ofn processeur +-ofmt NGC +-p xc6slx16-3-csg324 +-top processeur +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/ALU/processeur_envsettings.html b/xilinx/ALU/processeur_envsettings.html new file mode 100644 index 0000000..2d84867 --- /dev/null +++ b/xilinx/ALU/processeur_envsettings.html @@ -0,0 +1,404 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:
/usr/local/insa/lib:
$LD_LIBRARY_PATH		/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:
/usr/local/insa/lib:
$LD_LIBRARY_PATH		< data not available >< data not available >
PATH/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:
/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:
/usr/local/insa/shared/opam/system/bin:
/usr/local/insa/lustre-v4-III-dc-linux64/bin:
/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:
/usr/local/insa/anaconda/bin:
/usr/local/insa/bin:
/usr/local/insa/sbin:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/usr/local/insa/tina/bin:
/snap/bin		/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:
/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:
/usr/local/insa/shared/opam/system/bin:
/usr/local/insa/lustre-v4-III-dc-linux64/bin:
/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:
/usr/local/insa/anaconda/bin:
/usr/local/insa/bin:
/usr/local/insa/sbin:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/usr/local/insa/tina/bin:
/snap/bin		< data not available >< data not available >
XILINX/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/< data not available >< data not available >
XILINXD_LICENSE_FILE/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic< data not available >< data not available >
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn processeur.prj 
-ofn processeur 
-ofmt NGCNGC
-p xc6slx16-3-csg324 
-top processeur 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
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Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc6slx16-csg324-3None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4277.214 MHzIntel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4276.892 MHz<  data not available  ><  data not available  >
Hostinsa-11291insa-11291<  data not available  ><  data not available  >
OS NameUbuntuUbuntu<  data not available  ><  data not available  >
OS ReleaseUbuntu 18.04.5 LTSUbuntu 18.04.5 LTS<  data not available  ><  data not available  >
+ \ No newline at end of file diff --git a/xilinx/ALU/processeur_map.map b/xilinx/ALU/processeur_map.map new file mode 100644 index 0000000..0f9c60d --- /dev/null +++ b/xilinx/ALU/processeur_map.map @@ -0,0 +1,23 @@ +Release 13.4 Map O.87xd (lin64) +Xilinx Map Application Log File for Design 'processeur' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Tue May 18 16:15:07 2021 + +ERROR:Map:116 - The design is empty. No processing will be done. +ERROR:Map:52 - Problem encountered processing RPMs. + + + +Design Summary +-------------- +Number of errors : 2 +Number of warnings : 0 diff --git a/xilinx/ALU/processeur_map.mrp b/xilinx/ALU/processeur_map.mrp new file mode 100644 index 0000000..7bc54ad --- /dev/null +++ b/xilinx/ALU/processeur_map.mrp @@ -0,0 +1,31 @@ +Release 13.4 Map O.87xd (lin64) +Xilinx Mapping Report File for Design 'processeur' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Tue May 18 16:15:07 2021 + +Design Summary +-------------- +Number of errors : 2 +Number of warnings : 0 + +Section 1 - Errors +------------------ +ERROR:Map:116 - The design is empty. No processing will be done. +ERROR:Map:52 - Problem encountered processing RPMs. + + + +Section 2 - Warnings +-------------------- + +Section 3 - Informational +------------------------- diff --git a/xilinx/ALU/processeur_ngdbuild.xrpt b/xilinx/ALU/processeur_ngdbuild.xrpt new file mode 100644 index 0000000..c2d89e9 --- /dev/null +++ b/xilinx/ALU/processeur_ngdbuild.xrpt @@ -0,0 +1,67 @@ + + + + + + +
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processeur Project Status
processeur Project Status (05/18/2021 - 16:15:09)
Project File: ALU.xiseModule Name: processeur Implementation State:NewMapped (Failed)
Target Device: xc6slx16-3csg324
  • Errors:
  +X +2 Errors (2 new)
Product Version:ISE 13.4
  • Warnings:
 9 Warnings (9 new)
Design Goal:
Environment:  + +System Settings +
  • Final Timing Score:
   
+ +
Device Utilization Summary [-]
@@ -61,9 +68,9 @@ Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos -Synthesis Report      -Translation Report      -Map Report      +Synthesis ReportCurrentmar. mai 18 16:14:40 202108 Warnings (8 new)7 Infos (7 new) +Translation ReportCurrentmar. mai 18 16:15:06 202101 Warning (1 new)0 +Map ReportCurrentmar. mai 18 16:15:09 2021X 2 Errors (2 new)00 Place and Route Report      Power Report      Post-PAR Static Timing Report      @@ -72,9 +79,9 @@  
- +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datelun. mai 10 10:45:43 2021
ISIM Simulator LogOut of Datemar. mai 18 16:15:36 2021
-
Date Generated: 05/10/2021 - 10:47:06
+
Date Generated: 05/18/2021 - 16:16:17
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