From db6969e20e63d489a3fe6553612e69673bb473b5 Mon Sep 17 00:00:00 2001 From: Foussats Morgane Date: Tue, 18 May 2021 16:40:36 +0200 Subject: [PATCH] alea ok --- xilinx/ALU/ALU.gise | 123 +- xilinx/ALU/ALU.xise | 12 +- xilinx/ALU/_ngo/netlist.lst | 3 + xilinx/ALU/_xmsgs/map.xmsgs | 15 + xilinx/ALU/_xmsgs/ngdbuild.xmsgs | 12 + xilinx/ALU/_xmsgs/pn_parser.xmsgs | 2 +- xilinx/ALU/_xmsgs/xst.xmsgs | 54 + xilinx/ALU/bm_instr.vhd | 28 +- xilinx/ALU/bm_instr_isim_beh.exe | Bin 0 -> 21792 bytes xilinx/ALU/fuse.log | 8 +- xilinx/ALU/iseconfig/ALU.projectmgr | 16 +- xilinx/ALU/iseconfig/processeur.xreport | 4 +- xilinx/ALU/isim.log | 70 + xilinx/ALU/isim/isim_usage_statistics.html | 10 +- xilinx/ALU/isim/lockfile1 | 0 .../ieee/p_1242562249.didat | Bin 8516 -> 8516 bytes .../ieee/p_2592010699.didat | Bin 5844 -> 5844 bytes .../ieee/p_3499444699.didat | Bin 4332 -> 4332 bytes .../ieee/p_3620187407.didat | Bin 2264 -> 2264 bytes .../ISimEngine-DesignHierarchy.dbg | Bin 18885 -> 19887 bytes .../ISimEngine-DesignHierarchy1.dbg | Bin 0 -> 19887 bytes .../isimkernel.log | 24 +- .../process_test_isim_beh.exe.sim/netId.dat | Bin 564 -> 636 bytes .../process_test_isim_beh.exe.sim/netId1.dat | Bin 0 -> 28 bytes .../process_test_isim_beh.exe | Bin 249968 -> 254384 bytes .../process_test_isim_beh.exe.sim/tmp_save/_1 | Bin 131871 -> 132679 bytes .../work/a_0832606739_3212880686.didat | Bin 7452 -> 7452 bytes .../work/a_1229531095_2372691052.didat | Bin 3596 -> 3596 bytes .../work/a_1466808984_3212880686.didat | Bin 5956 -> 5956 bytes .../work/a_1802466774_3212880686.c | 2 +- .../work/a_1802466774_3212880686.didat | Bin 11612 -> 11612 bytes .../work/a_1802466774_3212880686.lin64.o | Bin 3048 -> 3048 bytes .../work/a_3650175700_3212880686.c | 131 +- .../work/a_3650175700_3212880686.didat | Bin 4172 -> 4376 bytes .../work/a_3650175700_3212880686.lin64.o | Bin 3376 -> 3952 bytes .../work/a_3998322972_3212880686.didat | Bin 5172 -> 5172 bytes .../work/a_4150868852_3212880686.c | 2123 +++++++++++++---- .../work/a_4150868852_3212880686.didat | Bin 19856 -> 23632 bytes .../work/a_4150868852_3212880686.lin64.o | Bin 9992 -> 15248 bytes xilinx/ALU/isim/work/alu.vdb | Bin 7331 -> 7331 bytes xilinx/ALU/isim/work/bm_data.vdb | Bin 5103 -> 5103 bytes xilinx/ALU/isim/work/bm_instr.vdb | Bin 4033 -> 4033 bytes xilinx/ALU/isim/work/br.vdb | Bin 6251 -> 6251 bytes xilinx/ALU/isim/work/pipeline.vdb | Bin 3621 -> 4185 bytes xilinx/ALU/isim/work/process_test.vdb | Bin 3201 -> 3201 bytes xilinx/ALU/isim/work/processeur.vdb | Bin 25562 -> 31218 bytes xilinx/ALU/pipeline.vhd | 18 +- xilinx/ALU/process_test_isim_beh.wdb | Bin 51420 -> 210954 bytes xilinx/ALU/process_test_isim_beh1.wdb | Bin 0 -> 21205 bytes xilinx/ALU/processeur.bld | 42 + xilinx/ALU/processeur.cmd_log | 3 + xilinx/ALU/processeur.lso | 1 + xilinx/ALU/processeur.ngc | 3 + xilinx/ALU/processeur.ngd | 3 + xilinx/ALU/processeur.ngr | 3 + xilinx/ALU/processeur.prj | 6 + xilinx/ALU/processeur.stx | 0 xilinx/ALU/processeur.syr | 303 +++ xilinx/ALU/processeur.vhd | 542 +++-- xilinx/ALU/processeur.xst | 52 + xilinx/ALU/processeur_envsettings.html | 404 ++++ xilinx/ALU/processeur_map.map | 23 + xilinx/ALU/processeur_map.mrp | 31 + xilinx/ALU/processeur_ngdbuild.xrpt | 67 + xilinx/ALU/processeur_summary.html | 29 +- xilinx/ALU/processeur_xst.xrpt | 129 + xilinx/ALU/webtalk_pn.xml | 43 + xilinx/ALU/xlnx_auto_0_xdb/cst.xbcd | Bin 0 -> 61 bytes xilinx/ALU/xst/work/work.vdbl | Bin 0 -> 57835 bytes xilinx/ALU/xst/work/work.vdbx | Bin 0 -> 168 bytes 70 files changed, 3532 insertions(+), 807 deletions(-) create mode 100644 xilinx/ALU/_ngo/netlist.lst create mode 100644 xilinx/ALU/_xmsgs/map.xmsgs create mode 100644 xilinx/ALU/_xmsgs/ngdbuild.xmsgs create mode 100644 xilinx/ALU/_xmsgs/xst.xmsgs create mode 100755 xilinx/ALU/bm_instr_isim_beh.exe create mode 100644 xilinx/ALU/isim/lockfile1 create mode 100644 xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg create mode 100644 xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat create mode 100644 xilinx/ALU/process_test_isim_beh1.wdb create mode 100644 xilinx/ALU/processeur.bld create mode 100644 xilinx/ALU/processeur.cmd_log create mode 100644 xilinx/ALU/processeur.lso create mode 100644 xilinx/ALU/processeur.ngc create mode 100644 xilinx/ALU/processeur.ngd create mode 100644 xilinx/ALU/processeur.ngr create mode 100644 xilinx/ALU/processeur.prj create mode 100644 xilinx/ALU/processeur.stx create mode 100644 xilinx/ALU/processeur.syr create mode 100644 xilinx/ALU/processeur.xst create mode 100644 xilinx/ALU/processeur_envsettings.html create mode 100644 xilinx/ALU/processeur_map.map create mode 100644 xilinx/ALU/processeur_map.mrp create mode 100644 xilinx/ALU/processeur_ngdbuild.xrpt create mode 100644 xilinx/ALU/processeur_xst.xrpt create mode 100644 xilinx/ALU/webtalk_pn.xml create mode 100644 xilinx/ALU/xlnx_auto_0_xdb/cst.xbcd create mode 100644 xilinx/ALU/xst/work/work.vdbl create mode 100644 xilinx/ALU/xst/work/work.vdbx diff --git a/xilinx/ALU/ALU.gise b/xilinx/ALU/ALU.gise index 7a6fa15..e76ce05 100644 --- a/xilinx/ALU/ALU.gise +++ b/xilinx/ALU/ALU.gise @@ -22,10 +22,15 @@ + + + + + @@ -37,7 +42,26 @@ + + + + + + + + + + + + + + + + + + + @@ -49,9 +73,13 @@ - + + + + + @@ -64,11 +92,11 @@ - + - + @@ -76,9 +104,14 @@ - + + + + + + @@ -91,9 +124,14 @@ - + + + + + + @@ -101,13 +139,86 @@ - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/ALU/ALU.xise b/xilinx/ALU/ALU.xise index ecd5fc7..99ead22 100644 --- a/xilinx/ALU/ALU.xise +++ b/xilinx/ALU/ALU.xise @@ -17,7 +17,7 @@ - + @@ -27,7 +27,7 @@ - + @@ -37,11 +37,11 @@ - + - + @@ -57,11 +57,11 @@ - + - + diff --git a/xilinx/ALU/_ngo/netlist.lst b/xilinx/ALU/_ngo/netlist.lst new file mode 100644 index 0000000..52fad93 --- /dev/null +++ b/xilinx/ALU/_ngo/netlist.lst @@ -0,0 +1,3 @@ +/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280 +/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280 +OK diff --git a/xilinx/ALU/_xmsgs/map.xmsgs b/xilinx/ALU/_xmsgs/map.xmsgs new file mode 100644 index 0000000..36d6790 --- /dev/null +++ b/xilinx/ALU/_xmsgs/map.xmsgs @@ -0,0 +1,15 @@ + + + +The design is empty. No processing will be done. + + +Problem encountered processing RPMs. + + + + diff --git a/xilinx/ALU/_xmsgs/ngdbuild.xmsgs b/xilinx/ALU/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..e7f0f74 --- /dev/null +++ b/xilinx/ALU/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,12 @@ + + + +Design contains no instances. + + + + diff --git a/xilinx/ALU/_xmsgs/pn_parser.xmsgs b/xilinx/ALU/_xmsgs/pn_parser.xmsgs index 0e8e45c..e6bbd48 100644 --- a/xilinx/ALU/_xmsgs/pn_parser.xmsgs +++ b/xilinx/ALU/_xmsgs/pn_parser.xmsgs @@ -8,7 +8,7 @@ -Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work diff --git a/xilinx/ALU/_xmsgs/xst.xmsgs b/xilinx/ALU/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..2d3bb0e --- /dev/null +++ b/xilinx/ALU/_xmsgs/xst.xmsgs @@ -0,0 +1,54 @@ + + + +Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance <addr_instructions> of block <bm_instr> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance <LI_LD> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance <banc_registres> of block <br> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance <DI_EX> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance <UAL> of block <alu> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance <EX_Mem> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance <data_memory> of block <bm_data> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance <Mem_RE> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <N> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <O> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <Z> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <C> of the instance <UAL> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port <C_OUT> of the instance <EX_Mem> is unconnected or connected to loadless signal. + + +"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port <C_OUT> of the instance <Mem_RE> is unconnected or connected to loadless signal. + + + + diff --git a/xilinx/ALU/bm_instr.vhd b/xilinx/ALU/bm_instr.vhd index a51c05d..fb4057e 100644 --- a/xilinx/ALU/bm_instr.vhd +++ b/xilinx/ALU/bm_instr.vhd @@ -34,12 +34,36 @@ architecture Behavioral of bm_instr is type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0); -- instruction "00000110 00000001 00000110 00000000" --test afc ---signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); +signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000"); --test afc cop -signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); +--test afc cop alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000"); --test add --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); +--test add alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000"); +--test sub + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000"); + +--test mul + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000"); + +--test store + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000"); + +--test store alea +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000"); + +--test load + +--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000"); + + begin OUT_data <= instr_memory(to_integer(unsigned(IN_addr))); diff --git a/xilinx/ALU/bm_instr_isim_beh.exe b/xilinx/ALU/bm_instr_isim_beh.exe new file mode 100755 index 0000000000000000000000000000000000000000..beb9ccd0da76c9db1831f53276aaa98f8c0d76b2 GIT binary patch literal 21792 zcmeHPeRNdSwLkfS6d@B7Gy=*MhZe*P2_~4t1ZS8D+_A%l5G?x8nPFy{(J+P{3p=WQ!PKN`;-1j5}k#8Fck*S(CyEWFE1Vn%@FOIQD_H7 zxSaq~__$X5b>5!YN? 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- 2021-05-10T10:47:06 + 2021-05-18T16:14:30 processeur Unknown /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport - /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU + /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/ 2021-05-10T09:34:56 false
diff --git a/xilinx/ALU/isim.log b/xilinx/ALU/isim.log index ac9885d..69c11ff 100644 --- a/xilinx/ALU/isim.log +++ b/xilinx/ALU/isim.log @@ -45,4 +45,74 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). +Finished circuit initialization process. +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 # exit 0 diff --git a/xilinx/ALU/isim/isim_usage_statistics.html b/xilinx/ALU/isim/isim_usage_statistics.html index 8db4a1e..be08e85 100644 --- a/xilinx/ALU/isim/isim_usage_statistics.html +++ b/xilinx/ALU/isim/isim_usage_statistics.html @@ -2,14 +2,14 @@ ISim Statistics Xilinx HDL Libraries Used=ieee -Fuse Resource Usage=850 ms, 1723208 KB +Fuse Resource Usage=980 ms, 1723384 KB -Total Signals=109 -Total Nets=10695 +Total Signals=121 +Total Nets=10703 Total Blocks=14 -Total Processes=31 +Total Processes=36 Total Simulation Time=1 us -Simulation Resource Usage=0.04 sec, 264146 KB +Simulation Resource Usage=0.03 sec, 264171 KB Simulation Mode=gui Hardware CoSim=0 diff --git a/xilinx/ALU/isim/lockfile1 b/xilinx/ALU/isim/lockfile1 new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat b/xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat index 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index 43b3bf6..86c6e6a 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log @@ -2,28 +2,28 @@ Command line: process_test_isim_beh.exe -simmode gui -simrunnum 0 - -socket 43981 + -socket 37953 -Mon May 10 12:31:07 2021 +Tue May 18 16:16:44 2021 Elaboration Time: 0.01 sec - Current Memory Usage: 189.698 Meg + Current Memory Usage: 189.723 Meg - Total Signals : 109 - Total Nets : 10695 - Total Signal Drivers : 44 + Total Signals : 121 + Total Nets : 10703 + Total Signal Drivers : 49 Total Blocks : 14 Total Primitive Blocks : 12 - Total Processes : 31 + Total Processes : 36 Total Traceable Variables : 16 - Total Scalar Nets and Variables : 11197 -Total Line Count : 66 + Total Scalar Nets and Variables : 11205 +Total Line Count : 92 - Total Simulation Time: 0.04 sec + Total Simulation Time: 0.03 sec - Current Memory Usage: 265.2 Meg + Current Memory Usage: 265.224 Meg -Mon May 10 12:32:41 2021 +Tue May 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a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c index 4990355..e98aa6a 100644 --- a/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c +++ b/xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c @@ -34,67 +34,74 @@ static void work_a_3650175700_3212880686_p_0(char *t0) char *t3; unsigned char t4; char *t5; - char *t6; + unsigned char t6; char *t7; char *t8; + char *t9; + char *t10; -LAB0: t1 = (t0 + 3464U); +LAB0: t1 = (t0 + 3624U); t2 = *((char **)t1); if (t2 == 0) goto LAB2; LAB3: goto *t2; -LAB2: xsi_set_current_line(49, ng0); +LAB2: xsi_set_current_line(50, ng0); -LAB6: t2 = (t0 + 3784); +LAB6: t2 = (t0 + 3944); *((int *)t2) = 1; *((char **)t1) = &&LAB7; LAB1: return; -LAB4: t5 = (t0 + 3784); +LAB4: t5 = (t0 + 3944); *((int *)t5) = 0; - xsi_set_current_line(50, ng0); - t2 = (t0 + 1032U); - t3 = *((char **)t2); - t2 = (t0 + 3864); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); - t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); xsi_set_current_line(51, ng0); - t2 = (t0 + 1192U); + t2 = (t0 + 1832U); t3 = *((char **)t2); - t2 = (t0 + 3928); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t4 = *((unsigned char *)t3); + t6 = (t4 == (unsigned char)3); + if (t6 != 0) + goto LAB8; + +LAB10: xsi_set_current_line(57, ng0); + t2 = (t0 + 6674); + t5 = (t0 + 4024); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - xsi_set_current_line(52, ng0); - t2 = (t0 + 1352U); - t3 = *((char **)t2); - t2 = (t0 + 3992); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(58, ng0); + t2 = (t0 + 6682); + t5 = (t0 + 4088); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - xsi_set_current_line(53, ng0); - t2 = (t0 + 1512U); - t3 = *((char **)t2); - t2 = (t0 + 4056); - t5 = (t2 + 56U); - t6 = *((char **)t5); - t7 = (t6 + 56U); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(59, ng0); + t2 = (t0 + 6690); + t5 = (t0 + 4152); + t7 = (t5 + 56U); t8 = *((char **)t7); - memcpy(t8, t3, 8U); - xsi_driver_first_trans_fast_port(t2); - goto LAB2; + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + xsi_set_current_line(60, ng0); + t2 = (t0 + 6698); + t5 = (t0 + 4216); + t7 = (t5 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t2, 8U); + xsi_driver_first_trans_fast_port(t5); + +LAB9: goto LAB2; LAB5: t3 = (t0 + 1632U); t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U); @@ -105,6 +112,48 @@ LAB5: t3 = (t0 + 1632U); LAB7: goto LAB5; +LAB8: xsi_set_current_line(52, ng0); + t2 = (t0 + 1032U); + t5 = *((char **)t2); + t2 = (t0 + 4024); + t7 = (t2 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t5, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(53, ng0); + t2 = (t0 + 1192U); + t3 = *((char **)t2); + t2 = (t0 + 4088); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(54, ng0); + t2 = (t0 + 1352U); + t3 = *((char **)t2); + t2 = (t0 + 4152); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + xsi_driver_first_trans_fast_port(t2); + xsi_set_current_line(55, ng0); + t2 = (t0 + 1512U); + t3 = *((char **)t2); + t2 = (t0 + 4216); + t5 = (t2 + 56U); + t7 = *((char **)t5); + t8 = (t7 + 56U); + t9 = *((char **)t8); + memcpy(t9, t3, 8U); + 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0); CLK : in STD_LOGIC; + EN : in STD_LOGIC; OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); A_OUT : out STD_LOGIC_VECTOR (7 downto 0); B_OUT : out STD_LOGIC_VECTOR (7 downto 0); @@ -47,10 +48,17 @@ begin process begin wait until rising_edge(CLK); - OP_OUT <= OP_IN; - A_OUT <= A_IN; - B_OUT <= B_IN; - C_OUT <= C_IN; - end process; + if (EN = '1') then + OP_OUT <= OP_IN; + A_OUT <= A_IN; + B_OUT <= B_IN; + C_OUT <= C_IN; + else + OP_OUT <= "00000000"; + A_OUT <= "00000000"; + B_OUT <= "00000000"; + C_OUT <= "00000000"; + end if; + end process; end Behavioral; diff --git a/xilinx/ALU/process_test_isim_beh.wdb b/xilinx/ALU/process_test_isim_beh.wdb index 6c339fb7203133da645434caf7256a2d883a5156..9119173241843a93f1ce017783ddc8d299c85618 100644 GIT binary patch literal 210954 zcmeF)4}5d;{r~@P1w{}PK@k*15fniYm!b%QA}ETWD1xFW!a9PYD1xG+=qQRJrs%eA ztF5!l%8HI`y6GtEwr=aTZhq%n?`Q3~%Q@uv`+WB2`~4=j+mYs;N8hj0lXKc$y)M`F zn*(0DHuCVUdrq9T>7)1keB+lro@G4ttz*f5J)W|cmtFE!?m`3aePA9R_o2D}^ndx5 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76=;h1b:7>5;h0a>5<<{?0;6o5r}of94?7|ugo1<7?t}|~DEE|980n>ihm6g4~DED|8tJK\vsO@ \ No newline at end of file diff --git a/xilinx/ALU/processeur.ngr b/xilinx/ALU/processeur.ngr new file mode 100644 index 0000000..a2895f4 --- /dev/null +++ b/xilinx/ALU/processeur.ngr @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$0:x0f=(`fgn#kazsrcww*Drzlk~#}|`jdv\w|usmd%{~bdjt^qzwqcjm&rb`d`w/@NV+uthklyxix|!viff?3ukp8!1!QWQG&7&8*J_NGF1d9[WQYNEYFNAH@[AUKLJZEHFZ^YMD@[S028\VRXZ]FT\_A_ESVZ2>^cjVCo==5Wdl]Neoiu^lxxeb`>0:ZgiZKnffx]i}foo18\vr>3QyK@akemc8twidmzyny?>;ya5wi~6>$9&o~i<25CDue:9344967>?8rd:>7?4n0192>"693o0q^=51585>453>:?=6?<7819g53<7280:w^:51585>453>:?=6?<7819uB<<7280:6=u\4;37>3<6;=<89;4=29:3?!b==2.<6<5m1783>7<729qGj7?t$6823>{K9909w)o50:la>75=831vqpsO@By`>g37>=i>qMNM{1CDU}zHI \ No newline at end of file diff --git a/xilinx/ALU/processeur.prj b/xilinx/ALU/processeur.prj new file mode 100644 index 0000000..8bfc086 --- /dev/null +++ b/xilinx/ALU/processeur.prj @@ -0,0 +1,6 @@ +vhdl work "pipeline.vhd" +vhdl work "br.vhd" +vhdl work "bm_instr.vhd" +vhdl work "bm.vhd" +vhdl work "alu.vhd" +vhdl work "processeur.vhd" diff --git a/xilinx/ALU/processeur.stx b/xilinx/ALU/processeur.stx new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ALU/processeur.syr b/xilinx/ALU/processeur.syr new file mode 100644 index 0000000..ceb40e4 --- /dev/null +++ b/xilinx/ALU/processeur.syr @@ -0,0 +1,303 @@ +Release 13.4 - xst O.87xd (lin64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 1.00 secs +Total CPU time to Xst completion: 0.03 secs + +--> +Reading design: processeur.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "processeur.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "processeur" +Output Format : NGC +Target Device : xc6slx16-3-csg324 + +---- Source Options +Top Module Name : processeur +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + +INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL + +========================================================================= +* HDL Parsing * +========================================================================= +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work +Parsing entity
. +Parsing architecture of entity
. +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work +Parsing entity . +Parsing architecture of entity . + +========================================================================= +* HDL Elaboration * +========================================================================= + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity
(architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance of block
are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance of block are unconnected in block . Underlying logic will be removed. +WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance of block are unconnected in block . Underlying logic will be removed. + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd". +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port of the instance is unconnected or connected to loadless signal. + Summary: + no macro. +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block processeur, actual ratio is 0. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Found no macro +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : processeur.ngc + +Primitive and Black Box Usage: +------------------------------ + +Device utilization summary: +--------------------------- + +Selected Device : 6slx16csg324-3 + + +Slice Logic Utilization: + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 0 + Number with an unused Flip Flop: 0 out of 0 + Number with an unused LUT: 0 out of 0 + Number of fully used LUT-FF pairs: 0 out of 0 + Number of unique control sets: 0 + +IO Utilization: + Number of IOs: 2 + Number of bonded IOBs: 0 out of 232 0% + +Specific Feature Utilization: + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -3 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: No path found + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +========================================================================= + + +Total REAL time to Xst completion: 4.00 secs +Total CPU time to Xst completion: 2.94 secs + +--> + + +Total memory usage is 389560 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 8 ( 0 filtered) +Number of infos : 7 ( 0 filtered) + diff --git a/xilinx/ALU/processeur.vhd b/xilinx/ALU/processeur.vhd index 04b95cd..536a9c6 100644 --- a/xilinx/ALU/processeur.vhd +++ b/xilinx/ALU/processeur.vhd @@ -1,271 +1,303 @@ ----------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:52:06 05/04/2021 --- Design Name: --- Module Name: processeur - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; + ---------------------------------------------------------------------------------- + -- Company: + -- Engineer: + -- + -- Create Date: 12:52:06 05/04/2021 + -- Design Name: + -- Module Name: processeur - Behavioral + -- Project Name: + -- Target Devices: + -- Tool versions: + -- Description: + -- + -- Dependencies: + -- + -- Revision: + -- Revision 0.01 - File Created + -- Additional Comments: + -- + ---------------------------------------------------------------------------------- + library IEEE; + use IEEE.STD_LOGIC_1164.ALL; + use IEEE.STD_LOGIC_UNSIGNED.ALL; -use IEEE.NUMERIC_STD.ALL; + use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; + -- Uncomment the following library declaration if using + -- arithmetic functions with Signed or Unsigned values + --use IEEE.NUMERIC_STD.ALL; --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; + -- Uncomment the following library declaration if instantiating + -- any Xilinx primitives in this code. + --library UNISIM; + --use UNISIM.VComponents.all; -entity processeur is - Port ( CLK: in STD_LOGIC ; - RST : in STD_LOGIC); -end processeur; + entity processeur is + Port ( CLK: in STD_LOGIC ; + RST : in STD_LOGIC); + end processeur; -architecture Behavioral of processeur is - COMPONENT bm_instr - PORT( - IN_addr : IN std_logic_vector(7 downto 0); - OUT_data : OUT std_logic_vector(31 downto 0); - CLK : IN std_logic - ); - END COMPONENT; - - COMPONENT pipeline - PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0); - A_IN : in STD_LOGIC_VECTOR (7 downto 0); - B_IN : in STD_LOGIC_VECTOR (7 downto 0); - C_IN : in STD_LOGIC_VECTOR (7 downto 0); - CLK : IN std_logic; - OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); - A_OUT : out STD_LOGIC_VECTOR (7 downto 0); - B_OUT : out STD_LOGIC_VECTOR (7 downto 0); - C_OUT : out STD_LOGIC_VECTOR (7 downto 0) - ); - END COMPONENT; - - COMPONENT br - PORT( - A_addr : IN std_logic_vector(3 downto 0); - B_addr : IN std_logic_vector(3 downto 0); - W_addr : IN std_logic_vector(3 downto 0); - W : IN std_logic; - Data : IN std_logic_vector(7 downto 0); - RST : IN std_logic; - CLK : IN std_logic; - QA : OUT std_logic_vector(7 downto 0); - QB : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - COMPONENT alu - PORT( - A : IN std_logic_vector(7 downto 0); - B : IN std_logic_vector(7 downto 0); - Ctrl_Alu : IN std_logic_vector(2 downto 0); - N : OUT std_logic; - O : OUT std_logic; - Z : OUT std_logic; - C : OUT std_logic; - S : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; - - COMPONENT bm_data - PORT( - IN_addr : IN std_logic_vector(7 downto 0); - IN_data : IN std_logic_vector(7 downto 0); - RW : IN std_logic; - RST : IN std_logic; - CLK : IN std_logic; - OUT_data : OUT std_logic_vector(7 downto 0) - ); - END COMPONENT; + architecture Behavioral of processeur is + COMPONENT bm_instr + PORT( + IN_addr : IN std_logic_vector(7 downto 0); + OUT_data : OUT std_logic_vector(31 downto 0); + CLK : IN std_logic + ); + END COMPONENT; + + COMPONENT pipeline + PORT( OP_IN : in STD_LOGIC_VECTOR (7 downto 0); + A_IN : in STD_LOGIC_VECTOR (7 downto 0); + B_IN : in STD_LOGIC_VECTOR (7 downto 0); + C_IN : in STD_LOGIC_VECTOR (7 downto 0); + CLK : IN std_logic; + EN : in STD_LOGIC; + OP_OUT : out STD_LOGIC_VECTOR (7 downto 0); + A_OUT : out STD_LOGIC_VECTOR (7 downto 0); + B_OUT : out STD_LOGIC_VECTOR (7 downto 0); + C_OUT : out STD_LOGIC_VECTOR (7 downto 0) + ); + END COMPONENT; + + COMPONENT br + PORT( + A_addr : IN std_logic_vector(3 downto 0); + B_addr : IN std_logic_vector(3 downto 0); + W_addr : IN std_logic_vector(3 downto 0); + W : IN std_logic; + Data : IN std_logic_vector(7 downto 0); + RST : IN std_logic; + CLK : IN std_logic; + QA : OUT std_logic_vector(7 downto 0); + QB : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + COMPONENT alu + PORT( + A : IN std_logic_vector(7 downto 0); + B : IN std_logic_vector(7 downto 0); + Ctrl_Alu : IN std_logic_vector(2 downto 0); + N : OUT std_logic; + O : OUT std_logic; + Z : OUT std_logic; + C : OUT std_logic; + S : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + COMPONENT bm_data + PORT( + IN_addr : IN std_logic_vector(7 downto 0); + IN_data : IN std_logic_vector(7 downto 0); + RW : IN std_logic; + RST : IN std_logic; + CLK : IN std_logic; + OUT_data : OUT std_logic_vector(7 downto 0) + ); + END COMPONENT; + + --Inputs + signal IP : std_logic_vector(7 downto 0) := (others => '0'); + signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); + + signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); + signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); + + --Outputs + signal OUT_data : std_logic_vector(31 downto 0); + + signal OP_LIDI_OUT : std_logic_vector(7 downto 0); + signal A_LIDI_OUT : std_logic_vector(7 downto 0); + signal B_LIDI_OUT : std_logic_vector(7 downto 0); + signal C_LIDI_OUT : std_logic_vector(7 downto 0); + + signal OP_DIEX_OUT : std_logic_vector(7 downto 0); + signal A_DIEX_OUT : std_logic_vector(7 downto 0); + signal B_DIEX_OUT : std_logic_vector(7 downto 0); + signal C_DIEX_OUT : std_logic_vector(7 downto 0); + + signal O_ALU_OUT : std_logic; + signal N_ALU_OUT : std_logic; + signal Z_ALU_OUT : std_logic; + signal C_ALU_OUT : std_logic; + + signal A_EXMem_OUT : std_logic_vector(7 downto 0); + signal B_EXMem_OUT : std_logic_vector(7 downto 0); + signal OP_EXMem_OUT : std_logic_vector(7 downto 0); + + signal A_MemRE_OUT : std_logic_vector(7 downto 0); + signal B_MemRE_OUT : std_logic_vector(7 downto 0); + signal OP_MemRE_OUT : std_logic_vector(7 downto 0); + + --AUX + + signal Ctr_ALU_LC : std_logic_vector(2 downto 0); + signal RW_LC : std_logic; + signal addr_dm_MUX : std_logic_vector(7 downto 0); + signal in_dm_MUX : std_logic_vector(7 downto 0); + signal out_dm_MUX : std_logic_vector(7 downto 0); + signal B_EXMem_IN : std_logic_vector(7 downto 0); + signal W_br_LC : std_logic; + signal S_IN_MUX : std_logic_vector(7 downto 0); + signal B_MemRE_IN : std_logic_vector(7 downto 0); + + --alea + signal li_di_r_b : std_logic; + signal li_di_r_c : std_logic; + signal di_ex_w_a : std_logic; + signal ex_mem_w_a : std_logic; + signal alea : std_logic; - --Inputs - signal IP : std_logic_vector(7 downto 0) := (others => '0'); - signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0'); + begin + + -- Instantiate adresse des instructions + addr_instructions: bm_instr PORT MAP ( + IN_addr => IP, + OUT_data => OUT_data, + CLK => CLK + ); - signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); - signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0'); - - --Outputs - signal OUT_data : std_logic_vector(31 downto 0); - - signal OP_LIDI_OUT : std_logic_vector(7 downto 0); - signal A_LIDI_OUT : std_logic_vector(7 downto 0); - signal B_LIDI_OUT : std_logic_vector(7 downto 0); - signal C_LIDI_OUT : std_logic_vector(7 downto 0); - - signal OP_DIEX_OUT : std_logic_vector(7 downto 0); - signal A_DIEX_OUT : std_logic_vector(7 downto 0); - signal B_DIEX_OUT : std_logic_vector(7 downto 0); - signal C_DIEX_OUT : std_logic_vector(7 downto 0); - - signal O_ALU_OUT : std_logic; - signal N_ALU_OUT : std_logic; - signal Z_ALU_OUT : std_logic; - signal C_ALU_OUT : std_logic; - - signal A_EXMem_OUT : std_logic_vector(7 downto 0); - signal B_EXMem_OUT : std_logic_vector(7 downto 0); - signal OP_EXMem_OUT : std_logic_vector(7 downto 0); - - signal A_MemRE_OUT : std_logic_vector(7 downto 0); - signal B_MemRE_OUT : std_logic_vector(7 downto 0); - signal OP_MemRE_OUT : std_logic_vector(7 downto 0); - - --AUX - - signal Ctr_ALU_LC : std_logic_vector(2 downto 0); - signal RW_LC : std_logic; - signal addr_dm_MUX : std_logic_vector(7 downto 0); - signal in_dm_MUX : std_logic_vector(7 downto 0); - signal out_dm_MUX : std_logic_vector(7 downto 0); - signal B_EXMem_IN : std_logic_vector(7 downto 0); - signal W_br_LC : std_logic; - signal S_IN_MUX : std_logic_vector(7 downto 0); - signal B_MemRE_IN : std_logic_vector(7 downto 0); - -begin - - -- Instantiate adresse des instructions - addr_instructions: bm_instr PORT MAP ( - IN_addr => IP, - OUT_data => OUT_data, - CLK => CLK - ); - - -- Instantiate pipeline LI_LD - LI_LD : pipeline PORT MAP ( - OP_IN => OUT_data(31 downto 24), - A_IN => OUT_data(23 downto 16), - B_IN => OUT_data(15 downto 8), - C_IN => OUT_data(7 downto 0), - CLK => CLK, - A_OUT => A_LIDI_OUT, - B_OUT => B_LIDI_OUT, - C_OUT => C_LIDI_OUT, - OP_OUT => OP_LIDI_OUT - ); - W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else - '0'; - -- Instanciate banc de registre - banc_registres : br PORT MAP ( - A_addr => B_LIDI_OUT(3 downto 0), - B_addr => C_LIDI_OUT(3 downto 0), - W_addr => A_MemRE_OUT(3 downto 0), - W => W_br_LC, --ATTENTION LC - Data => B_MemRE_OUT, - RST => RST, - CLK => CLK, - QA => QA_IN_MUX, - QB => C_DIEX_IN - ); - - B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ; - - - -- Instantiate pipeline DI_EX - DI_EX : pipeline PORT MAP ( - OP_IN => OP_LIDI_OUT, - A_IN => A_LIDI_OUT, - B_IN => B_DIEX_IN, - C_IN => C_DIEX_IN, - CLK => CLK, - A_OUT => A_DIEX_OUT, - B_OUT => B_DIEX_OUT, - C_OUT => C_DIEX_OUT, - OP_OUT => OP_DIEX_OUT - ); - - Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else - "010" when OP_DIEX_OUT = x"03" else - "011" when OP_DIEX_OUT = x"02" else - "000"; - - -- Instantiate alu - UAL : alu PORT MAP ( - A => B_DIEX_OUT, - B => C_DIEX_OUT, - Ctrl_Alu =>Ctr_AlU_LC, - N => N_ALU_OUT, - O => O_ALU_OUT, - Z => Z_ALU_OUT, - C => C_ALU_OUT, - S => S_IN_MUX - ); - - B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else - B_DIEX_OUT ; + -- Instantiate pipeline LI_LD + LI_LD : pipeline PORT MAP ( + OP_IN => OUT_data(31 downto 24), + A_IN => OUT_data(23 downto 16), + B_IN => OUT_data(15 downto 8), + C_IN => OUT_data(7 downto 0), + CLK => CLK, + EN => alea, + A_OUT => A_LIDI_OUT, + B_OUT => B_LIDI_OUT, + C_OUT => C_LIDI_OUT, + OP_OUT => OP_LIDI_OUT + ); + W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else + '0'; - - -- Instantiate pipeline EX_Mem - EX_Mem : pipeline PORT MAP ( - OP_IN => OP_DIEX_OUT, - A_IN => A_DIEX_OUT, - B_IN => B_EXMem_IN, - C_IN => x"00", - CLK => CLK, - A_OUT => A_EXMem_OUT, - B_OUT => B_EXMem_OUT, - C_OUT => open, - OP_OUT => OP_EXMem_OUT - ); - - RW_LC <= '0' when OP_EXMem_OUT = x"08" else - '1'; - addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else - A_EXMem_OUT; - in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; - B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else - B_EXMem_OUT; - -- Instantiate banc de données - data_memory: bm_data PORT MAP ( - IN_addr => addr_dm_MUX, - IN_data => B_MemRE_IN, - RW => RW_LC, - RST => RST, - CLK => CLK, - OUT_data => out_dm_MUX - ); + --alea LI_DI + li_di_r_b <= '1' when OUT_data(31 downto 24) = x"05" or OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" or OUT_data(31 downto 24) = x"08" + else '0'; + li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" + else '0'; + -- Instanciate banc de registre + banc_registres : br PORT MAP ( + A_addr => B_LIDI_OUT(3 downto 0), + B_addr => C_LIDI_OUT(3 downto 0), + W_addr => A_MemRE_OUT(3 downto 0), + W => W_br_LC, --ATTENTION LC + Data => B_MemRE_OUT, + RST => RST, + CLK => CLK, + QA => QA_IN_MUX, + QB => C_DIEX_IN + ); + + B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ; + + + -- Instantiate pipeline DI_EX + DI_EX : pipeline PORT MAP ( + OP_IN => OP_LIDI_OUT, + A_IN => A_LIDI_OUT, + B_IN => B_DIEX_IN, + C_IN => C_DIEX_IN, + CLK => CLK, + EN => '1', + A_OUT => A_DIEX_OUT, + B_OUT => B_DIEX_OUT, + C_OUT => C_DIEX_OUT, + OP_OUT => OP_DIEX_OUT + ); + + Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else + "010" when OP_DIEX_OUT = x"03" else + "011" when OP_DIEX_OUT = x"02" else + "000"; + -- alea DI_EX + di_ex_w_a <= '0' when OP_LIDI_OUT = x"08" or OP_LIDI_OUT = x"00" + else '1'; + -- Instantiate alu + UAL : alu PORT MAP ( + A => B_DIEX_OUT, + B => C_DIEX_OUT, + Ctrl_Alu =>Ctr_AlU_LC, + N => N_ALU_OUT, + O => O_ALU_OUT, + Z => Z_ALU_OUT, + C => C_ALU_OUT, + S => S_IN_MUX + ); + + B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else + B_DIEX_OUT ; + + + -- Instantiate pipeline EX_Mem + EX_Mem : pipeline PORT MAP ( + OP_IN => OP_DIEX_OUT, + A_IN => A_DIEX_OUT, + B_IN => B_EXMem_IN, + C_IN => x"00", + CLK => CLK, + EN => '1', + A_OUT => A_EXMem_OUT, + B_OUT => B_EXMem_OUT, + C_OUT => open, + OP_OUT => OP_EXMem_OUT + ); + + RW_LC <= '0' when OP_EXMem_OUT = x"08" else + '1'; + addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else + A_EXMem_OUT; + in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; + B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else + B_EXMem_OUT; + + -- alea ex_mem + ex_mem_w_a <= '0' when OP_DIEX_OUT = x"08" or OP_DIEX_OUT = x"00" + else '1'; + -- Instantiate banc de données + data_memory: bm_data PORT MAP ( + IN_addr => addr_dm_MUX, + IN_data => in_dm_MUX, + RW => RW_LC, + RST => RST, + CLK => CLK, + OUT_data => out_dm_MUX + ); + + -- Instantiate pipeline Mem_RE + Mem_RE : pipeline PORT MAP ( + OP_IN => OP_EXMem_OUT, + A_IN => A_EXMem_OUT, + B_IN => B_MemRE_IN, + C_IN => x"00", + CLK => CLK, + EN => '1', + A_OUT => A_MemRE_OUT, + B_OUT => B_MemRE_OUT, + C_OUT => open, + OP_OUT => OP_MemRE_OUT + ); + + alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or + (li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or + (li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or + (li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else + '1'; - -- Instantiate pipeline Mem_RE - Mem_RE : pipeline PORT MAP ( - OP_IN => OP_EXMem_OUT, - A_IN => A_EXMem_OUT, - B_IN => B_EXMem_OUT, - C_IN => x"00", - CLK => CLK, - A_OUT => A_MemRE_OUT, - B_OUT => B_MemRE_OUT, - C_OUT => open, - OP_OUT => OP_MemRE_OUT - ); - process + process begin wait until rising_edge(CLK); if rst = '0' then IP <= x"00"; else - IP <= IP + "00000001"; + if alea = '1' then + IP <= IP + "00000001"; + end if; end if; end process; - -end Behavioral; - + + end Behavioral; diff --git a/xilinx/ALU/processeur.xst b/xilinx/ALU/processeur.xst new file mode 100644 index 0000000..b644f1c --- /dev/null +++ b/xilinx/ALU/processeur.xst @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn processeur.prj +-ofn processeur +-ofmt NGC +-p xc6slx16-3-csg324 +-top processeur +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/ALU/processeur_envsettings.html b/xilinx/ALU/processeur_envsettings.html new file mode 100644 index 0000000..2d84867 --- /dev/null +++ b/xilinx/ALU/processeur_envsettings.html @@ -0,0 +1,404 @@ +Xilinx System Settings Report + +

System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:
/usr/local/insa/lib:
$LD_LIBRARY_PATH		/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:
/usr/local/insa/lib:
$LD_LIBRARY_PATH		< data not available >< data not available >
PATH/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:
/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:
/usr/local/insa/shared/opam/system/bin:
/usr/local/insa/lustre-v4-III-dc-linux64/bin:
/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:
/usr/local/insa/anaconda/bin:
/usr/local/insa/bin:
/usr/local/insa/sbin:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/usr/local/insa/tina/bin:
/snap/bin		/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:
/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:
/usr/local/insa/shared/opam/system/bin:
/usr/local/insa/lustre-v4-III-dc-linux64/bin:
/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:
/usr/local/insa/anaconda/bin:
/usr/local/insa/bin:
/usr/local/insa/sbin:
/usr/local/sbin:
/usr/local/bin:
/usr/sbin:
/usr/bin:
/sbin:
/bin:
/usr/games:
/usr/local/games:
/usr/local/insa/tina/bin:
/snap/bin		< data not available >< data not available >
XILINX/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/< data not available >< data not available >
XILINXD_LICENSE_FILE/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn processeur.prj 
-ofn processeur 
-ofmt NGCNGC
-p xc6slx16-3-csg324 
-top processeur 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc6slx16-csg324-3None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4277.214 MHzIntel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4276.892 MHz<  data not available  ><  data not available  >
Hostinsa-11291insa-11291<  data not available  ><  data not available  >
OS NameUbuntuUbuntu<  data not available  ><  data not available  >
OS ReleaseUbuntu 18.04.5 LTSUbuntu 18.04.5 LTS<  data not available  ><  data not available  >
+ \ No newline at end of file diff --git a/xilinx/ALU/processeur_map.map b/xilinx/ALU/processeur_map.map new file mode 100644 index 0000000..0f9c60d --- /dev/null +++ b/xilinx/ALU/processeur_map.map @@ -0,0 +1,23 @@ +Release 13.4 Map O.87xd (lin64) +Xilinx Map Application Log File for Design 'processeur' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Tue May 18 16:15:07 2021 + +ERROR:Map:116 - The design is empty. No processing will be done. +ERROR:Map:52 - Problem encountered processing RPMs. + + + +Design Summary +-------------- +Number of errors : 2 +Number of warnings : 0 diff --git a/xilinx/ALU/processeur_map.mrp b/xilinx/ALU/processeur_map.mrp new file mode 100644 index 0000000..7bc54ad --- /dev/null +++ b/xilinx/ALU/processeur_map.mrp @@ -0,0 +1,31 @@ +Release 13.4 Map O.87xd (lin64) +Xilinx Mapping Report File for Design 'processeur' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf +Target Device : xc6slx16 +Target Package : csg324 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Tue May 18 16:15:07 2021 + +Design Summary +-------------- +Number of errors : 2 +Number of warnings : 0 + +Section 1 - Errors +------------------ +ERROR:Map:116 - The design is empty. No processing will be done. +ERROR:Map:52 - Problem encountered processing RPMs. + + + +Section 2 - Warnings +-------------------- + +Section 3 - Informational +------------------------- diff --git a/xilinx/ALU/processeur_ngdbuild.xrpt b/xilinx/ALU/processeur_ngdbuild.xrpt new file mode 100644 index 0000000..c2d89e9 --- /dev/null +++ b/xilinx/ALU/processeur_ngdbuild.xrpt @@ -0,0 +1,67 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + +
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+ + + + diff --git a/xilinx/ALU/processeur_summary.html b/xilinx/ALU/processeur_summary.html index 23acf3d..e983e48 100644 --- a/xilinx/ALU/processeur_summary.html +++ b/xilinx/ALU/processeur_summary.html @@ -2,7 +2,7 @@ - + @@ -13,18 +13,20 @@ - + - + - + @@ -41,7 +43,10 @@ - + @@ -49,7 +54,9 @@ - + 
processeur Project Status
processeur Project Status (05/18/2021 - 16:15:09)
Project File: ALU.xiseModule Name: processeur Implementation State:NewMapped (Failed)
Target Device: xc6slx16-3csg324
  • Errors:
  +X +2 Errors (2 new)
Product Version:ISE 13.4
  • Warnings:
 9 Warnings (9 new)
Design Goal:
Environment:  + +System Settings +
  • Final Timing Score:
   
+ +
Device Utilization Summary [-]
@@ -61,9 +68,9 @@ Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos -Synthesis Report      -Translation Report      -Map Report      +Synthesis ReportCurrentmar. mai 18 16:14:40 202108 Warnings (8 new)7 Infos (7 new) +Translation ReportCurrentmar. mai 18 16:15:06 202101 Warning (1 new)0 +Map ReportCurrentmar. mai 18 16:15:09 2021X 2 Errors (2 new)00 Place and Route Report      Power Report      Post-PAR Static Timing Report      @@ -72,9 +79,9 @@  
- +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of Datelun. mai 10 10:45:43 2021
ISIM Simulator LogOut of Datemar. mai 18 16:15:36 2021
-
Date Generated: 05/10/2021 - 10:47:06
+
Date Generated: 05/18/2021 - 16:16:17
\ No newline at end of file diff --git a/xilinx/ALU/processeur_xst.xrpt b/xilinx/ALU/processeur_xst.xrpt new file mode 100644 index 0000000..97a8453 --- /dev/null +++ b/xilinx/ALU/processeur_xst.xrpt @@ -0,0 +1,129 @@ + + + + + + +
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