Foussats Morgane 4 months ago
parent
commit
db6969e20e
70 changed files with 3378 additions and 635 deletions
  1. 117
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      xilinx/ALU/ALU.gise
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      xilinx/ALU/ALU.xise
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      xilinx/ALU/_ngo/netlist.lst
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      xilinx/ALU/_xmsgs/xst.xmsgs
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      xilinx/ALU/bm_instr.vhd
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      xilinx/ALU/bm_instr_isim_beh.exe
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      xilinx/ALU/fuse.log
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      xilinx/ALU/iseconfig/ALU.projectmgr
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      xilinx/ALU/iseconfig/processeur.xreport
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      xilinx/ALU/isim.log
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      xilinx/ALU/isim/isim_usage_statistics.html
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      xilinx/ALU/isim/lockfile1
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      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
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      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
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      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId.dat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/netId1.dat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/process_test_isim_beh.exe
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/tmp_save/_1
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.didat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.lin64.o
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3998322972_3212880686.didat
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.c
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      xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_4150868852_3212880686.lin64.o
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      xilinx/ALU/isim/work/alu.vdb
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      xilinx/ALU/isim/work/bm_data.vdb
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      xilinx/ALU/isim/work/bm_instr.vdb
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      xilinx/ALU/isim/work/br.vdb
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      xilinx/ALU/isim/work/pipeline.vdb
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      xilinx/ALU/isim/work/process_test.vdb
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      xilinx/ALU/isim/work/processeur.vdb
  47. 13
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      xilinx/ALU/pipeline.vhd
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      xilinx/ALU/process_test_isim_beh.wdb
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      xilinx/ALU/process_test_isim_beh1.wdb
  50. 42
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      xilinx/ALU/processeur.bld
  51. 3
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      xilinx/ALU/processeur.cmd_log
  52. 1
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      xilinx/ALU/processeur.lso
  53. 3
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      xilinx/ALU/processeur.ngc
  54. 3
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      xilinx/ALU/processeur.ngd
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      xilinx/ALU/processeur.ngr
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      xilinx/ALU/processeur.prj
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      xilinx/ALU/processeur.syr
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      xilinx/ALU/processeur.vhd
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      xilinx/ALU/processeur_map.map
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      xilinx/ALU/processeur_map.mrp
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      xilinx/ALU/processeur_ngdbuild.xrpt
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      xilinx/ALU/processeur_summary.html
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      xilinx/ALU/processeur_xst.xrpt
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      xilinx/ALU/webtalk_pn.xml
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      xilinx/ALU/xst/work/work.vdbx

+ 117
- 6
xilinx/ALU/ALU.gise View File

@@ -22,10 +22,15 @@
22 22
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23 23
 
24 24
   <files xmlns="http://www.xilinx.com/XMLSchema">
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+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
25 29
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
26 30
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
27 31
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_isim_beh.exe"/>
28 32
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_data_test_isim_beh.exe"/>
33
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_isim_beh.exe"/>
29 34
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
30 35
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31 36
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@@ -37,7 +42,26 @@
37 42
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38 43
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39 44
     <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="process_test_isim_beh.wdb"/>
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+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="processeur_beh.prj"/>
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+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="processeur_map.map" xil_pn:subbranch="Map"/>
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+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="processeur_ngdbuild.xrpt"/>
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+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
40 62
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
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+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
41 65
   </files>
42 66
 
43 67
   <transforms xmlns="http://www.xilinx.com/XMLSchema">
@@ -49,9 +73,13 @@
49 73
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50 74
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51 75
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52
-    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1620641821">
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+    <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1621346572">
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       <status xil_pn:value="SuccessfullyRun"/>
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       <status xil_pn:value="ReadyToRun"/>
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+      <status xil_pn:value="OutOfDateForInputs"/>
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+      <status xil_pn:value="OutOfDateForOutputs"/>
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+      <status xil_pn:value="InputChanged"/>
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+      <status xil_pn:value="OutputChanged"/>
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       <outfile xil_pn:name="alu.vhd"/>
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       <outfile xil_pn:name="alu_test.vhd"/>
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@@ -64,11 +92,11 @@
64 92
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65 93
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66 94
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67
-    <transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1620632845">
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+    <transform xil_pn:end_ts="1621342541" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6971558793754694324" xil_pn:start_ts="1621342541">
68 96
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70 98
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-    <transform xil_pn:end_ts="1620632845" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1620632845">
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+    <transform xil_pn:end_ts="1621342541" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7480952545073688782" xil_pn:start_ts="1621342541">
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@@ -76,9 +104,14 @@
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-    <transform xil_pn:end_ts="1620641821" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1620641821">
107
+    <transform xil_pn:end_ts="1621346572" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1621346572">
80 108
       <status xil_pn:value="SuccessfullyRun"/>
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       <status xil_pn:value="ReadyToRun"/>
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+      <status xil_pn:value="OutOfDateForInputs"/>
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+      <status xil_pn:value="OutOfDateForPredecessor"/>
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+      <status xil_pn:value="OutOfDateForOutputs"/>
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+      <status xil_pn:value="InputChanged"/>
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+      <status xil_pn:value="OutputChanged"/>
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       <outfile xil_pn:name="alu.vhd"/>
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       <outfile xil_pn:name="alu_test.vhd"/>
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@@ -91,9 +124,14 @@
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-    <transform xil_pn:end_ts="1620641822" xil_pn:in_ck="1065830448803121098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-8598345349839697464" xil_pn:start_ts="1620641821">
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95 128
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+      <status xil_pn:value="OutOfDateForInputs"/>
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@@ -101,13 +139,86 @@
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+      <outfile xil_pn:name="processeur.bld"/>
211
+      <outfile xil_pn:name="processeur.ngd"/>
212
+      <outfile xil_pn:name="processeur_ngdbuild.xrpt"/>
213
+    </transform>
214
+    <transform xil_pn:end_ts="1621347309" xil_pn:in_ck="-3700998983167034414" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1621347306">
215
+      <status xil_pn:value="FailedRun"/>
216
+      <status xil_pn:value="ReadyToRun"/>
217
+      <status xil_pn:value="OutOfDateForPredecessor"/>
218
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
219
+      <outfile xil_pn:name="processeur_map.map"/>
220
+      <outfile xil_pn:name="processeur_map.mrp"/>
221
+    </transform>
111 222
   </transforms>
112 223
 
113 224
 </generated_project>

+ 6
- 6
xilinx/ALU/ALU.xise View File

@@ -17,7 +17,7 @@
17 17
   <files>
18 18
     <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
19 19
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
20
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
20
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
21 21
     </file>
22 22
     <file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
23 23
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -27,7 +27,7 @@
27 27
     </file>
28 28
     <file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
29 29
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
30
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
30
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
31 31
     </file>
32 32
     <file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
33 33
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -37,11 +37,11 @@
37 37
     </file>
38 38
     <file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
39 39
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
40
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
40
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
41 41
     </file>
42 42
     <file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
43 43
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
44
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
44
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
45 45
     </file>
46 46
     <file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
47 47
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -57,11 +57,11 @@
57 57
     </file>
58 58
     <file xil_pn:name="pipeline.vhd" xil_pn:type="FILE_VHDL">
59 59
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
60
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
60
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
61 61
     </file>
62 62
     <file xil_pn:name="processeur.vhd" xil_pn:type="FILE_VHDL">
63 63
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
64
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
64
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
65 65
     </file>
66 66
     <file xil_pn:name="process_test.vhd" xil_pn:type="FILE_VHDL">
67 67
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>

+ 3
- 0
xilinx/ALU/_ngo/netlist.lst View File

@@ -0,0 +1,3 @@
1
+/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280
2
+/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc 1621347280
3
+OK

+ 15
- 0
xilinx/ALU/_xmsgs/map.xmsgs View File

@@ -0,0 +1,15 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- IMPORTANT: This is an internal file that has been generated
3
+     by the Xilinx ISE software.  Any direct editing or
4
+     changes made to this file may result in unpredictable
5
+     behavior or data corruption.  It is strongly advised that
6
+     users do not edit the contents of this file. -->
7
+<messages>
8
+<msg type="error" file="Map" num="116" delta="new" >The design is empty.  No processing will be done.
9
+</msg>
10
+
11
+<msg type="user_fatal" file="Map" num="52" delta="new" >Problem encountered processing RPMs.
12
+</msg>
13
+
14
+</messages>
15
+

+ 12
- 0
xilinx/ALU/_xmsgs/ngdbuild.xmsgs View File

@@ -0,0 +1,12 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- IMPORTANT: This is an internal file that has been generated
3
+     by the Xilinx ISE software.  Any direct editing or
4
+     changes made to this file may result in unpredictable
5
+     behavior or data corruption.  It is strongly advised that
6
+     users do not edit the contents of this file. -->
7
+<messages>
8
+<msg type="warning" file="NgdBuild" num="578" delta="new" >Design contains no instances.
9
+</msg>
10
+
11
+</messages>
12
+

+ 1
- 1
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File

@@ -8,7 +8,7 @@
8 8
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9 9
 
10 10
 <messages>
11
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd&quot; into library work</arg>
11
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
12 12
 </msg>
13 13
 
14 14
 </messages>

+ 54
- 0
xilinx/ALU/_xmsgs/xst.xmsgs View File

@@ -0,0 +1,54 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- IMPORTANT: This is an internal file that has been generated
3
+     by the Xilinx ISE software.  Any direct editing or
4
+     changes made to this file may result in unpredictable
5
+     behavior or data corruption.  It is strongly advised that
6
+     users do not edit the contents of this file. -->
7
+<messages>
8
+<msg type="info" file="Xst" num="0" delta="new" >Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
9
+</msg>
10
+
11
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">156</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">addr_instructions</arg>&gt; of block &lt;<arg fmt="%s" index="4">bm_instr</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
12
+</msg>
13
+
14
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">163</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">LI_LD</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
15
+</msg>
16
+
17
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">184</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">banc_registres</arg>&gt; of block &lt;<arg fmt="%s" index="4">br</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
18
+</msg>
19
+
20
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">200</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">DI_EX</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
21
+</msg>
22
+
23
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">221</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">UAL</arg>&gt; of block &lt;<arg fmt="%s" index="4">alu</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
24
+</msg>
25
+
26
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">237</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">EX_Mem</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
27
+</msg>
28
+
29
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">262</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">data_memory</arg>&gt; of block &lt;<arg fmt="%s" index="4">bm_data</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
30
+</msg>
31
+
32
+<msg type="warning" file="Xst" num="2972" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%d" index="2">272</arg>. All outputs of instance &lt;<arg fmt="%s" index="3">Mem_RE</arg>&gt; of block &lt;<arg fmt="%s" index="4">pipeline</arg>&gt; are unconnected in block &lt;<arg fmt="%s" index="5">processeur</arg>&gt;. Underlying logic will be removed.
33
+</msg>
34
+
35
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">N</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
36
+</msg>
37
+
38
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">O</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
39
+</msg>
40
+
41
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">Z</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
42
+</msg>
43
+
44
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">221</arg>: Output port &lt;<arg fmt="%s" index="3">C</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">UAL</arg>&gt; is unconnected or connected to loadless signal.
45
+</msg>
46
+
47
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">237</arg>: Output port &lt;<arg fmt="%s" index="3">C_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">EX_Mem</arg>&gt; is unconnected or connected to loadless signal.
48
+</msg>
49
+
50
+<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd</arg>&quot; line <arg fmt="%s" index="2">272</arg>: Output port &lt;<arg fmt="%s" index="3">C_OUT</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">Mem_RE</arg>&gt; is unconnected or connected to loadless signal.
51
+</msg>
52
+
53
+</messages>
54
+

+ 26
- 2
xilinx/ALU/bm_instr.vhd View File

@@ -34,12 +34,36 @@ architecture Behavioral of bm_instr is
34 34
 type mem is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
35 35
 -- instruction "00000110 00000001 00000110 00000000"
36 36
 --test afc
37
---signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
37
+signal instr_memory: mem := (1 => "00000110000000010000001000000000", others =>"00000000000000000000000000000000");
38 38
 
39 39
 --test afc cop
40
-signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
40
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
41
+--test afc cop alea
42
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 =>"00000101000000100000000100000000", others =>"00000000000000000000000000000000");
41 43
 --test add
42 44
 --signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
45
+--test add alea
46
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 3 =>"00000001000000110000000100000010", others =>"00000000000000000000000000000000");
47
+--test sub
48
+
49
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000011000000110000000100000010", others =>"00000000000000000000000000000000");
50
+
51
+--test mul
52
+
53
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00000110000000100000000100000000", 10 =>"00000010000000110000000100000010", others =>"00000000000000000000000000000000");
54
+
55
+--test store
56
+
57
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 10 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
58
+
59
+--test store alea
60
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 2 => "00001000000000000000000100000000", others =>"00000000000000000000000000000000");
61
+
62
+--test load
63
+
64
+--signal instr_memory: mem := (1 => "00000110000000010000011000000000", 6 => "00001000000000000000000100000000", 15 => "00000111000000110000000000000000", others =>"00000000000000000000000000000000");
65
+
66
+
43 67
 begin
44 68
 
45 69
 		OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));

BIN
xilinx/ALU/bm_instr_isim_beh.exe View File


+ 4
- 4
xilinx/ALU/fuse.log View File

@@ -13,7 +13,7 @@ Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU
13 13
 Starting static elaboration
14 14
 Completed static elaboration
15 15
 Fuse Memory Usage: 98520 KB
16
-Fuse CPU Usage: 760 ms
16
+Fuse CPU Usage: 840 ms
17 17
 Compiling package standard
18 18
 Compiling package std_logic_1164
19 19
 Compiling package std_logic_arith
@@ -30,6 +30,6 @@ Time Resolution for simulation is 1ps.
30 30
 Waiting for 1 sub-compilation(s) to finish...
31 31
 Compiled 18 VHDL Units
32 32
 Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test_isim_beh.exe
33
-Fuse Memory Usage: 1723208 KB
34
-Fuse CPU Usage: 850 ms
35
-GCC CPU Usage: 120 ms
33
+Fuse Memory Usage: 1723384 KB
34
+Fuse CPU Usage: 980 ms
35
+GCC CPU Usage: 110 ms

+ 8
- 8
xilinx/ALU/iseconfig/ALU.projectmgr View File

@@ -23,13 +23,13 @@
23 23
          <ClosedNode>Design Utilities</ClosedNode>
24 24
       </ClosedNodes>
25 25
       <SelectedItems>
26
-         <SelectedItem></SelectedItem>
26
+         <SelectedItem/>
27 27
       </SelectedItems>
28 28
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
29 29
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
30 30
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
31 31
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
32
-      <CurrentItem></CurrentItem>
32
+      <CurrentItem/>
33 33
    </ItemView>
34 34
    <ItemView guiview="File" >
35 35
       <ClosedNodes>
@@ -81,13 +81,13 @@
81 81
          <ClosedNode>/br_test - behavior |home|foussats|Bureau|projet_system|projet_systeme|xilinx|ALU|br_test.vhd</ClosedNode>
82 82
       </ClosedNodes>
83 83
       <SelectedItems>
84
-         <SelectedItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</SelectedItem>
84
+         <SelectedItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</SelectedItem>
85 85
       </SelectedItems>
86 86
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
87 87
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
88
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001e4000000020000000000000000000000000200000064ffffffff000000810000000300000002000001e40000000100000003000000000000000100000003</ViewHeaderState>
88
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001f8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001f80000000100000003000000000000000100000003</ViewHeaderState>
89 89
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
90
-      <CurrentItem>processeur - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd)</CurrentItem>
90
+      <CurrentItem>process_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/process_test.vhd)</CurrentItem>
91 91
    </ItemView>
92 92
    <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
93 93
       <ClosedNodes>
@@ -107,13 +107,13 @@
107 107
          <ClosedNodesVersion>1</ClosedNodesVersion>
108 108
       </ClosedNodes>
109 109
       <SelectedItems>
110
-         <SelectedItem>Simulate Behavioral Model</SelectedItem>
110
+         <SelectedItem></SelectedItem>
111 111
       </SelectedItems>
112 112
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
113 113
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
114 114
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000176000000010000000100000000000000000000000064ffffffff000000810000000000000001000001760000000100000000</ViewHeaderState>
115 115
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
116
-      <CurrentItem>Simulate Behavioral Model</CurrentItem>
116
+      <CurrentItem></CurrentItem>
117 117
    </ItemView>
118 118
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
119 119
       <ClosedNodes>
@@ -130,5 +130,5 @@
130 130
       <CurrentItem/>
131 131
    </ItemView>
132 132
    <SourceProcessView>000000ff0000000000000002000001a6000000db01000000040100000002</SourceProcessView>
133
-   <CurrentView>Behavioral Simulation</CurrentView>
133
+   <CurrentView>Implementation</CurrentView>
134 134
 </Project>

+ 2
- 2
xilinx/ALU/iseconfig/processeur.xreport View File

@@ -1,11 +1,11 @@
1 1
 <?xml version='1.0' encoding='UTF-8'?>
2 2
 <report-views version="2.0" >
3 3
  <header>
4
-  <DateModified>2021-05-10T10:47:06</DateModified>
4
+  <DateModified>2021-05-18T16:14:30</DateModified>
5 5
   <ModuleName>processeur</ModuleName>
6 6
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/processeur.xreport</SavedFilePath>
8
-  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
8
+  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
9 9
   <DateInitialized>2021-05-10T09:34:56</DateInitialized>
10 10
   <EnableMessageFiltering>false</EnableMessageFiltering>
11 11
  </header>

+ 70
- 0
xilinx/ALU/isim.log View File

@@ -45,4 +45,74 @@ at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_IN
45 45
 at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
46 46
 at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
47 47
 at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
48
+ISim O.87xd (signature 0x8ddf5b5d)
49
+WARNING: A WEBPACK license was found.
50
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
51
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
52
+This is a Lite version of ISim.
53
+# run 1000 ns
54
+Simulator is doing circuit initialization process.
55
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
56
+Finished circuit initialization process.
57
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
58
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
59
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
60
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
61
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
62
+ISim O.87xd (signature 0x8ddf5b5d)
63
+WARNING: A WEBPACK license was found.
64
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
65
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
66
+This is a Lite version of ISim.
67
+# run 1000 ns
68
+Simulator is doing circuit initialization process.
69
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
70
+Finished circuit initialization process.
71
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
72
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
73
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
74
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
75
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
76
+ISim O.87xd (signature 0x8ddf5b5d)
77
+WARNING: A WEBPACK license was found.
78
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
79
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
80
+This is a Lite version of ISim.
81
+# run 1000 ns
82
+Simulator is doing circuit initialization process.
83
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
84
+Finished circuit initialization process.
85
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
86
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
87
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
88
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
89
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
90
+ISim O.87xd (signature 0x8ddf5b5d)
91
+WARNING: A WEBPACK license was found.
92
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
93
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
94
+This is a Lite version of ISim.
95
+# run 1000 ns
96
+Simulator is doing circuit initialization process.
97
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
98
+Finished circuit initialization process.
99
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
100
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
101
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
102
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
103
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
104
+ISim O.87xd (signature 0x8ddf5b5d)
105
+WARNING: A WEBPACK license was found.
106
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
107
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
108
+This is a Lite version of ISim.
109
+# run 1000 ns
110
+Simulator is doing circuit initialization process.
111
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
112
+Finished circuit initialization process.
113
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
114
+at 0 ps, Instance /process_test/uut/banc_registres/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
115
+at 5 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
116
+at 15 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
117
+at 25 ns(1), Instance /process_test/uut/data_memory/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
48 118
 # exit 0

+ 5
- 5
xilinx/ALU/isim/isim_usage_statistics.html View File

@@ -2,14 +2,14 @@
2 2
 <xtag-section name="ISimStatistics">
3 3
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
4 4
 <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
5
-<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>850 ms, 1723208 KB</xtag-isim-property-value></TD></TR>
5
+<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 1723384 KB</xtag-isim-property-value></TD></TR>
6 6
 
7
-<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>109</xtag-isim-property-value></TD></TR>
8
-<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10695</xtag-isim-property-value></TD></TR>
7
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>121</xtag-isim-property-value></TD></TR>
8
+<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>10703</xtag-isim-property-value></TD></TR>
9 9
 <TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>14</xtag-isim-property-value></TD></TR>
10
-<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>31</xtag-isim-property-value></TD></TR>
10
+<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>36</xtag-isim-property-value></TD></TR>
11 11
 <TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
12
-<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 264146 KB</xtag-isim-property-value></TD></TR>
12
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 264171 KB</xtag-isim-property-value></TD></TR>
13 13
 <TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
14 14
 <TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
15 15
 </xtag-section>

+ 0
- 0
xilinx/ALU/isim/lockfile1 View File


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+ 12
- 12
xilinx/ALU/isim/process_test_isim_beh.exe.sim/isimkernel.log View File

@@ -2,28 +2,28 @@ Command line:
2 2
    process_test_isim_beh.exe
3 3
      -simmode  gui
4 4
      -simrunnum  0
5
-     -socket  43981
5
+     -socket  37953
6 6
 
7
-Mon May 10 12:31:07 2021
7
+Tue May 18 16:16:44 2021
8 8
 
9 9
 
10 10
  Elaboration Time: 0.01 sec
11 11
 
12
- Current Memory Usage: 189.698 Meg
12
+ Current Memory Usage: 189.723 Meg
13 13
 
14
- Total Signals          : 109
15
- Total Nets             : 10695
16
- Total Signal Drivers   : 44
14
+ Total Signals          : 121
15
+ Total Nets             : 10703
16
+ Total Signal Drivers   : 49
17 17
  Total Blocks           : 14
18 18
  Total Primitive Blocks : 12
19
- Total Processes        : 31
19
+ Total Processes        : 36
20 20
  Total Traceable Variables  : 16
21
- Total Scalar Nets and Variables : 11197
22
-Total Line Count : 66
21
+ Total Scalar Nets and Variables : 11205
22
+Total Line Count : 92
23 23
 
24
- Total Simulation Time: 0.04 sec
24
+ Total Simulation Time: 0.03 sec
25 25
 
26
- Current Memory Usage: 265.2 Meg
26
+ Current Memory Usage: 265.224 Meg
27 27
 
28
-Mon May 10 12:32:41 2021
28
+Tue May 18 16:20:51 2021
29 29
 

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+ 1
- 1
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c View File

@@ -45,7 +45,7 @@ static void work_a_1802466774_3212880686_p_0(char *t0)
45 45
     char *t14;
46 46
     char *t15;
47 47
 
48
-LAB0:    xsi_set_current_line(45, ng0);
48
+LAB0:    xsi_set_current_line(67, ng0);
49 49
 
50 50
 LAB3:    t1 = (t0 + 1512U);
51 51
     t2 = *((char **)t1);

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+ 89
- 40
xilinx/ALU/isim/process_test_isim_beh.exe.sim/work/a_3650175700_3212880686.c View File

@@ -34,76 +34,125 @@ static void work_a_3650175700_3212880686_p_0(char *t0)
34 34
     char *t3;
35 35
     unsigned char t4;
36 36
     char *t5;
37
-    char *t6;
37
+    unsigned char t6;
38 38
     char *t7;
39 39
     char *t8;
40
+    char *t9;
41
+    char *t10;
40 42
 
41
-LAB0:    t1 = (t0 + 3464U);
43
+LAB0:    t1 = (t0 + 3624U);
42 44
     t2 = *((char **)t1);
43 45
     if (t2 == 0)
44 46
         goto LAB2;
45 47
 
46 48
 LAB3:    goto *t2;
47 49
 
48
-LAB2:    xsi_set_current_line(49, ng0);
50
+LAB2:    xsi_set_current_line(50, ng0);
49 51
 
50
-LAB6:    t2 = (t0 + 3784);
52
+LAB6:    t2 = (t0 + 3944);
51 53
     *((int *)t2) = 1;
52 54
     *((char **)t1) = &&LAB7;
53 55
 
54 56
 LAB1:    return;
55
-LAB4:    t5 = (t0 + 3784);
57
+LAB4:    t5 = (t0 + 3944);
56 58
     *((int *)t5) = 0;
57
-    xsi_set_current_line(50, ng0);
58
-    t2 = (t0 + 1032U);
59
+    xsi_set_current_line(51, ng0);
60
+    t2 = (t0 + 1832U);
59 61
     t3 = *((char **)t2);
60
-    t2 = (t0 + 3864);
61
-    t5 = (t2 + 56U);
62
-    t6 = *((char **)t5);
63
-    t7 = (t6 + 56U);
62
+    t4 = *((unsigned char *)t3);
63
+    t6 = (t4 == (unsigned char)3);
64
+    if (t6 != 0)
65
+        goto LAB8;
66
+
67
+LAB10:    xsi_set_current_line(57, ng0);
68
+    t2 = (t0 + 6674);
69
+    t5 = (t0 + 4024);
70
+    t7 = (t5 + 56U);
71
+    t8 = *((char **)t7);
72
+    t9 = (t8 + 56U);
73
+    t10 = *((char **)t9);
74
+    memcpy(t10, t2, 8U);
75
+    xsi_driver_first_trans_fast_port(t5);
76
+    xsi_set_current_line(58, ng0);
77
+    t2 = (t0 + 6682);
78
+    t5 = (t0 + 4088);
79
+    t7 = (t5 + 56U);
64 80
     t8 = *((char **)t7);
65
-    memcpy(t8, t3, 8U);
81
+    t9 = (t8 + 56U);
82
+    t10 = *((char **)t9);
83
+    memcpy(t10, t2, 8U);
84
+    xsi_driver_first_trans_fast_port(t5);
85
+    xsi_set_current_line(59, ng0);
86
+    t2 = (t0 + 6690);
87
+    t5 = (t0 + 4152);
88
+    t7 = (t5 + 56U);
89
+    t8 = *((char **)t7);
90
+    t9 = (t8 + 56U);
91
+    t10 = *((char **)t9);
92
+    memcpy(t10, t2, 8U);
93
+    xsi_driver_first_trans_fast_port(t5);
94
+    xsi_set_current_line(60, ng0);
95
+    t2 = (t0 + 6698);
96
+    t5 = (t0 + 4216);
97
+    t7 = (t5 + 56U);
98
+    t8 = *((char **)t7);
99
+    t9 = (t8 + 56U);
100
+    t10 = *((char **)t9);
101
+    memcpy(t10, t2, 8U);
102
+    xsi_driver_first_trans_fast_port(t5);
103
+
104
+LAB9:    goto LAB2;
105
+
106
+LAB5:    t3 = (t0 + 1632U);
107
+    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
108
+    if (t4 == 1)
109
+        goto LAB4;
110
+    else
111
+        goto LAB6;
112
+
113
+LAB7:    goto LAB5;
114
+
115
+LAB8:    xsi_set_current_line(52, ng0);
116
+    t2 = (t0 + 1032U);
117
+    t5 = *((char **)t2);
118
+    t2 = (t0 + 4024);
119
+    t7 = (t2 + 56U);
120
+    t8 = *((char **)t7);
121
+    t9 = (t8 + 56U);
122
+    t10 = *((char **)t9);
123
+    memcpy(t10, t5, 8U);
66 124
     xsi_driver_first_trans_fast_port(t2);
67
-    xsi_set_current_line(51, ng0);
125
+    xsi_set_current_line(53, ng0);
68 126
     t2 = (t0 + 1192U);
69 127
     t3 = *((char **)t2);
70
-    t2 = (t0 + 3928);
128
+    t2 = (t0 + 4088);
71 129
     t5 = (t2 + 56U);
72
-    t6 = *((char **)t5);
73
-    t7 = (t6 + 56U);
74
-    t8 = *((char **)t7);
75
-    memcpy(t8, t3, 8U);
130
+    t7 = *((char **)t5);
131
+    t8 = (t7 + 56U);
132
+    t9 = *((char **)t8);
133
+    memcpy(t9, t3, 8U);
76 134
     xsi_driver_first_trans_fast_port(t2);
77
-    xsi_set_current_line(52, ng0);
135
+    xsi_set_current_line(54, ng0);
78 136
     t2 = (t0 + 1352U);
79 137
     t3 = *((char **)t2);
80
-    t2 = (t0 + 3992);
138
+    t2 = (t0 + 4152);
81 139
     t5 = (t2 + 56U);
82
-    t6 = *((char **)t5);
83
-    t7 = (t6 + 56U);
84
-    t8 = *((char **)t7);
85
-    memcpy(t8, t3, 8U);
140
+    t7 = *((char **)t5);
141
+    t8 = (t7 + 56U);
142
+    t9 = *((char **)t8);
143
+    memcpy(t9, t3, 8U);
86 144
     xsi_driver_first_trans_fast_port(t2);
87
-    xsi_set_current_line(53, ng0);
145
+    xsi_set_current_line(55, ng0);
88 146
     t2 = (t0 + 1512U);
89 147
     t3 = *((char **)t2);
90
-    t2 = (t0 + 4056);
148
+    t2 = (t0 + 4216);
91 149
     t5 = (t2 + 56U);
92
-    t6 = *((char **)t5);
93
-    t7 = (t6 + 56U);
94
-    t8 = *((char **)t7);
95
-    memcpy(t8, t3, 8U);
150
+    t7 = *((char **)t5);
151
+    t8 = (t7 + 56U);
152
+    t9 = *((char **)t8);
153
+    memcpy(t9, t3, 8U);
96 154
     xsi_driver_first_trans_fast_port(t2);
97
-    goto LAB2;
98
-
99
-LAB5:    t3 = (t0 + 1632U);
100
-    t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
101
-    if (t4 == 1)
102
-        goto LAB4;
103
-    else
104
-        goto LAB6;
105
-
106
-LAB7:    goto LAB5;
155
+    goto LAB9;
107 156
 
108 157
 }
109 158
 

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+ 1522
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xilinx/ALU/isim/work/br.vdb View File


BIN
xilinx/ALU/isim/work/pipeline.vdb View File


BIN
xilinx/ALU/isim/work/process_test.vdb View File


BIN
xilinx/ALU/isim/work/processeur.vdb View File


+ 13
- 5
xilinx/ALU/pipeline.vhd View File

@@ -35,6 +35,7 @@ entity pipeline is
35 35
            B_IN : in  STD_LOGIC_VECTOR (7 downto 0);
36 36
            C_IN : in  STD_LOGIC_VECTOR (7 downto 0);
37 37
 			  CLK : in  STD_LOGIC;
38
+			  EN : in STD_LOGIC;
38 39
            OP_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
39 40
            A_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
40 41
            B_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
@@ -47,10 +48,17 @@ begin
47 48
 	process
48 49
 		begin
49 50
 			wait until rising_edge(CLK);
50
-			OP_OUT <= OP_IN;
51
-			A_OUT <= A_IN;
52
-			B_OUT <= B_IN;
53
-			C_OUT <= C_IN;
54
-	end process;
51
+			if (EN = '1') then
52
+				OP_OUT <= OP_IN;
53
+				A_OUT <= A_IN;
54
+				B_OUT <= B_IN;
55
+				C_OUT <= C_IN;
56
+			else
57
+				OP_OUT <= "00000000";
58
+				A_OUT <= "00000000";
59
+				B_OUT <= "00000000";
60
+				C_OUT <= "00000000";
61
+			end if;
62
+		end process;
55 63
 end Behavioral;
56 64
 

BIN
xilinx/ALU/process_test_isim_beh.wdb View File


BIN
xilinx/ALU/process_test_isim_beh1.wdb View File


+ 42
- 0
xilinx/ALU/processeur.bld View File

@@ -0,0 +1,42 @@
1
+Release 13.4 ngdbuild O.87xd (lin64)
2
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
3
+
4
+Command Line:
5
+/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
6
+-intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc
7
+processeur.ngd
8
+
9
+Reading NGO file
10
+"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc"
11
+...
12
+Loading design module
13
+"/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.ngc"..
14
+.
15
+WARNING:NgdBuild:578 - Design contains no instances.
16
+Gathering constraint information from source properties...
17
+Done.
18
+
19
+Resolving constraint associations...
20
+Checking Constraint Associations...
21
+Done...
22
+
23
+Checking expanded design ...
24
+
25
+Partition Implementation Status
26
+-------------------------------
27
+
28
+  No Partitions were found in this design.
29
+
30
+-------------------------------
31
+
32
+NGDBUILD Design Results Summary:
33
+  Number of errors:     0
34
+  Number of warnings:   1
35
+
36
+Total memory usage is 398744 kilobytes
37
+
38
+Writing NGD file "processeur.ngd" ...
39
+Total REAL time to NGDBUILD completion:  1 sec
40
+Total CPU time to NGDBUILD completion:   1 sec
41
+
42
+Writing NGDBUILD log file "processeur.bld"...

+ 3
- 0
xilinx/ALU/processeur.cmd_log View File

@@ -0,0 +1,3 @@
1
+xst -intstyle ise -ifn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.xst" -ofn "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.syr" 
2
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx16-csg324-3 processeur.ngc processeur.ngd  
3
+map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf 

+ 1
- 0
xilinx/ALU/processeur.lso View File

@@ -0,0 +1 @@
1
+work

+ 3
- 0
xilinx/ALU/processeur.ngc View File

@@ -0,0 +1,3 @@
1
+XILINX-XDB 0.1 STUB 0.1 ASCII
2
+XILINX-XDM V1.6e
3
+$3cx5>443JF@86MCK148GIM609<0OAE=7178GIM5P11H@F<W1926?FJL19?0OAEN169@HNG6L;=0OAEN1E64?FJLI8N396MCKC36?FJLK8?0OAEK149@HNBQk2IGGIXPDHTJ@@3<KEAMT55LLJD[5=6>3JEFADZ[EE58GWCF\LN=7AALKDF4?II@AJKG46A!86zg[I2<XHX_:6^\DNLF7>TT\8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI;5\OTP@A3=T\H^^_95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;XGPe>vugjoxh{}109{g3ukp8<&? m|g207yEFwi2JKt?65F;095~U6<38=6<951265700=:;2<jv`=4;38j73=>2.9?7<=;|Q27?4128=1=>:9344967>?82n947>51;3xW42=:?0:;7?<47162?450>l0zY?k:182>4<7sZ;?6?8516827104=?09>59i;%02>40<,821>45m2983>7<729qC>=5+1g81<>"6k3:0(<l5269j5?6=3`;j6=44}|~DEE|i32=i=7987CDG}7uIJ[wpNO

+ 3
- 0
xilinx/ALU/processeur.ngd View File

@@ -0,0 +1,3 @@
1
+XILINX-XDB 0.1 STUB 0.1 ASCII
2
+XILINX-XDM V1.6e
3
+$2fx4>753-Xnzd}foo8#5+420).?o6!golg,bjst{h~x#O{}e`w,twimm}Uxu~zjm.rqkocsWzsxxhcj/ykomk~(IE_$|alerqfqw(ioj;0>h59smz22fu`;;>&?<>4BTKO@ZRFZNO_M_MG3:AOO1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK826?FJLI8=0OAEN1E04?FJLI8N?;6MCK@3G<0=DDBH:96MCKB36?FJLL8?0OAEKVb9@HNBQWMC]EIK:;BNHB]><KEAMT<6?9:ALIHOS\LN<7N\JAUGGa>BUKVY^ONK\SGWO<>C_XHDOII?>;DZSEKBBLVHHHRHFLD37?@^WIGNNHRM@NRVQELHS[8;0IU^NNEGG[LUBWOCGI55IIMGMEHCc3OCGICOBE^PLKQc<AGUEKIQNNE]AGA0<DFKOII84LNAHAA1<DFMBOLBl;LcikwPbzzcdbn5BiomqR`ttafd<7CK[WNPH<>I)0>roSA:4P@PW2>VTLFDN?6\\T038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA3=T\H^^_95[YQG`?PUBZV\B_DLCE89UM@QX\PZN=i5WIMKM\(^CJ):%=-][UC"3*4&F[JCB:6Vkb^Kgb>^c`VZye`Xjrrklj46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafd87U}{3:[FW==iomh~eajn;qplg`utm|x37~~nrucm24><pedsSl{{o^2\|ad(kz~%tomk}ABs54=GHq9j6K4;:0yP5<<4?3836<=;6275>74??oqe?84>;o15>3=#;:08>6s\19803?4?289?:>;9:30;<5=T:;0857?51265700=:;2h<6]>8;1:>4<6;=<89;4=29a1?a5f290:6<u\18803?4?289?:>;9:30;3c=#=39i7E?n;wV2f?6=93;1>v]>9;14>7>=9:>=?88523:4b>"4938?7[=;:3yv60<63|8=6=5r$3;90>"6m3:0(<m53b9'5a<592h8m7>52;296~N482.9j7=n;%0g>6=#:j0846*>f;08 76=;h1b:7>5;h0a>5<<{?0;6<uQ6:p6g<728qU>o5r}of94?7|ugo1<7?t}|~DEE|980n>ihm6g4~DED|8tJK\vsO@

+ 3
- 0
xilinx/ALU/processeur.ngr View File

@@ -0,0 +1,3 @@
1
+XILINX-XDB 0.1 STUB 0.1 ASCII
2
+XILINX-XDM V1.6e
3
+$0:x0f=(`fgn#kazsrcww*Drzlk~#}|`jdv\w|usmd%{~bdjt^qzwqcjm&rb`d`w/@NV+uthklyxix|!viff?3ukp8<hj==4,10?FJL12IDA@G[TDF4?FTBI]OO;6B@GHABH==H&1=shRB;;QCQP6=U[]90^YBi;RMVVFCXN@FNBLCJd:QLQWEBWECEICL;;U[SA<=QAL]TXT^J1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF1d9[WQYNEYFNAH@[AUKLJZEHFZ^YMD@[S028\VRXZ]FT\_A_ESVZ2>^cjVCo==5Wdl]Neoiu^lxxeb`>0:ZgiZKnffx]i}foo18\vr>3QyK@akemc8twidmzyny?>;ya5wi~6>$9&o~i<25CDue<HIr:97H52;3xW1<6<3<1=>:9344967>?8rd:>7?4n0192>"693o0q^=51585>453>:?=6?<7819g53<7280:w^:51585>453>:?=6?<7819uB<<7280:6=u\4;37>3<6;=<89;4=29:3?!b==2.<6<5m1783>7<729qGj7?t$6823>{K9909w)o50:la>75<u-i1=;5f2;29?l>=831vqpsO@By`>g37>=i>qMNM{1CDU}zHI

+ 6
- 0
xilinx/ALU/processeur.prj View File

@@ -0,0 +1,6 @@
1
+vhdl work "pipeline.vhd"
2
+vhdl work "br.vhd"
3
+vhdl work "bm_instr.vhd"
4
+vhdl work "bm.vhd"
5
+vhdl work "alu.vhd"
6
+vhdl work "processeur.vhd"

+ 0
- 0
xilinx/ALU/processeur.stx View File


+ 303
- 0
xilinx/ALU/processeur.syr View File

@@ -0,0 +1,303 @@
1
+Release 13.4 - xst O.87xd (lin64)
2
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
3
+--> 
4
+Parameter TMPDIR set to xst/projnav.tmp
5
+
6
+
7
+Total REAL time to Xst completion: 1.00 secs
8
+Total CPU time to Xst completion: 0.03 secs
9
+ 
10
+--> 
11
+Parameter xsthdpdir set to xst
12
+
13
+
14
+Total REAL time to Xst completion: 1.00 secs
15
+Total CPU time to Xst completion: 0.03 secs
16
+ 
17
+--> 
18
+Reading design: processeur.prj
19
+
20
+TABLE OF CONTENTS
21
+  1) Synthesis Options Summary
22
+  2) HDL Parsing
23
+  3) HDL Elaboration
24
+  4) HDL Synthesis
25
+       4.1) HDL Synthesis Report
26
+  5) Advanced HDL Synthesis
27
+       5.1) Advanced HDL Synthesis Report
28
+  6) Low Level Synthesis
29
+  7) Partition Report
30
+  8) Design Summary
31
+       8.1) Primitive and Black Box Usage
32
+       8.2) Device utilization summary
33
+       8.3) Partition Resource Summary
34
+       8.4) Timing Report
35
+            8.4.1) Clock Information
36
+            8.4.2) Asynchronous Control Signals Information
37
+            8.4.3) Timing Summary
38
+            8.4.4) Timing Details
39
+            8.4.5) Cross Clock Domains Report
40
+
41
+
42
+=========================================================================
43
+*                      Synthesis Options Summary                        *
44
+=========================================================================
45
+---- Source Parameters
46
+Input File Name                    : "processeur.prj"
47
+Ignore Synthesis Constraint File   : NO
48
+
49
+---- Target Parameters
50
+Output File Name                   : "processeur"
51
+Output Format                      : NGC
52
+Target Device                      : xc6slx16-3-csg324
53
+
54
+---- Source Options
55
+Top Module Name                    : processeur
56
+Automatic FSM Extraction           : YES
57
+FSM Encoding Algorithm             : Auto
58
+Safe Implementation                : No
59
+FSM Style                          : LUT
60
+RAM Extraction                     : Yes
61
+RAM Style                          : Auto
62
+ROM Extraction                     : Yes
63
+Shift Register Extraction          : YES
64
+ROM Style                          : Auto
65
+Resource Sharing                   : YES
66
+Asynchronous To Synchronous        : NO
67
+Shift Register Minimum Size        : 2
68
+Use DSP Block                      : Auto
69
+Automatic Register Balancing       : No
70
+
71
+---- Target Options
72
+LUT Combining                      : Auto
73
+Reduce Control Sets                : Auto
74
+Add IO Buffers                     : YES
75
+Global Maximum Fanout              : 100000
76
+Add Generic Clock Buffer(BUFG)     : 16
77
+Register Duplication               : YES
78
+Optimize Instantiated Primitives   : NO
79
+Use Clock Enable                   : Auto
80
+Use Synchronous Set                : Auto
81
+Use Synchronous Reset              : Auto
82
+Pack IO Registers into IOBs        : Auto
83
+Equivalent register Removal        : YES
84
+
85
+---- General Options
86
+Optimization Goal                  : Speed
87
+Optimization Effort                : 1
88
+Power Reduction                    : NO
89
+Keep Hierarchy                     : No
90
+Netlist Hierarchy                  : As_Optimized
91
+RTL Output                         : Yes
92
+Global Optimization                : AllClockNets
93
+Read Cores                         : YES
94
+Write Timing Constraints           : NO
95
+Cross Clock Analysis               : NO
96
+Hierarchy Separator                : /
97
+Bus Delimiter                      : <>
98
+Case Specifier                     : Maintain
99
+Slice Utilization Ratio            : 100
100
+BRAM Utilization Ratio             : 100
101
+DSP48 Utilization Ratio            : 100
102
+Auto BRAM Packing                  : NO
103
+Slice Utilization Ratio Delta      : 5
104
+
105
+=========================================================================
106
+
107
+INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL
108
+
109
+=========================================================================
110
+*                          HDL Parsing                                  *
111
+=========================================================================
112
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/pipeline.vhd" into library work
113
+Parsing entity <pipeline>.
114
+Parsing architecture <Behavioral> of entity <pipeline>.
115
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd" into library work
116
+Parsing entity <br>.
117
+Parsing architecture <Behavioral> of entity <br>.
118
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
119
+Parsing entity <bm_instr>.
120
+Parsing architecture <Behavioral> of entity <bm_instr>.
121
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm.vhd" into library work
122
+Parsing entity <bm_data>.
123
+Parsing architecture <Behavioral> of entity <bm_data>.
124
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
125
+Parsing entity <alu>.
126
+Parsing architecture <Behavioral> of entity <alu>.
127
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" into library work
128
+Parsing entity <processeur>.
129
+Parsing architecture <Behavioral> of entity <processeur>.
130
+
131
+=========================================================================
132
+*                            HDL Elaboration                            *
133
+=========================================================================
134
+
135
+Elaborating entity <processeur> (architecture <Behavioral>) from library <work>.
136
+
137
+Elaborating entity <bm_instr> (architecture <Behavioral>) from library <work>.
138
+
139
+Elaborating entity <pipeline> (architecture <Behavioral>) from library <work>.
140
+
141
+Elaborating entity <br> (architecture <Behavioral>) from library <work>.
142
+
143
+Elaborating entity <alu> (architecture <Behavioral>) from library <work>.
144
+
145
+Elaborating entity <bm_data> (architecture <Behavioral>) from library <work>.
146
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 156. All outputs of instance <addr_instructions> of block <bm_instr> are unconnected in block <processeur>. Underlying logic will be removed.
147
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 163. All outputs of instance <LI_LD> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
148
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 184. All outputs of instance <banc_registres> of block <br> are unconnected in block <processeur>. Underlying logic will be removed.
149
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 200. All outputs of instance <DI_EX> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
150
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221. All outputs of instance <UAL> of block <alu> are unconnected in block <processeur>. Underlying logic will be removed.
151
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237. All outputs of instance <EX_Mem> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
152
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 262. All outputs of instance <data_memory> of block <bm_data> are unconnected in block <processeur>. Underlying logic will be removed.
153
+WARNING:Xst:2972 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272. All outputs of instance <Mem_RE> of block <pipeline> are unconnected in block <processeur>. Underlying logic will be removed.
154
+
155
+=========================================================================
156
+*                           HDL Synthesis                               *
157
+=========================================================================
158
+
159
+Synthesizing Unit <processeur>.
160
+    Related source file is "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd".
161
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <N> of the instance <UAL> is unconnected or connected to loadless signal.
162
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <O> of the instance <UAL> is unconnected or connected to loadless signal.
163
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <Z> of the instance <UAL> is unconnected or connected to loadless signal.
164
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 221: Output port <C> of the instance <UAL> is unconnected or connected to loadless signal.
165
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 237: Output port <C_OUT> of the instance <EX_Mem> is unconnected or connected to loadless signal.
166
+INFO:Xst:3210 - "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/processeur.vhd" line 272: Output port <C_OUT> of the instance <Mem_RE> is unconnected or connected to loadless signal.
167
+    Summary:
168
+	no macro.
169
+Unit <processeur> synthesized.
170
+
171
+=========================================================================
172
+HDL Synthesis Report
173
+
174
+Found no macro
175
+=========================================================================
176
+
177
+=========================================================================
178
+*                       Advanced HDL Synthesis                          *
179
+=========================================================================
180
+
181
+
182
+=========================================================================
183
+Advanced HDL Synthesis Report
184
+
185
+Found no macro
186
+=========================================================================
187
+
188
+=========================================================================
189
+*                         Low Level Synthesis                           *
190
+=========================================================================
191
+
192
+Optimizing unit <processeur> ...
193
+
194
+Mapping all equations...
195
+Building and optimizing final netlist ...
196
+Found area constraint ratio of 100 (+ 5) on block processeur, actual ratio is 0.
197
+
198
+Final Macro Processing ...
199
+
200
+=========================================================================
201
+Final Register Report
202
+
203
+Found no macro
204
+=========================================================================
205
+
206
+=========================================================================
207
+*                           Partition Report                            *
208
+=========================================================================
209
+
210
+Partition Implementation Status
211
+-------------------------------
212
+
213
+  No Partitions were found in this design.
214
+
215
+-------------------------------
216
+
217
+=========================================================================
218
+*                            Design Summary                             *
219
+=========================================================================
220
+
221
+Top Level Output File Name         : processeur.ngc
222
+
223
+Primitive and Black Box Usage:
224
+------------------------------
225
+
226
+Device utilization summary:
227
+---------------------------
228
+
229
+Selected Device : 6slx16csg324-3 
230
+
231
+
232
+Slice Logic Utilization: 
233
+
234
+Slice Logic Distribution: 
235
+ Number of LUT Flip Flop pairs used:      0
236
+   Number with an unused Flip Flop:       0  out of      0         
237
+   Number with an unused LUT:             0  out of      0         
238
+   Number of fully used LUT-FF pairs:     0  out of      0         
239
+   Number of unique control sets:         0
240
+
241
+IO Utilization: 
242
+ Number of IOs:                           2
243
+ Number of bonded IOBs:                   0  out of    232     0%  
244
+
245
+Specific Feature Utilization:
246
+
247
+---------------------------
248
+Partition Resource Summary:
249
+---------------------------
250
+
251
+  No Partitions were found in this design.
252
+
253
+---------------------------
254
+
255
+
256
+=========================================================================
257
+Timing Report
258
+
259
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
260
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
261
+      GENERATED AFTER PLACE-and-ROUTE.
262
+
263
+Clock Information:
264
+------------------
265
+No clock signals found in this design
266
+
267
+Asynchronous Control Signals Information:
268
+----------------------------------------
269
+No asynchronous control signals found in this design
270
+
271
+Timing Summary:
272
+---------------
273
+Speed Grade: -3
274
+
275
+   Minimum period: No path found
276
+   Minimum input arrival time before clock: No path found
277
+   Maximum output required time after clock: No path found
278
+   Maximum combinational path delay: No path found
279
+
280
+Timing Details:
281
+---------------
282
+All values displayed in nanoseconds (ns)
283
+
284
+=========================================================================
285
+
286
+Cross Clock Domains Report:
287
+--------------------------
288
+
289
+=========================================================================
290
+
291
+
292
+Total REAL time to Xst completion: 4.00 secs
293
+Total CPU time to Xst completion: 2.94 secs
294
+ 
295
+--> 
296
+
297
+
298
+Total memory usage is 389560 kilobytes
299
+
300
+Number of errors   :    0 (   0 filtered)
301
+Number of warnings :    8 (   0 filtered)
302
+Number of infos    :    7 (   0 filtered)
303
+

+ 287
- 237
xilinx/ALU/processeur.vhd View File

@@ -1,271 +1,303 @@
1
-----------------------------------------------------------------------------------
2
---
3
---
4
---
5
-----------------------------------------------------------------------------------
6
-library IEEE;
7
-use IEEE.STD_LOGIC_1164.ALL;
8
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
1
+    ----------------------------------------------------------------------------------
2
+    -- Company: 
3
+    -- Engineer: 
4
+    -- 
5
+    -- Create Date:    12:52:06 05/04/2021 
6
+    -- Design Name: 
7
+    -- Module Name:    processeur - Behavioral 
8
+    -- Project Name: 
9
+    -- Target Devices: 
10
+    -- Tool versions: 
11
+    -- Description: 
12
+    --
13
+    -- Dependencies: 
14
+    --
15
+    -- Revision: 
16
+    -- Revision 0.01 - File Created
17
+    -- Additional Comments: 
18
+    --
19
+    ----------------------------------------------------------------------------------
20
+    library IEEE;
21
+    use IEEE.STD_LOGIC_1164.ALL;
22
+    use IEEE.STD_LOGIC_UNSIGNED.ALL;
9 23
 
10
-use IEEE.NUMERIC_STD.ALL;
24
+    use IEEE.NUMERIC_STD.ALL;
11 25
 
12
---use IEEE.NUMERIC_STD.ALL;
26
+    -- Uncomment the following library declaration if using
27
+    -- arithmetic functions with Signed or Unsigned values
28
+    --use IEEE.NUMERIC_STD.ALL;
13 29
 
14
---library UNISIM;
15
---use UNISIM.VComponents.all;
30
+    -- Uncomment the following library declaration if instantiating
31
+    -- any Xilinx primitives in this code.
32
+    --library UNISIM;
33
+    --use UNISIM.VComponents.all;
16 34
 
17
-entity processeur is
18
-    Port ( CLK: in  STD_LOGIC ;
19
-				RST : in STD_LOGIC);
20
-end processeur;
35
+    entity processeur is
36
+        Port ( CLK: in  STD_LOGIC ;
37
+    				RST : in STD_LOGIC);
38
+    end processeur;
21 39
 
22
-architecture Behavioral of processeur is
23
-	COMPONENT bm_instr
24
-    PORT(
25
-         IN_addr : IN  std_logic_vector(7 downto 0);
26
-         OUT_data : OUT  std_logic_vector(31 downto 0);
27
-         CLK : IN  std_logic 
28
-        );
29
-    END COMPONENT;
30
-	 
31
-	 COMPONENT pipeline
32
-    PORT( OP_IN : in  STD_LOGIC_VECTOR (7 downto 0);
33
-           A_IN : in  STD_LOGIC_VECTOR (7 downto 0);
34
-           B_IN : in  STD_LOGIC_VECTOR (7 downto 0);
35
-           C_IN : in  STD_LOGIC_VECTOR (7 downto 0);
36
-			  CLK : IN  std_logic;
37
-           OP_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
38
-           A_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
39
-           B_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
40
-           C_OUT : out  STD_LOGIC_VECTOR (7 downto 0)
41
-        );
42
-    END COMPONENT;
43
-	 
44
-	 COMPONENT br
45
-    PORT(
46
-         A_addr : IN  std_logic_vector(3 downto 0);
47
-         B_addr : IN  std_logic_vector(3 downto 0);
48
-         W_addr : IN  std_logic_vector(3 downto 0);
49
-         W : IN  std_logic;
50
-         Data : IN  std_logic_vector(7 downto 0);
51
-         RST : IN  std_logic;
52
-         CLK : IN  std_logic;
53
-         QA : OUT  std_logic_vector(7 downto 0);
54
-         QB : OUT  std_logic_vector(7 downto 0)
55
-        );
56
-    END COMPONENT;
57
-	 
58
-	 COMPONENT alu
59
-    PORT(
60
-         A : IN  std_logic_vector(7 downto 0);
61
-         B : IN  std_logic_vector(7 downto 0);
62
-         Ctrl_Alu : IN  std_logic_vector(2 downto 0);
63
-         N : OUT  std_logic;
64
-         O : OUT  std_logic;
65
-         Z : OUT  std_logic;
66
-         C : OUT  std_logic;
67
-         S : OUT  std_logic_vector(7 downto 0)
68
-        );
69
-    END COMPONENT;
70
-	 
71
-	 COMPONENT bm_data
72
-    PORT(
73
-         IN_addr : IN  std_logic_vector(7 downto 0);
74
-         IN_data : IN  std_logic_vector(7 downto 0);
75
-         RW : IN  std_logic;
76
-         RST : IN  std_logic;
77
-         CLK : IN  std_logic;
78
-         OUT_data : OUT  std_logic_vector(7 downto 0)
79
-        );
80
-    END COMPONENT;
81
-		
82
-	--Inputs
83
-   signal IP : std_logic_vector(7 downto 0) := (others => '0');
84
-	signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
40
+    architecture Behavioral of processeur is
41
+    	COMPONENT bm_instr
42
+        PORT(
43
+             IN_addr : IN  std_logic_vector(7 downto 0);
44
+             OUT_data : OUT  std_logic_vector(31 downto 0);
45
+             CLK : IN  std_logic 
46
+            );
47
+        END COMPONENT;
48
+    	 
49
+    	 COMPONENT pipeline
50
+        PORT( OP_IN : in  STD_LOGIC_VECTOR (7 downto 0);
51
+               A_IN : in  STD_LOGIC_VECTOR (7 downto 0);
52
+               B_IN : in  STD_LOGIC_VECTOR (7 downto 0);
53
+               C_IN : in  STD_LOGIC_VECTOR (7 downto 0);
54
+    			  CLK : IN  std_logic;
55
+				  EN : in STD_LOGIC;
56
+               OP_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
57
+               A_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
58
+               B_OUT : out  STD_LOGIC_VECTOR (7 downto 0);
59
+               C_OUT : out  STD_LOGIC_VECTOR (7 downto 0)
60
+            );
61
+        END COMPONENT;
62
+    	 
63
+    	 COMPONENT br
64
+        PORT(
65
+             A_addr : IN  std_logic_vector(3 downto 0);
66
+             B_addr : IN  std_logic_vector(3 downto 0);
67
+             W_addr : IN  std_logic_vector(3 downto 0);
68
+             W : IN  std_logic;
69
+             Data : IN  std_logic_vector(7 downto 0);
70
+             RST : IN  std_logic;
71
+             CLK : IN  std_logic;
72
+             QA : OUT  std_logic_vector(7 downto 0);
73
+             QB : OUT  std_logic_vector(7 downto 0)
74
+            );
75
+        END COMPONENT;
76
+    	 
77
+    	 COMPONENT alu
78
+        PORT(
79
+             A : IN  std_logic_vector(7 downto 0);
80
+             B : IN  std_logic_vector(7 downto 0);
81
+             Ctrl_Alu : IN  std_logic_vector(2 downto 0);
82
+             N : OUT  std_logic;
83
+             O : OUT  std_logic;
84
+             Z : OUT  std_logic;
85
+             C : OUT  std_logic;
86
+             S : OUT  std_logic_vector(7 downto 0)
87
+            );
88
+        END COMPONENT;
89
+    	 
90
+    	 COMPONENT bm_data
91
+        PORT(
92
+             IN_addr : IN  std_logic_vector(7 downto 0);
93
+             IN_data : IN  std_logic_vector(7 downto 0);
94
+             RW : IN  std_logic;
95
+             RST : IN  std_logic;
96
+             CLK : IN  std_logic;
97
+             OUT_data : OUT  std_logic_vector(7 downto 0)
98
+            );
99
+        END COMPONENT;
100
+    		
101
+    	--Inputs
102
+       signal IP : std_logic_vector(7 downto 0) := (others => '0');
103
+    	signal QA_IN_MUX : std_logic_vector(7 downto 0) := (others => '0');
85 104
 
86
-	signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
87
-	signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
88
-	
89
- 	--Outputs
90
-   signal OUT_data : std_logic_vector(31 downto 0);
91
-	
92
-	signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
93
-	signal A_LIDI_OUT : std_logic_vector(7 downto 0);
94
-	signal B_LIDI_OUT : std_logic_vector(7 downto 0);
95
-	signal C_LIDI_OUT : std_logic_vector(7 downto 0);
96
-	
97
-	signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
98
-	signal A_DIEX_OUT : std_logic_vector(7 downto 0);
99
-	signal B_DIEX_OUT : std_logic_vector(7 downto 0);
100
-	signal C_DIEX_OUT : std_logic_vector(7 downto 0);
101
-	
102
-	signal O_ALU_OUT : std_logic;
103
-	signal N_ALU_OUT : std_logic;
104
-	signal Z_ALU_OUT : std_logic;
105
-	signal C_ALU_OUT : std_logic;
106
-	
107
-	signal A_EXMem_OUT : std_logic_vector(7 downto 0);
108
-	signal B_EXMem_OUT : std_logic_vector(7 downto 0);
109
-	signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
110
-	
111
-	signal A_MemRE_OUT : std_logic_vector(7 downto 0);
112
-	signal B_MemRE_OUT : std_logic_vector(7 downto 0);
113
-	signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
114
-	
115
-	--AUX
116
-	
117
-	signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
118
-	signal RW_LC : std_logic;
119
-	signal addr_dm_MUX : std_logic_vector(7 downto 0);
120
-	signal in_dm_MUX : std_logic_vector(7 downto 0);
121
-	signal out_dm_MUX : std_logic_vector(7 downto 0);
122
-	signal B_EXMem_IN : std_logic_vector(7 downto 0);
123
-	signal W_br_LC : std_logic;
124
-	signal S_IN_MUX : std_logic_vector(7 downto 0);
125
-	signal B_MemRE_IN : std_logic_vector(7 downto 0);
126
-	
127
-begin
128
-	
129
-	-- Instantiate adresse des instructions 
130
-   addr_instructions: bm_instr PORT MAP (
131
-          IN_addr => IP,
132
-          OUT_data => OUT_data,
133
-          CLK => CLK
134
-   	);
105
+    	signal B_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
106
+    	signal C_DIEX_IN : std_logic_vector(7 downto 0) := (others => '0');
107
+    	
108
+     	--Outputs
109
+       signal OUT_data : std_logic_vector(31 downto 0);
110
+    	
111
+    	signal OP_LIDI_OUT : std_logic_vector(7 downto 0);
112
+    	signal A_LIDI_OUT : std_logic_vector(7 downto 0);
113
+    	signal B_LIDI_OUT : std_logic_vector(7 downto 0);
114
+    	signal C_LIDI_OUT : std_logic_vector(7 downto 0);
115
+    	
116
+    	signal OP_DIEX_OUT : std_logic_vector(7 downto 0);
117
+    	signal A_DIEX_OUT : std_logic_vector(7 downto 0);
118
+    	signal B_DIEX_OUT : std_logic_vector(7 downto 0);
119
+    	signal C_DIEX_OUT : std_logic_vector(7 downto 0);
120
+    	
121
+    	signal O_ALU_OUT : std_logic;
122
+    	signal N_ALU_OUT : std_logic;
123
+    	signal Z_ALU_OUT : std_logic;
124
+    	signal C_ALU_OUT : std_logic;
125
+    	
126
+    	signal A_EXMem_OUT : std_logic_vector(7 downto 0);
127
+    	signal B_EXMem_OUT : std_logic_vector(7 downto 0);
128
+    	signal OP_EXMem_OUT : std_logic_vector(7 downto 0);
129
+    	
130
+    	signal A_MemRE_OUT : std_logic_vector(7 downto 0);
131
+    	signal B_MemRE_OUT : std_logic_vector(7 downto 0);
132
+    	signal OP_MemRE_OUT : std_logic_vector(7 downto 0);
133
+    	
134
+    	--AUX
135
+    	
136
+    	signal Ctr_ALU_LC : std_logic_vector(2 downto 0);
137
+    	signal RW_LC : std_logic;
138
+    	signal addr_dm_MUX : std_logic_vector(7 downto 0);
139
+    	signal in_dm_MUX : std_logic_vector(7 downto 0);
140
+    	signal out_dm_MUX : std_logic_vector(7 downto 0);
141
+    	signal B_EXMem_IN : std_logic_vector(7 downto 0);
142
+    	signal W_br_LC : std_logic;
143
+    	signal S_IN_MUX : std_logic_vector(7 downto 0);
144
+    	signal B_MemRE_IN : std_logic_vector(7 downto 0);
145
+    	
146
+		--alea
147
+		signal li_di_r_b : std_logic;
148
+		signal li_di_r_c : std_logic;
149
+		signal di_ex_w_a : std_logic;
150
+		signal ex_mem_w_a : std_logic;
151
+		signal alea : std_logic;
152
+		
153
+    begin
154
+    	
155
+    	-- Instantiate adresse des instructions 
156
+       addr_instructions: bm_instr PORT MAP (
157
+              IN_addr => IP,
158
+              OUT_data => OUT_data,
159
+              CLK => CLK
160
+       	);
135 161
 
136
-	-- Instantiate pipeline LI_LD
137
-	LI_LD : pipeline PORT MAP (
138
-			OP_IN => OUT_data(31 downto 24),
139
-           A_IN => OUT_data(23 downto 16),
140
-           B_IN => OUT_data(15 downto 8),
141
-           C_IN => OUT_data(7 downto 0),
142
-			  CLK => CLK,
143
-			  A_OUT => A_LIDI_OUT,
144
-			  B_OUT => B_LIDI_OUT,
145
-			  C_OUT => C_LIDI_OUT,
146
-			  OP_OUT => OP_LIDI_OUT
147
-           );
148
-	W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
149
-					'0';
150
-	-- Instanciate banc de registre
151
-   banc_registres : br PORT MAP (
152
-          A_addr => B_LIDI_OUT(3 downto 0),
153
-          B_addr => C_LIDI_OUT(3 downto 0),
154
-          W_addr => A_MemRE_OUT(3 downto 0),
155
-          W => W_br_LC, --ATTENTION LC
156
-          Data => B_MemRE_OUT,
157
-          RST => RST,
158
-          CLK => CLK,
159
-          QA => QA_IN_MUX,
160
-          QB => C_DIEX_IN
161
-        );
162
-			
163
-	B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" else B_LIDI_OUT ;
164
-			
165
-			
166
-	-- Instantiate pipeline DI_EX
167
-	DI_EX : pipeline PORT MAP (
168
-			OP_IN => OP_LIDI_OUT,
169
-		  A_IN => A_LIDI_OUT,
170
-		  B_IN => B_DIEX_IN,
171
-		  C_IN => C_DIEX_IN,
172
-		  CLK => CLK,
173
-		  A_OUT => A_DIEX_OUT,
174
-		  B_OUT => B_DIEX_OUT,
175
-		  C_OUT => C_DIEX_OUT,
176
-		  OP_OUT => OP_DIEX_OUT
177
-		  );
178
-		  
179
-	Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else 
180
-						"010" when OP_DIEX_OUT = x"03" else
181
-						"011" when OP_DIEX_OUT = x"02" else
182
-						"000";	  
183
-	
184
-	-- Instantiate alu	  
185
-	 UAL : alu PORT MAP (
186
-         A => B_DIEX_OUT,
187
-         B => C_DIEX_OUT,
188
-         Ctrl_Alu =>Ctr_AlU_LC,
189
-         N => N_ALU_OUT,
190
-         O => O_ALU_OUT,
191
-         Z => Z_ALU_OUT,
192
-         C => C_ALU_OUT,
193
-         S => S_IN_MUX
194
-        );
195
-	
196
-	B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else 
197
-						B_DIEX_OUT ;
198
-						
162
+    	-- Instantiate pipeline LI_LD
163
+    	LI_LD : pipeline PORT MAP (
164
+    			OP_IN => OUT_data(31 downto 24),
165
+               A_IN => OUT_data(23 downto 16),
166
+               B_IN => OUT_data(15 downto 8),
167
+               C_IN => OUT_data(7 downto 0),
168
+    			  CLK => CLK,
169
+				  EN => alea,
170
+    			  A_OUT => A_LIDI_OUT,
171
+    			  B_OUT => B_LIDI_OUT,
172
+    			  C_OUT => C_LIDI_OUT,
173
+    			  OP_OUT => OP_LIDI_OUT
174
+               );
175
+    	W_br_LC <= '1' when OP_MemRE_OUT = x"07" or OP_MemRE_OUT = x"05" or OP_MemRE_OUT = x"06" or OP_MemRE_OUT = x"01" or OP_MemRE_OUT = x"02" or OP_MemRE_OUT = x"03" or OP_MemRE_OUT = x"04" else
176
+    					'0';
199 177
 						
200
-	-- Instantiate pipeline EX_Mem
201
-	EX_Mem : pipeline PORT MAP (
202
-			OP_IN => OP_DIEX_OUT,
203
-           A_IN => A_DIEX_OUT,
204
-           B_IN => B_EXMem_IN,
205
-           C_IN => x"00",
206
-			  CLK => CLK,
207
-			  A_OUT => A_EXMem_OUT,
208
-			  B_OUT => B_EXMem_OUT,
209
-			  C_OUT => open,
210
-			  OP_OUT => OP_EXMem_OUT
211
-           );
212
-			
213
-	RW_LC <= '0' when OP_EXMem_OUT = x"08" else 
214
-						'1';
215
-	addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
216
-						A_EXMem_OUT;
217
-	in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; 
218
-	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" else
219
-						B_EXMem_OUT;
220
-	-- Instantiate banc de données
221
-   data_memory: bm_data PORT MAP (
222
-          IN_addr => addr_dm_MUX,
223
-          IN_data => B_MemRE_IN,
224
-          RW => RW_LC,
225
-          RST => RST,
226
-          CLK => CLK,
227
-          OUT_data => out_dm_MUX 
228
-        );
178
+		--alea LI_DI
179
+		li_di_r_b <= '1' when OUT_data(31 downto 24) = x"05" or OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04" or OUT_data(31 downto 24) = x"08"
180
+						else '0';
181
+		li_di_r_c <= '1' when OUT_data(31 downto 24) = x"01" or OUT_data(31 downto 24) = x"02" or OUT_data(31 downto 24) = x"03" or OUT_data(31 downto 24) = x"04"
182
+						else '0';
183
+    	-- Instanciate banc de registre
184
+       banc_registres : br PORT MAP (
185
+              A_addr => B_LIDI_OUT(3 downto 0),
186
+              B_addr => C_LIDI_OUT(3 downto 0),
187
+              W_addr => A_MemRE_OUT(3 downto 0),
188
+              W => W_br_LC, --ATTENTION LC
189
+              Data => B_MemRE_OUT,
190
+              RST => RST,
191
+              CLK => CLK,
192
+              QA => QA_IN_MUX,
193
+              QB => C_DIEX_IN
194
+            );
195
+    			
196
+    	B_DIEX_IN <= QA_IN_MUX when OP_LIDI_OUT = x"05" or OP_LIDI_OUT = x"01" or OP_LIDI_OUT = x"02" or OP_LIDI_OUT = x"03" or OP_LIDI_OUT = x"04" or OP_LIDI_OUT = x"08" else B_LIDI_OUT ;
197
+    			
198
+    			
199
+    	-- Instantiate pipeline DI_EX
200
+    	DI_EX : pipeline PORT MAP (
201
+    			OP_IN => OP_LIDI_OUT,
202
+    		  A_IN => A_LIDI_OUT,
203
+    		  B_IN => B_DIEX_IN,
204
+    		  C_IN => C_DIEX_IN,
205
+    		  CLK => CLK,
206
+			  EN => '1',
207
+    		  A_OUT => A_DIEX_OUT,
208
+    		  B_OUT => B_DIEX_OUT,
209
+    		  C_OUT => C_DIEX_OUT,
210
+    		  OP_OUT => OP_DIEX_OUT
211
+    		  );
212
+    		  
213
+    	Ctr_ALU_LC <= "001" when OP_DIEX_OUT = x"01" else 
214
+    						"010" when OP_DIEX_OUT = x"03" else
215
+    						"011" when OP_DIEX_OUT = x"02" else
216
+    						"000";	  
217
+    	-- alea DI_EX
218
+		di_ex_w_a <= '0' when OP_LIDI_OUT = x"08" or OP_LIDI_OUT = x"00"
219
+					else '1';
220
+    	-- Instantiate alu	  
221
+    	 UAL : alu PORT MAP (
222
+             A => B_DIEX_OUT,
223
+             B => C_DIEX_OUT,
224
+             Ctrl_Alu =>Ctr_AlU_LC,
225
+             N => N_ALU_OUT,
226
+             O => O_ALU_OUT,
227
+             Z => Z_ALU_OUT,
228
+             C => C_ALU_OUT,
229
+             S => S_IN_MUX
230
+            );
231
+    	
232
+    	B_EXMem_IN <= S_IN_MUX when OP_DIEX_OUT = x"01" or OP_DIEX_OUT = x"02" or OP_DIEX_OUT = x"03" else 
233
+    						B_DIEX_OUT ;
234
+    						
235
+    						
236
+    	-- Instantiate pipeline EX_Mem
237
+    	EX_Mem : pipeline PORT MAP (
238
+    			OP_IN => OP_DIEX_OUT,
239
+               A_IN => A_DIEX_OUT,
240
+               B_IN => B_EXMem_IN,
241
+               C_IN => x"00",
242
+    			  CLK => CLK,
243
+				  EN => '1',
244
+    			  A_OUT => A_EXMem_OUT,
245
+    			  B_OUT => B_EXMem_OUT,
246
+    			  C_OUT => open,
247
+    			  OP_OUT => OP_EXMem_OUT
248
+               );
249
+    			
250
+    	RW_LC <= '0' when OP_EXMem_OUT = x"08" else 
251
+    						'1';
252
+    	addr_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"07" else
253
+    						A_EXMem_OUT;
254
+    	in_dm_MUX <= B_EXMem_OUT when OP_EXMem_OUT = x"08"; 
255
+    	B_MemRE_IN <= out_dm_MUX when OP_EXMem_OUT = x"08" or OP_EXMem_OUT = x"07" else
256
+    						B_EXMem_OUT;
257
+							
258
+		-- alea ex_mem
259
+		ex_mem_w_a <= '0' when OP_DIEX_OUT = x"08" or OP_DIEX_OUT = x"00"
260
+				else '1';
261
+    	-- Instantiate banc de données
262
+       data_memory: bm_data PORT MAP (
263
+              IN_addr => addr_dm_MUX,
264
+              IN_data => in_dm_MUX,
265
+              RW => RW_LC,
266
+              RST => RST,
267
+              CLK => CLK,
268
+              OUT_data => out_dm_MUX 
269
+            );
270
+    	
271
+    	-- Instantiate pipeline Mem_RE
272
+    	Mem_RE : pipeline PORT MAP (
273
+    			OP_IN => OP_EXMem_OUT,
274
+               A_IN => A_EXMem_OUT,
275
+               B_IN => B_MemRE_IN,
276
+               C_IN => x"00",
277
+    			  CLK => CLK,
278
+				  EN => '1',
279
+    			  A_OUT => A_MemRE_OUT,
280
+    			  B_OUT => B_MemRE_OUT,
281
+    			  C_OUT => open,
282
+    			  OP_OUT => OP_MemRE_OUT
283
+               );
284
+					
285
+		alea <= '0' when (li_di_r_b = '1' and di_ex_w_a = '1' and OUT_data(15 downto 8) = A_LIDI_OUT) or
286
+						  (li_di_r_c = '1' and di_ex_w_a = '1' and OUT_data(7 downto 0) = A_LIDI_OUT) or
287
+						  (li_di_r_b = '1' and ex_mem_w_a = '1' and OUT_data(15 downto 8) = A_DIEX_OUT) or
288
+						  (li_di_r_c = '1' and ex_mem_w_a = '1' and OUT_data(7 downto 0) = A_DIEX_OUT) else
289
+						  '1';
229 290
 	
230
-	-- Instantiate pipeline Mem_RE
231
-	Mem_RE : pipeline PORT MAP (
232
-			OP_IN => OP_EXMem_OUT,
233
-           A_IN => A_EXMem_OUT,
234
-           B_IN => B_EXMem_OUT,
235
-           C_IN => x"00",
236
-			  CLK => CLK,
237
-			  A_OUT => A_MemRE_OUT,
238
-			  B_OUT => B_MemRE_OUT,
239
-			  C_OUT => open,
240
-			  OP_OUT => OP_MemRE_OUT
241
-           );
242
-	process
291
+    	process
243 292
 		begin
244 293
 			wait until rising_edge(CLK);
245 294
 			if rst = '0' then
246 295
 				IP <= x"00";
247 296
 			else
248
-				IP <= IP + "00000001";
297
+				if alea = '1' then
298
+					IP <= IP + "00000001";
299
+				end if;
249 300
 			end if;
250 301
 		end process;
251
-	
252
-end Behavioral;
253
-
302
+    	
303
+    end Behavioral;

+ 52
- 0
xilinx/ALU/processeur.xst View File

@@ -0,0 +1,52 @@
1
+set -tmpdir "xst/projnav.tmp"
2
+set -xsthdpdir "xst"
3
+run
4
+-ifn processeur.prj
5
+-ofn processeur
6
+-ofmt NGC
7
+-p xc6slx16-3-csg324
8
+-top processeur
9
+-opt_mode Speed
10
+-opt_level 1
11
+-power NO
12
+-iuc NO
13
+-keep_hierarchy No
14
+-netlist_hierarchy As_Optimized
15
+-rtlview Yes
16
+-glob_opt AllClockNets
17
+-read_cores YES
18
+-write_timing_constraints NO
19
+-cross_clock_analysis NO
20
+-hierarchy_separator /
21
+-bus_delimiter <>
22
+-case Maintain
23
+-slice_utilization_ratio 100
24
+-bram_utilization_ratio 100
25
+-dsp_utilization_ratio 100
26
+-lc Auto
27
+-reduce_control_sets Auto
28
+-fsm_extract YES -fsm_encoding Auto
29
+-safe_implementation No
30
+-fsm_style LUT
31
+-ram_extract Yes
32
+-ram_style Auto
33
+-rom_extract Yes
34
+-shreg_extract YES
35
+-rom_style Auto
36
+-auto_bram_packing NO
37
+-resource_sharing YES
38
+-async_to_sync NO
39
+-shreg_min_size 2
40
+-use_dsp48 Auto
41
+-iobuf YES
42
+-max_fanout 100000
43
+-bufg 16
44
+-register_duplication YES
45
+-register_balancing No
46
+-optimize_primitives NO
47
+-use_clock_enable Auto
48
+-use_sync_set Auto
49
+-use_sync_reset Auto
50
+-iob Auto
51
+-equivalent_register_removal YES
52
+-slice_utilization_ratio_maxmargin 5

+ 404
- 0
xilinx/ALU/processeur_envsettings.html View File

@@ -0,0 +1,404 @@
1
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3
+<center><big><big><b>System Settings</b></big></big></center><br>
4
+<A NAME="Environment Settings"></A>
5
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8
+</tr>
9
+<tr bgcolor='#ffff99'>
10
+<td><b>Environment Variable</b></td>
11
+<td><b>xst</b></td>
12
+<td><b>ngdbuild</b></td>
13
+<td><b>map</b></td>
14
+<td><b>par</b></td>
15
+</tr>
16
+<tr>
17
+<td>LD_LIBRARY_PATH</td>
18
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:<br>/usr/local/insa/lib:<br>$LD_LIBRARY_PATH</td>
19
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:<br>/usr/local/insa/lib:<br>$LD_LIBRARY_PATH</td>
20
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
21
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
22
+</tr>
23
+<tr>
24
+<td>PATH</td>
25
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:<br>/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:<br>/usr/local/insa/shared/opam/system/bin:<br>/usr/local/insa/lustre-v4-III-dc-linux64/bin:<br>/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:<br>/usr/local/insa/anaconda/bin:<br>/usr/local/insa/bin:<br>/usr/local/insa/sbin:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/sbin:<br>/usr/bin:<br>/sbin:<br>/bin:<br>/usr/games:<br>/usr/local/games:<br>/usr/local/insa/tina/bin:<br>/snap/bin</td>
26
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:<br>/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:<br>/usr/local/insa/shared/opam/system/bin:<br>/usr/local/insa/lustre-v4-III-dc-linux64/bin:<br>/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:<br>/usr/local/insa/anaconda/bin:<br>/usr/local/insa/bin:<br>/usr/local/insa/sbin:<br>/usr/local/sbin:<br>/usr/local/bin:<br>/usr/sbin:<br>/usr/bin:<br>/sbin:<br>/bin:<br>/usr/games:<br>/usr/local/games:<br>/usr/local/insa/tina/bin:<br>/snap/bin</td>
27
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
28
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
29
+</tr>
30
+<tr>
31
+<td>XILINX</td>
32
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/</td>
33
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/</td>
34
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
35
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
36
+</tr>
37
+<tr>
38
+<td>XILINXD_LICENSE_FILE</td>
39
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic</td>
40
+<td>/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic</td>
41
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
42
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
43
+</tr>
44
+</TABLE>
45
+<A NAME="Synthesis Property Settings"></A>
46
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
47
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
48
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
49
+</tr>
50
+<tr bgcolor='#ffff99'>
51
+<td><b>Switch Name</b></td>
52
+<td><b>Property Name</b></td>
53
+<td><b>Value</b></td>
54
+<td><b>Default Value</b></td>
55
+</tr>
56
+<tr>
57
+<td>-ifn</td>
58
+<td>&nbsp;</td>
59
+<td>processeur.prj</td>
60
+<td>&nbsp;</td>
61
+</tr>
62
+<tr>
63
+<td>-ofn</td>
64
+<td>&nbsp;</td>
65
+<td>processeur</td>
66
+<td>&nbsp;</td>
67
+</tr>
68
+<tr>
69
+<td>-ofmt</td>
70
+<td>&nbsp;</td>
71
+<td>NGC</td>
72
+<td>NGC</td>
73
+</tr>
74
+<tr>
75
+<td>-p</td>
76
+<td>&nbsp;</td>
77
+<td>xc6slx16-3-csg324</td>
78
+<td>&nbsp;</td>
79
+</tr>
80
+<tr>
81
+<td>-top</td>
82
+<td>&nbsp;</td>
83
+<td>processeur</td>
84
+<td>&nbsp;</td>
85
+</tr>
86
+<tr>
87
+<td>-opt_mode</td>
88
+<td>Optimization Goal</td>
89
+<td>Speed</td>
90
+<td>Speed</td>
91
+</tr>
92
+<tr>
93
+<td>-opt_level</td>
94
+<td>Optimization Effort</td>
95
+<td>1</td>
96
+<td>1</td>
97
+</tr>
98
+<tr>
99
+<td>-power</td>
100
+<td>Power Reduction</td>
101
+<td>NO</td>
102
+<td>No</td>
103
+</tr>
104
+<tr>
105
+<td>-iuc</td>
106
+<td>Use synthesis Constraints File</td>
107
+<td>NO</td>
108
+<td>No</td>
109
+</tr>
110
+<tr>
111
+<td>-keep_hierarchy</td>
112
+<td>Keep Hierarchy</td>
113
+<td>No</td>
114
+<td>No</td>
115
+</tr>
116
+<tr>
117
+<td>-netlist_hierarchy</td>
118
+<td>Netlist Hierarchy</td>
119
+<td>As_Optimized</td>
120
+<td>As_Optimized</td>
121
+</tr>
122
+<tr>
123
+<td>-rtlview</td>
124
+<td>Generate RTL Schematic</td>
125
+<td>Yes</td>
126
+<td>No</td>
127
+</tr>
128
+<tr>
129
+<td>-glob_opt</td>
130
+<td>Global Optimization Goal</td>
131
+<td>AllClockNets</td>
132
+<td>AllClockNets</td>
133
+</tr>
134
+<tr>
135
+<td>-read_cores</td>
136
+<td>Read Cores</td>
137
+<td>YES</td>
138
+<td>Yes</td>
139
+</tr>
140
+<tr>
141
+<td>-write_timing_constraints</td>
142
+<td>Write Timing Constraints</td>
143
+<td>NO</td>
144
+<td>No</td>
145
+</tr>
146
+<tr>
147
+<td>-cross_clock_analysis</td>
148
+<td>Cross Clock Analysis</td>
149
+<td>NO</td>
150
+<td>No</td>
151
+</tr>
152
+<tr>
153
+<td>-bus_delimiter</td>
154
+<td>Bus Delimiter</td>
155
+<td>&lt;&gt;</td>
156
+<td>&lt;&gt;</td>
157
+</tr>
158
+<tr>
159
+<td>-slice_utilization_ratio</td>
160
+<td>Slice Utilization Ratio</td>
161
+<td>100</td>
162
+<td>100</td>
163
+</tr>
164
+<tr>
165
+<td>-bram_utilization_ratio</td>
166
+<td>BRAM Utilization Ratio</td>
167
+<td>100</td>
168
+<td>100</td>
169
+</tr>
170
+<tr>
171
+<td>-dsp_utilization_ratio</td>
172
+<td>DSP Utilization Ratio</td>
173
+<td>100</td>
174
+<td>100</td>
175
+</tr>
176
+<tr>
177
+<td>-reduce_control_sets</td>
178
+<td>&nbsp;</td>
179
+<td>Auto</td>
180
+<td>Auto</td>
181
+</tr>
182
+<tr>
183
+<td>-fsm_extract</td>
184
+<td>&nbsp;</td>
185
+<td>YES</td>
186
+<td>Yes</td>
187
+</tr>
188
+<tr>
189
+<td>-fsm_encoding</td>
190
+<td>&nbsp;</td>
191
+<td>Auto</td>
192
+<td>Auto</td>
193
+</tr>
194
+<tr>
195
+<td>-safe_implementation</td>
196
+<td>&nbsp;</td>
197
+<td>No</td>
198
+<td>No</td>
199
+</tr>
200
+<tr>
201
+<td>-fsm_style</td>
202
+<td>&nbsp;</td>
203
+<td>LUT</td>
204
+<td>LUT</td>
205
+</tr>
206
+<tr>
207
+<td>-ram_extract</td>
208
+<td>&nbsp;</td>
209
+<td>Yes</td>
210
+<td>Yes</td>
211
+</tr>
212
+<tr>
213
+<td>-ram_style</td>
214
+<td>&nbsp;</td>
215
+<td>Auto</td>
216
+<td>Auto</td>
217
+</tr>
218
+<tr>
219
+<td>-rom_extract</td>
220
+<td>&nbsp;</td>
221
+<td>Yes</td>
222
+<td>Yes</td>
223
+</tr>
224
+<tr>
225
+<td>-shreg_extract</td>
226
+<td>&nbsp;</td>
227
+<td>YES</td>
228
+<td>Yes</td>
229
+</tr>
230
+<tr>
231
+<td>-rom_style</td>
232
+<td>&nbsp;</td>
233
+<td>Auto</td>
234
+<td>Auto</td>
235
+</tr>
236
+<tr>
237
+<td>-auto_bram_packing</td>
238
+<td>&nbsp;</td>
239
+<td>NO</td>
240
+<td>No</td>
241
+</tr>
242
+<tr>
243
+<td>-resource_sharing</td>
244
+<td>&nbsp;</td>
245
+<td>YES</td>
246
+<td>Yes</td>
247
+</tr>
248
+<tr>
249
+<td>-async_to_sync</td>
250
+<td>&nbsp;</td>
251
+<td>NO</td>
252
+<td>No</td>
253
+</tr>
254
+<tr>
255
+<td>-use_dsp48</td>
256
+<td>&nbsp;</td>
257
+<td>Auto</td>
258
+<td>Auto</td>
259
+</tr>
260
+<tr>
261
+<td>-iobuf</td>
262
+<td>&nbsp;</td>
263
+<td>YES</td>
264
+<td>Yes</td>
265
+</tr>
266
+<tr>
267
+<td>-max_fanout</td>
268
+<td>&nbsp;</td>
269
+<td>100000</td>
270
+<td>100000</td>
271
+</tr>
272
+<tr>
273
+<td>-bufg</td>
274
+<td>&nbsp;</td>
275
+<td>16</td>
276
+<td>16</td>
277
+</tr>
278
+<tr>
279
+<td>-register_duplication</td>
280
+<td>&nbsp;</td>
281
+<td>YES</td>
282
+<td>Yes</td>
283
+</tr>
284
+<tr>
285
+<td>-register_balancing</td>
286
+<td>&nbsp;</td>
287
+<td>No</td>
288
+<td>No</td>
289
+</tr>
290
+<tr>
291
+<td>-optimize_primitives</td>
292
+<td>&nbsp;</td>
293
+<td>NO</td>
294
+<td>No</td>
295
+</tr>
296
+<tr>
297
+<td>-use_clock_enable</td>
298
+<td>&nbsp;</td>
299
+<td>Auto</td>
300
+<td>Auto</td>
301
+</tr>
302
+<tr>
303
+<td>-use_sync_set</td>
304
+<td>&nbsp;</td>
305
+<td>Auto</td>
306
+<td>Auto</td>
307
+</tr>
308
+<tr>
309
+<td>-use_sync_reset</td>
310
+<td>&nbsp;</td>
311
+<td>Auto</td>
312
+<td>Auto</td>
313
+</tr>
314
+<tr>
315
+<td>-iob</td>
316
+<td>&nbsp;</td>
317
+<td>Auto</td>
318
+<td>Auto</td>
319
+</tr>
320
+<tr>
321
+<td>-equivalent_register_removal</td>
322
+<td>&nbsp;</td>
323
+<td>YES</td>
324
+<td>Yes</td>
325
+</tr>
326
+<tr>
327
+<td>-slice_utilization_ratio_maxmargin</td>
328
+<td>&nbsp;</td>
329
+<td>5</td>
330
+<td>0</td>
331
+</tr>
332
+</TABLE>
333
+<A NAME="Translation Property Settings"></A>
334
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
335
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
336
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
337
+</tr>
338
+<tr bgcolor='#ffff99'>
339
+<td><b>Switch Name</b></td>
340
+<td><b>Property Name</b></td>
341
+<td><b>Value</b></td>
342
+<td><b>Default Value</b></td>
343
+</tr>
344
+<tr>
345
+<td>-intstyle</td>
346
+<td>&nbsp;</td>
347
+<td>ise</td>
348
+<td>None</td>
349
+</tr>
350
+<tr>
351
+<td>-dd</td>
352
+<td>&nbsp;</td>
353
+<td>_ngo</td>
354
+<td>None</td>
355
+</tr>
356
+<tr>
357
+<td>-p</td>
358
+<td>&nbsp;</td>
359
+<td>xc6slx16-csg324-3</td>
360
+<td>None</td>
361
+</tr>
362
+</TABLE>
363
+<A NAME="Operating System Information"></A>
364
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
365
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
366
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
367
+</tr>
368
+<tr bgcolor='#ffff99'>
369
+<td><b>Operating System Information</b></td>
370
+<td><b>xst</b></td>
371
+<td><b>ngdbuild</b></td>
372
+<td><b>map</b></td>
373
+<td><b>par</b></td>
374
+</tr>
375
+<tr>
376
+<td>CPU Architecture/Speed</td>
377
+<td>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4277.214 MHz</td>
378
+<td>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz/4276.892 MHz</td>
379
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
380
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
381
+</tr>
382
+<tr>
383
+<td>Host</td>
384
+<td>insa-11291</td>
385
+<td>insa-11291</td>
386
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
387
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
388
+</tr>
389
+<tr>
390
+<td>OS Name</td>
391
+<td>Ubuntu</td>
392
+<td>Ubuntu</td>
393
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
394
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
395
+</tr>
396
+<tr>
397
+<td>OS Release</td>
398
+<td>Ubuntu 18.04.5 LTS</td>
399
+<td>Ubuntu 18.04.5 LTS</td>
400
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
401
+<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
402
+</tr>
403
+</TABLE>
404
+</BODY> </HTML>

+ 23
- 0
xilinx/ALU/processeur_map.map View File

@@ -0,0 +1,23 @@
1
+Release 13.4 Map O.87xd (lin64)
2
+Xilinx Map Application Log File for Design 'processeur'
3
+
4
+Design Information
5
+------------------
6
+Command Line   : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
7
+high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
8
+-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf 
9
+Target Device  : xc6slx16
10
+Target Package : csg324
11
+Target Speed   : -3
12
+Mapper Version : spartan6 -- $Revision: 1.55 $
13
+Mapped Date    : Tue May 18 16:15:07 2021
14
+
15
+ERROR:Map:116 - The design is empty.  No processing will be done.
16
+ERROR:Map:52 - Problem encountered processing RPMs.
17
+
18
+
19
+
20
+Design Summary
21
+--------------
22
+Number of errors   :   2
23
+Number of warnings :   0

+ 31
- 0
xilinx/ALU/processeur_map.mrp View File

@@ -0,0 +1,31 @@
1
+Release 13.4 Map O.87xd (lin64)
2
+Xilinx Mapping Report File for Design 'processeur'
3
+
4
+Design Information
5
+------------------
6
+Command Line   : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol
7
+high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
8
+-pr off -lc off -power off -o processeur_map.ncd processeur.ngd processeur.pcf 
9
+Target Device  : xc6slx16
10
+Target Package : csg324
11
+Target Speed   : -3
12
+Mapper Version : spartan6 -- $Revision: 1.55 $
13
+Mapped Date    : Tue May 18 16:15:07 2021
14
+
15
+Design Summary
16
+--------------
17
+Number of errors   :   2
18
+Number of warnings :   0
19
+
20
+Section 1 - Errors
21
+------------------
22
+ERROR:Map:116 - The design is empty.  No processing will be done.
23
+ERROR:Map:52 - Problem encountered processing RPMs.
24
+
25
+
26
+
27
+Section 2 - Warnings
28
+--------------------
29
+
30
+Section 3 - Informational
31
+-------------------------

+ 67
- 0
xilinx/ALU/processeur_ngdbuild.xrpt View File

@@ -0,0 +1,67 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
2
+<document OS="lin64" product="ISE" version="13.4">
3
+
4
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
5
+    The structure and the elements are likely to change over the next few releases.
6
+    This means code written to parse this file will need to be revisited each subsequent release.-->
7
+
8
+  <application stringID="NgdBuild" timeStamp="Tue May 18 16:15:05 2021">
9
+    <section stringID="User_Env">
10
+      <table stringID="User_EnvVar">
11
+        <column stringID="variable"/>
12
+        <column stringID="value"/>
13
+        <row stringID="row" value="0">
14
+          <item stringID="variable" value="LD_LIBRARY_PATH"/>
15
+          <item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//lib/lin64:/usr/local/insa/lib:$LD_LIBRARY_PATH"/>
16
+        </row>
17
+        <row stringID="row" value="1">
18
+          <item stringID="variable" value="XILINXD_LICENSE_FILE"/>
19
+          <item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/common/licenses/Xilinx.lic"/>
20
+        </row>
21
+        <row stringID="row" value="2">
22
+          <item stringID="variable" value="PATH"/>
23
+          <item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE//bin/lin64:/mnt/commetud/GEI/OCaml/.opam/4.08.1/bin:/usr/local/insa/shared/opam/system/bin:/usr/local/insa/lustre-v4-III-dc-linux64/bin:/usr/local/insa/arm-ada/compilateur/gcc-arm-none-eabi/bin:/usr/local/insa/anaconda/bin:/usr/local/insa/bin:/usr/local/insa/sbin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/usr/local/insa/tina/bin:/snap/bin"/>
24
+        </row>
25
+        <row stringID="row" value="3">
26
+          <item stringID="variable" value="XILINX"/>
27
+          <item stringID="value" value="/usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/"/>
28
+        </row>
29
+      </table>
30
+      <item stringID="User_EnvOs" value="OS Information">
31
+        <item stringID="User_EnvOsname" value="Ubuntu"/>
32
+        <item stringID="User_EnvOsrelease" value="Ubuntu 18.04.5 LTS"/>
33
+      </item>
34
+      <item stringID="User_EnvHost" value="insa-11291"/>
35
+      <table stringID="User_EnvCpu">
36
+        <column stringID="arch"/>
37
+        <column stringID="speed"/>
38
+        <row stringID="row" value="0">
39
+          <item stringID="arch" value="Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz"/>
40
+          <item stringID="speed" value="4276.892 MHz"/>
41
+        </row>
42
+      </table>
43
+    </section>
44
+    <task stringID="NGDBUILD_OPTION_SUMMARY">
45
+      <section stringID="NGDBUILD_OPTION_SUMMARY">
46
+        <item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
47
+        <item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
48
+        <item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx16-csg324-3"/>
49
+      </section>
50
+    </task>
51
+    <task stringID="NGDBUILD_REPORT">
52
+      <section stringID="NGDBUILD_DESIGN_SUMMARY">
53
+        <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
54
+        <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
55
+        <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="1"/>
56
+        <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
57
+        <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
58
+      </section>
59
+      <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"/>
60
+      <section stringID="NGDBUILD_POST_UNISIM_SUMMARY"/>
61
+      <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
62
+        <section stringID="NGDBUILD_CORE_INSTANCES"/>
63
+      </section>
64
+    </task>
65
+  </application>
66
+
67
+</document>

+ 18
- 11
xilinx/ALU/processeur_summary.html View File

@@ -2,7 +2,7 @@
2 2
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 3
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4 4
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5
-<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status</B></TD></TR>
5
+<TD ALIGN=CENTER COLSPAN='4'><B>processeur Project Status (05/18/2021 - 16:15:09)</B></TD></TR>
6 6
 <TR ALIGN=LEFT>
7 7
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8 8
 <TD>ALU.