foussats/projet_systeme
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

compilateur ok + alu ok + br a finir

Browse source
This commit is contained in:
Foussats Morgane 2021-04-13 12:18:28 +02:00
parent 17419e1663
commit 56676de078
72 changed files with 76482 additions and 1999 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

BIN
a.out
View file

Binary file not shown.

1437
analyse_syntaxique.output
View file

File diff suppressed because it is too large Load diff

1838
analyse_syntaxique.tab.c
View file

File diff suppressed because it is too large Load diff

159
analyse_syntaxique.tab.h
View file

@ -1,14 +1,13 @@
/* A Bison parser, made by GNU Bison 2.3. */
/* A Bison parser, made by GNU Bison 3.0.4. */
/* Skeleton interface for Bison's Yacc-like parsers in C
/* Bison interface for Yacc-like parsers in C
Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -16,9 +15,7 @@
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* As a special exception, you may create a larger work that contains
part or all of the Bison parser skeleton and distribute that work
@ -33,97 +30,77 @@
This special exception was added by the Free Software Foundation in
version 2.2 of Bison. */
/* Tokens. */
#ifndef YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
# define YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
/* Debug traces. */
#ifndef YYDEBUG
# define YYDEBUG 1
#endif
#if YYDEBUG
extern int yydebug;
#endif
/* Token type. */
#ifndef YYTOKENTYPE
# define YYTOKENTYPE
/* Put the tokens into the symbol table, so that GDB and other debuggers
know about them. */
enum yytokentype {
tENTIER = 258,
tENTIEREXP = 259,
tADD = 260,
tSUB = 261,
tMUL = 262,
tDIV = 263,
tPO = 264,
tPF = 265,
tAO = 266,
tAF = 267,
tERROR = 268,
tPV = 269,
tVIRGULE = 270,
tAFFECTATION = 271,
tEGAL = 272,
tDIFF = 273,
tLT = 274,
tGT = 275,
tGTE = 276,
tLTE = 277,
tMAIN = 278,
tINT = 279,
tPRINT = 280,
tRETURN = 281,
tOR = 282,
tAND = 283,
tIF = 284,
tELSE = 285,
tWHILE = 286,
tCONST = 287,
tVAR = 288,
tNOT = 289
};
enum yytokentype
{
tENTIER = 258,
tENTIEREXP = 259,
tADD = 260,
tSUB = 261,
tMUL = 262,
tDIV = 263,
tPO = 264,
tPF = 265,
tAO = 266,
tAF = 267,
tERROR = 268,
tPV = 269,
tVIRGULE = 270,
tAFFECTATION = 271,
tEGAL = 272,
tDIFF = 273,
tLT = 274,
tGT = 275,
tGTE = 276,
tLTE = 277,
tMAIN = 278,
tINT = 279,
tPRINT = 280,
tRETURN = 281,
tOR = 282,
tAND = 283,
tIF = 284,
tELSE = 285,
tWHILE = 286,
tCONST = 287,
tVAR = 288,
tNOT = 289
};
#endif
/* Tokens. */
#define tENTIER 258
#define tENTIEREXP 259
#define tADD 260
#define tSUB 261
#define tMUL 262
#define tDIV 263
#define tPO 264
#define tPF 265
#define tAO 266
#define tAF 267
#define tERROR 268
#define tPV 269
#define tVIRGULE 270
#define tAFFECTATION 271
#define tEGAL 272
#define tDIFF 273
#define tLT 274
#define tGT 275
#define tGTE 276
#define tLTE 277
#define tMAIN 278
#define tINT 279
#define tPRINT 280
#define tRETURN 281
#define tOR 282
#define tAND 283
#define tIF 284
#define tELSE 285
#define tWHILE 286
#define tCONST 287
#define tVAR 288
#define tNOT 289
/* Value type. */
#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
typedef union YYSTYPE
#line 1 "analyse_syntaxique.y"
union YYSTYPE
{
#line 1 "analyse_syntaxique.y" /* yacc.c:1909 */
int nombre;
char id[30];
}
/* Line 1529 of yacc.c. */
#line 122 "analyse_syntaxique.tab.h"
YYSTYPE;
# define yystype YYSTYPE /* obsolescent; will be withdrawn */
# define YYSTYPE_IS_DECLARED 1
#line 94 "analyse_syntaxique.tab.h" /* yacc.c:1909 */
};
typedef union YYSTYPE YYSTYPE;
# define YYSTYPE_IS_TRIVIAL 1
# define YYSTYPE_IS_DECLARED 1
#endif
extern YYSTYPE yylval;
int yyparse (void);
#endif /* !YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED */

12
analyse_syntaxique.y
View file

@ -22,6 +22,7 @@ int whileCondition;
%type<nombre> E
%type<nombre> Return
%type<nombre> Cond
%type<nombre> While
@ -149,12 +150,11 @@ Else : tELSE tAO Instructions tAF {printf("else\n");} ;
Else : ;
Else : tELSE tIF tPO Cond tPF tAO Instructions tAF Else {printf("elsif\n");} ;
/*While : tWHILE tPO {
$2 = array.index + 1 ;
} Cond tPF {*/
While : tWHILE tPO Cond tPF {
//gen_jmpf(&table, &array, $3, -1);
generate_instruction_2(&array, JMF, $3, -1);
While : tWHILE tPO {
$2 = array.index ;
} Cond tPF {
//gen_jmpf(&table, &array, $4, -1);
generate_instruction_2(&array, JMF, $4, -1);
free_temp(&table);
$1 = array.index;
}

2
instructions.txt
View file

@ -8,7 +8,7 @@
7 JPF 49 10
8 AFC 49 1
9 AFC 49 4
10 JPM 4
10 JPM 5
11 CPY 49 1
12 PRI 49
13 AFC 49 5

448
lex.yy.c
View file

File diff suppressed because it is too large Load diff

101
xilinx/ALU/ALU.gise Normal file
View file

@ -0,0 +1,101 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ALU.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="alu_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="alu_test_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1618303334" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="-3594876569575637225" xil_pn:start_ts="1618303334">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1618303356">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618304610">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-6587339501330506153" xil_pn:start_ts="1618304817">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1575583835443101483" xil_pn:start_ts="1618304817">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-8229480169080511278" xil_pn:start_ts="1618303356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618304610">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1618304818" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="5625932807789681934" xil_pn:start_ts="1618304817">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1618304818" xil_pn:in_ck="-4068278894953614943" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5179862647015444475" xil_pn:start_ts="1618304818">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
</transforms>
</generated_project>

410
xilinx/ALU/ALU.xise Normal file
View file

@ -0,0 +1,410 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx16" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|alu|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="alu.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/alu" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="alu" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="alu_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="alu" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|alu_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-04-13T10:09:14" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E745AC3463D83535AAF1ABA5736091BC" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

18
xilinx/ALU/_xmsgs/pn_parser.xmsgs Normal file
View file

@ -0,0 +1,18 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd</arg>&quot; Line <arg fmt="%d" index="2">47</arg>. <arg fmt="%s" index="3">Syntax error near &quot;CLK&quot;.</arg>
</msg>
</messages>

74
xilinx/ALU/alu.vhd Normal file
View file

@ -0,0 +1,74 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:12:38 04/13/2021
-- Design Name:
-- Module Name: alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (7 downto 0));
end alu;
architecture Behavioral of alu is
signal A9: STD_LOGIC_VECTOR(8 downto 0);
signal B9: STD_LOGIC_VECTOR(8 downto 0);
signal ADD: STD_LOGIC_VECTOR(8 downto 0);
signal SUB: STD_LOGIC_VECTOR(8 downto 0);
signal MUL: STD_LOGIC_VECTOR(15 downto 0);
signal SBIS: STD_LOGIC_VECTOR(7 downto 0);
begin
A9 <= "0"& A;
B9 <= "0"& B;
ADD <= A9 + B9;
SUB <= A9 - B9;
MUL <= A * B;
SBIS <= ADD(7 downto 0) when Ctrl_Alu = "01" else
SUB(7 downto 0) when Ctrl_Alu = "10" else
MUL(7 downto 0) when Ctrl_Alu = "11" else
(others => '0');
O <= '1' when MUL(15 downto 8) /= "00000000" and Ctrl_Alu = "011" else
'0';
C <= '1' when ADD(8) = '1' and Ctrl_Alu = "01" else
'0';
N <= '1' when SUB(8) = '1' and Ctrl_Alu = "10" else
'0';
Z <= '1' when SBIS = "00000000" else
'0';
S <= SBIS;
end Behavioral;

BIN
xilinx/ALU/alu_isim_beh.exe Executable file
View file

Binary file not shown.

BIN
xilinx/ALU/alu_isim_beh1.wdb Normal file
View file

Binary file not shown.

80
xilinx/ALU/alu_summary.html Normal file
View file

@ -0,0 +1,80 @@
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>alu Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ALU.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>alu</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx16-3csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. avr. 13 11:14:16 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 04/13/2021 - 11:53:22</center>
</BODY></HTML>

100
xilinx/ALU/alu_test.vhd Normal file
View file

@ -0,0 +1,100 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:50:53 04/13/2021
-- Design Name:
-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY alu_test IS
END alu_test;
ARCHITECTURE behavior OF alu_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Ctrl_Alu : IN std_logic_vector(2 downto 0);
N : OUT std_logic;
O : OUT std_logic;
Z : OUT std_logic;
C : OUT std_logic;
S : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal Ctrl_Alu : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal N : std_logic;
signal O : std_logic;
signal Z : std_logic;
signal C : std_logic;
signal S : std_logic_vector(7 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
A => A,
B => B,
Ctrl_Alu => Ctrl_Alu,
N => N,
O => O,
Z => Z,
C => C,
S => S
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
B<="11111111";
A<="11111111";
Ctrl_Alu<="001" after 4 ns;
Ctrl_Alu<="010" after 8 ns;
Ctrl_Alu<="011" after 12 ns;
wait;
end process;
END;

2
xilinx/ALU/alu_test_beh.prj Normal file
View file

@ -0,0 +1,2 @@
vhdl work "alu.vhd"
vhdl work "alu_test.vhd"

BIN
xilinx/ALU/alu_test_isim_beh.exe Executable file
View file

Binary file not shown.

BIN
xilinx/ALU/alu_test_isim_beh.wdb Normal file
View file

Binary file not shown.

61
xilinx/ALU/br.vhd Normal file
View file

@ -0,0 +1,61 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:29:59 04/13/2021
-- Design Name:
-- Module Name: br - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
--use UNISIM.VComponents.all;
entity br is
Port ( A_addr : in STD_LOGIC_VECTOR (3 downto 0);
B_addr : in STD_LOGIC_VECTOR (3 downto 0);
W_addr : in STD_LOGIC_VECTOR (3 downto 0);
W : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (7 downto 0);
QB : out STD_LOGIC_VECTOR (7 downto 0));
end br;
architecture Behavioral of br is
type reg is array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
signal registres: reg;
begin
process
begin
wait until CLK'event CLK = '1';
if W = '1' then
registres(W_addr) <= Data;
else
end if;
if RST='0' then
QA <= "00000000";
QB <= "00000000";
end if;
end process;
end Behavioral;

25
xilinx/ALU/fuse.log Normal file
View file

@ -0,0 +1,25 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test"
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Determining compilation order of HDL files
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 98500 KB
Fuse CPU Usage: 810 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package numeric_std
Compiling architecture behavioral of entity alu [alu_default]
Compiling architecture behavior of entity alu_test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe
Fuse Memory Usage: 1722952 KB
Fuse CPU Usage: 920 ms
GCC CPU Usage: 80 ms

9
xilinx/ALU/fuse.xmsgs Normal file
View file

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

1
xilinx/ALU/fuseRelaunch.cmd Normal file
View file

@ -0,0 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test"

131
xilinx/ALU/iseconfig/ALU.projectmgr Normal file
View file

@ -0,0 +1,131 @@
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="ALU" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>ALU</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000200000064ffffffff000000810000000300000002000001040000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>ALU</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004f0000000100000000000000390000000100000000000000830000000100000000000002960000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000010001000100000000000000000000000064ffffffff000000810000000000000001000003a10000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode></ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000b0000000020000000000000000000000000200000064ffffffff000000810000000300000002000000b00000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>View Compilation Log</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>View Compilation Log</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<SourceProcessView>000000ff0000000000000002000001620000011b01000000040100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
</Project>

215
xilinx/ALU/iseconfig/alu.xreport Normal file
View file

@ -0,0 +1,215 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2021-04-13T11:53:22</DateModified>
<ModuleName>alu</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
<DateInitialized>2021-04-13T10:12:38</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="alu_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="alu_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="alu_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="alu_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="alu_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="alu.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="alu_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="alu_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="alu.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="alu_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="alu.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="alu.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="alu.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="alu_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="alu.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="alu.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="alu.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="alu.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="alu.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/alu_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/alu_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/alu_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="alu_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/alu_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="alu.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/alu_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>

3
xilinx/ALU/isim.cmd Normal file
View file

@ -0,0 +1,3 @@
onerror {resume}
wave add /
run 1000 ns;

33
xilinx/ALU/isim.log Normal file
View file

@ -0,0 +1,33 @@
ISim log file
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
# exit 0

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe Executable file
View file

Binary file not shown.

0
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimcrash.log Normal file
View file

29
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimkernel.log Normal file
View file

@ -0,0 +1,29 @@
Command line:
alu_isim_beh.exe
-simmode gui
-simrunnum 1
-socket 46007
Tue Apr 13 11:05:00 2021
Elaboration Time: 0 sec
Current Memory Usage: 181.678 Meg
Total Signals : 14
Total Nets : 91
Total Signal Drivers : 11
Total Blocks : 5
Total Primitive Blocks : 5
Total Processes : 11
Total Traceable Variables : 15
Total Scalar Nets and Variables : 592
Total Line Count : 11
Total Simulation Time: 0.08 sec
Current Memory Usage: 257.18 Meg
Tue Apr 13 11:05:21 2021

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/netId1.dat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/tmp_save/_1 Normal file
View file

Binary file not shown.

931
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.c Normal file
View file

@ -0,0 +1,931 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_3620187407;
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
static void work_a_2725559894_3212880686_p_0(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(54, ng0);
LAB3: t1 = (t0 + 11471);
t3 = (t0 + 1032U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11224U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7304);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7064);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_1(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(55, ng0);
LAB3: t1 = (t0 + 11472);
t3 = (t0 + 1192U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11240U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7368);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7080);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(56, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7096);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_3(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(57, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7496);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7112);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(58, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 11224U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 11240U);
t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (16U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 16U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7128);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(16U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_5(char *t0)
{
char t5[16];
char t23[16];
char t41[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
unsigned int t12;
unsigned int t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t24;
char *t25;
int t26;
unsigned int t27;
unsigned char t28;
char *t29;
unsigned int t30;
unsigned int t31;
char *t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
char *t38;
char *t39;
char *t42;
char *t43;
int t44;
unsigned int t45;
unsigned char t46;
char *t47;
unsigned int t48;
unsigned int t49;
char *t50;
char *t51;
char *t52;
char *t53;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
LAB0: xsi_set_current_line(60, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t1 = (t0 + 11256U);
t3 = (t0 + 11473);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 1;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (1 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4: t19 = (t0 + 1352U);
t20 = *((char **)t19);
t19 = (t0 + 11256U);
t21 = (t0 + 11475);
t24 = (t23 + 0U);
t25 = (t24 + 0U);
*((int *)t25) = 0;
t25 = (t24 + 4U);
*((int *)t25) = 1;
t25 = (t24 + 8U);
*((int *)t25) = 1;
t26 = (1 - 0);
t27 = (t26 * 1);
t27 = (t27 + 1);
t25 = (t24 + 12U);
*((unsigned int *)t25) = t27;
t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
if (t28 != 0)
goto LAB5;
LAB6: t37 = (t0 + 1352U);
t38 = *((char **)t37);
t37 = (t0 + 11256U);
t39 = (t0 + 11477);
t42 = (t41 + 0U);
t43 = (t42 + 0U);
*((int *)t43) = 0;
t43 = (t42 + 4U);
*((int *)t43) = 1;
t43 = (t42 + 8U);
*((int *)t43) = 1;
t44 = (1 - 0);
t45 = (t44 * 1);
t45 = (t45 + 1);
t43 = (t42 + 12U);
*((unsigned int *)t43) = t45;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
if (t46 != 0)
goto LAB7;
LAB8:
LAB9: t55 = xsi_get_transient_memory(8U);
memset(t55, 0, 8U);
t56 = t55;
memset(t56, (unsigned char)2, 8U);
t57 = (t0 + 7624);
t58 = (t57 + 56U);
t59 = *((char **)t58);
t60 = (t59 + 56U);
t61 = *((char **)t60);
memcpy(t61, t55, 8U);
xsi_driver_first_trans_fast(t57);
LAB2: t62 = (t0 + 7144);
*((int *)t62) = 1;
LAB1: return;
LAB3: t7 = (t0 + 2632U);
t11 = *((char **)t7);
t9 = (8 - 7);
t12 = (t9 * 1U);
t13 = (0 + t12);
t7 = (t11 + t13);
t14 = (t0 + 7624);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t7, 8U);
xsi_driver_first_trans_fast(t14);
goto LAB2;
LAB5: t25 = (t0 + 2792U);
t29 = *((char **)t25);
t27 = (8 - 7);
t30 = (t27 * 1U);
t31 = (0 + t30);
t25 = (t29 + t31);
t32 = (t0 + 7624);
t33 = (t32 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
memcpy(t36, t25, 8U);
xsi_driver_first_trans_fast(t32);
goto LAB2;
LAB7: t43 = (t0 + 2952U);
t47 = *((char **)t43);
t45 = (15 - 7);
t48 = (t45 * 1U);
t49 = (0 + t48);
t43 = (t47 + t49);
t50 = (t0 + 7624);
t51 = (t50 + 56U);
t52 = *((char **)t51);
t53 = (t52 + 56U);
t54 = *((char **)t53);
memcpy(t54, t43, 8U);
xsi_driver_first_trans_fast(t50);
goto LAB2;
LAB10: goto LAB2;
}
static void work_a_2725559894_3212880686_p_6(char *t0)
{
char t7[16];
char t13[16];
char t21[16];
unsigned char t1;
char *t2;
char *t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
char *t14;
char *t15;
int t16;
unsigned char t17;
char *t18;
char *t19;
char *t22;
char *t23;
int t24;
unsigned char t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
char *t32;
char *t33;
char *t34;
char *t35;
LAB0: xsi_set_current_line(64, ng0);
t2 = (t0 + 2952U);
t3 = *((char **)t2);
t4 = (15 - 15);
t5 = (t4 * 1U);
t6 = (0 + t5);
t2 = (t3 + t6);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 15;
t9 = (t8 + 4U);
*((int *)t9) = 8;
t9 = (t8 + 8U);
*((int *)t9) = -1;
t10 = (8 - 15);
t11 = (t10 * -1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11479);
t14 = (t13 + 0U);
t15 = (t14 + 0U);
*((int *)t15) = 0;
t15 = (t14 + 4U);
*((int *)t15) = 7;
t15 = (t14 + 8U);
*((int *)t15) = 1;
t16 = (7 - 0);
t11 = (t16 * 1);
t11 = (t11 + 1);
t15 = (t14 + 12U);
*((unsigned int *)t15) = t11;
t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
if (t17 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t30 = (t0 + 7688);
t31 = (t30 + 56U);
t32 = *((char **)t31);
t33 = (t32 + 56U);
t34 = *((char **)t33);
*((unsigned char *)t34) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t30);
LAB2: t35 = (t0 + 7160);
*((int *)t35) = 1;
LAB1: return;
LAB3: t23 = (t0 + 7688);
t26 = (t23 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
*((unsigned char *)t29) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t23);
goto LAB2;
LAB5: t15 = (t0 + 1352U);
t18 = *((char **)t15);
t15 = (t0 + 11256U);
t19 = (t0 + 11487);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
t23 = (t22 + 4U);
*((int *)t23) = 2;
t23 = (t22 + 8U);
*((int *)t23) = 1;
t24 = (2 - 0);
t11 = (t24 * 1);
t11 = (t11 + 1);
t23 = (t22 + 12U);
*((unsigned int *)t23) = t11;
t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
t1 = t25;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_7(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(66, ng0);
t2 = (t0 + 2632U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7752);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7176);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7752);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11490);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_8(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(68, ng0);
t2 = (t0 + 2792U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7816);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7192);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7816);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11492);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_9(char *t0)
{
char t5[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
LAB0: xsi_set_current_line(70, ng0);
t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 11368U);
t3 = (t0 + 11494);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 7;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (7 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4:
LAB5: t15 = (t0 + 7880);
t16 = (t15 + 56U);
t17 = *((char **)t16);
t18 = (t17 + 56U);
t19 = *((char **)t18);
*((unsigned char *)t19) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t15);
LAB2: t20 = (t0 + 7208);
*((int *)t20) = 1;
LAB1: return;
LAB3: t7 = (t0 + 7880);
t11 = (t7 + 56U);
t12 = *((char **)t11);
t13 = (t12 + 56U);
t14 = *((char **)t13);
*((unsigned char *)t14) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t7);
goto LAB2;
LAB6: goto LAB2;
}
static void work_a_2725559894_3212880686_p_10(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(72, ng0);
LAB3: t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 7944);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 7224);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_2725559894_3212880686_init()
{
static char *pe[] = {(void *)work_a_2725559894_3212880686_p_0,(void *)work_a_2725559894_3212880686_p_1,(void *)work_a_2725559894_3212880686_p_2,(void *)work_a_2725559894_3212880686_p_3,(void *)work_a_2725559894_3212880686_p_4,(void *)work_a_2725559894_3212880686_p_5,(void *)work_a_2725559894_3212880686_p_6,(void *)work_a_2725559894_3212880686_p_7,(void *)work_a_2725559894_3212880686_p_8,(void *)work_a_2725559894_3212880686_p_9,(void *)work_a_2725559894_3212880686_p_10};
xsi_register_didat("work_a_2725559894_3212880686", "isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.lin64.o Normal file
View file

Binary file not shown.

48
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.c Normal file
View file

@ -0,0 +1,48 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
char *IEEE_P_3620187407;
char *IEEE_P_3499444699;
char *IEEE_P_1242562249;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_2725559894_3212880686_init();
xsi_register_tops("work_a_2725559894_3212880686");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
return xsi_run_simulation(argc, argv);
}

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.lin64.o Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/alu_test_isim_beh.exe Executable file
View file

Binary file not shown.

0
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimcrash.log Normal file
View file

29
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimkernel.log Normal file
View file

@ -0,0 +1,29 @@
Command line:
alu_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 38597
Tue Apr 13 11:10:10 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 181.686 Meg
Total Signals : 22
Total Nets : 91
Total Signal Drivers : 14
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 12
Total Traceable Variables : 15
Total Scalar Nets and Variables : 592
Total Line Count : 18
Total Simulation Time: 0.19 sec
Current Memory Usage: 257.188 Meg
Tue Apr 13 11:14:15 2021

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/netId.dat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/tmp_save/_1 Normal file
View file

Binary file not shown.

931
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c Normal file
View file

@ -0,0 +1,931 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_3620187407;
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
static void work_a_0832606739_3212880686_p_0(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(54, ng0);
LAB3: t1 = (t0 + 11471);
t3 = (t0 + 1032U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11224U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7304);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7064);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_1(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(55, ng0);
LAB3: t1 = (t0 + 11472);
t3 = (t0 + 1192U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11240U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7368);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7080);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(56, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7096);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_3(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(57, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7496);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7112);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(58, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 11224U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 11240U);
t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (16U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 16U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7128);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(16U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_5(char *t0)
{
char t5[16];
char t23[16];
char t41[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
unsigned int t12;
unsigned int t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t24;
char *t25;
int t26;
unsigned int t27;
unsigned char t28;
char *t29;
unsigned int t30;
unsigned int t31;
char *t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
char *t38;
char *t39;
char *t42;
char *t43;
int t44;
unsigned int t45;
unsigned char t46;
char *t47;
unsigned int t48;
unsigned int t49;
char *t50;
char *t51;
char *t52;
char *t53;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
LAB0: xsi_set_current_line(60, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t1 = (t0 + 11256U);
t3 = (t0 + 11473);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 1;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (1 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4: t19 = (t0 + 1352U);
t20 = *((char **)t19);
t19 = (t0 + 11256U);
t21 = (t0 + 11475);
t24 = (t23 + 0U);
t25 = (t24 + 0U);
*((int *)t25) = 0;
t25 = (t24 + 4U);
*((int *)t25) = 1;
t25 = (t24 + 8U);
*((int *)t25) = 1;
t26 = (1 - 0);
t27 = (t26 * 1);
t27 = (t27 + 1);
t25 = (t24 + 12U);
*((unsigned int *)t25) = t27;
t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
if (t28 != 0)
goto LAB5;
LAB6: t37 = (t0 + 1352U);
t38 = *((char **)t37);
t37 = (t0 + 11256U);
t39 = (t0 + 11477);
t42 = (t41 + 0U);
t43 = (t42 + 0U);
*((int *)t43) = 0;
t43 = (t42 + 4U);
*((int *)t43) = 1;
t43 = (t42 + 8U);
*((int *)t43) = 1;
t44 = (1 - 0);
t45 = (t44 * 1);
t45 = (t45 + 1);
t43 = (t42 + 12U);
*((unsigned int *)t43) = t45;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
if (t46 != 0)
goto LAB7;
LAB8:
LAB9: t55 = xsi_get_transient_memory(8U);
memset(t55, 0, 8U);
t56 = t55;
memset(t56, (unsigned char)2, 8U);
t57 = (t0 + 7624);
t58 = (t57 + 56U);
t59 = *((char **)t58);
t60 = (t59 + 56U);
t61 = *((char **)t60);
memcpy(t61, t55, 8U);
xsi_driver_first_trans_fast(t57);
LAB2: t62 = (t0 + 7144);
*((int *)t62) = 1;
LAB1: return;
LAB3: t7 = (t0 + 2632U);
t11 = *((char **)t7);
t9 = (8 - 7);
t12 = (t9 * 1U);
t13 = (0 + t12);
t7 = (t11 + t13);
t14 = (t0 + 7624);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t7, 8U);
xsi_driver_first_trans_fast(t14);
goto LAB2;
LAB5: t25 = (t0 + 2792U);
t29 = *((char **)t25);
t27 = (8 - 7);
t30 = (t27 * 1U);
t31 = (0 + t30);
t25 = (t29 + t31);
t32 = (t0 + 7624);
t33 = (t32 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
memcpy(t36, t25, 8U);
xsi_driver_first_trans_fast(t32);
goto LAB2;
LAB7: t43 = (t0 + 2952U);
t47 = *((char **)t43);
t45 = (15 - 7);
t48 = (t45 * 1U);
t49 = (0 + t48);
t43 = (t47 + t49);
t50 = (t0 + 7624);
t51 = (t50 + 56U);
t52 = *((char **)t51);
t53 = (t52 + 56U);
t54 = *((char **)t53);
memcpy(t54, t43, 8U);
xsi_driver_first_trans_fast(t50);
goto LAB2;
LAB10: goto LAB2;
}
static void work_a_0832606739_3212880686_p_6(char *t0)
{
char t7[16];
char t13[16];
char t21[16];
unsigned char t1;
char *t2;
char *t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
char *t14;
char *t15;
int t16;
unsigned char t17;
char *t18;
char *t19;
char *t22;
char *t23;
int t24;
unsigned char t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
char *t32;
char *t33;
char *t34;
char *t35;
LAB0: xsi_set_current_line(64, ng0);
t2 = (t0 + 2952U);
t3 = *((char **)t2);
t4 = (15 - 15);
t5 = (t4 * 1U);
t6 = (0 + t5);
t2 = (t3 + t6);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 15;
t9 = (t8 + 4U);
*((int *)t9) = 8;
t9 = (t8 + 8U);
*((int *)t9) = -1;
t10 = (8 - 15);
t11 = (t10 * -1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11479);
t14 = (t13 + 0U);
t15 = (t14 + 0U);
*((int *)t15) = 0;
t15 = (t14 + 4U);
*((int *)t15) = 7;
t15 = (t14 + 8U);
*((int *)t15) = 1;
t16 = (7 - 0);
t11 = (t16 * 1);
t11 = (t11 + 1);
t15 = (t14 + 12U);
*((unsigned int *)t15) = t11;
t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
if (t17 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t30 = (t0 + 7688);
t31 = (t30 + 56U);
t32 = *((char **)t31);
t33 = (t32 + 56U);
t34 = *((char **)t33);
*((unsigned char *)t34) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t30);
LAB2: t35 = (t0 + 7160);
*((int *)t35) = 1;
LAB1: return;
LAB3: t23 = (t0 + 7688);
t26 = (t23 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
*((unsigned char *)t29) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t23);
goto LAB2;
LAB5: t15 = (t0 + 1352U);
t18 = *((char **)t15);
t15 = (t0 + 11256U);
t19 = (t0 + 11487);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
t23 = (t22 + 4U);
*((int *)t23) = 2;
t23 = (t22 + 8U);
*((int *)t23) = 1;
t24 = (2 - 0);
t11 = (t24 * 1);
t11 = (t11 + 1);
t23 = (t22 + 12U);
*((unsigned int *)t23) = t11;
t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
t1 = t25;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_7(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(66, ng0);
t2 = (t0 + 2632U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7752);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7176);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7752);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11490);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_8(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(68, ng0);
t2 = (t0 + 2792U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7816);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7192);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7816);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11492);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_9(char *t0)
{
char t5[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
LAB0: xsi_set_current_line(70, ng0);
t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 11368U);
t3 = (t0 + 11494);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 7;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (7 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4:
LAB5: t15 = (t0 + 7880);
t16 = (t15 + 56U);
t17 = *((char **)t16);
t18 = (t17 + 56U);
t19 = *((char **)t18);
*((unsigned char *)t19) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t15);
LAB2: t20 = (t0 + 7208);
*((int *)t20) = 1;
LAB1: return;
LAB3: t7 = (t0 + 7880);
t11 = (t7 + 56U);
t12 = *((char **)t11);
t13 = (t12 + 56U);
t14 = *((char **)t13);
*((unsigned char *)t14) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t7);
goto LAB2;
LAB6: goto LAB2;
}
static void work_a_0832606739_3212880686_p_10(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(72, ng0);
LAB3: t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 7944);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 7224);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0832606739_3212880686_init()
{
static char *pe[] = {(void *)work_a_0832606739_3212880686_p_0,(void *)work_a_0832606739_3212880686_p_1,(void *)work_a_0832606739_3212880686_p_2,(void *)work_a_0832606739_3212880686_p_3,(void *)work_a_0832606739_3212880686_p_4,(void *)work_a_0832606739_3212880686_p_5,(void *)work_a_0832606739_3212880686_p_6,(void *)work_a_0832606739_3212880686_p_7,(void *)work_a_0832606739_3212880686_p_8,(void *)work_a_0832606739_3212880686_p_9,(void *)work_a_0832606739_3212880686_p_10};
xsi_register_didat("work_a_0832606739_3212880686", "isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o Normal file
View file

Binary file not shown.

132
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.c Normal file
View file

@ -0,0 +1,132 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd";
static void work_a_2602956921_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 3304U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(100, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3112);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(103, ng0);
t2 = (t0 + 6215);
t5 = (t0 + 3688);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 8U);
xsi_driver_first_trans_fast(t5);
xsi_set_current_line(104, ng0);
t2 = (t0 + 6223);
t5 = (t0 + 3752);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 8U);
xsi_driver_first_trans_fast(t5);
xsi_set_current_line(105, ng0);
t3 = (4 * 1000LL);
t2 = (t0 + 6231);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(106, ng0);
t3 = (8 * 1000LL);
t2 = (t0 + 6234);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(107, ng0);
t3 = (12 * 1000LL);
t2 = (t0 + 6237);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(108, ng0);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
extern void work_a_2602956921_2372691052_init()
{
static char *pe[] = {(void *)work_a_2602956921_2372691052_p_0};
xsi_register_didat("work_a_2602956921_2372691052", "isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.lin64.o Normal file
View file

Binary file not shown.

49
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/alu_test_isim_beh.exe_main.c Normal file
View file

@ -0,0 +1,49 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
char *IEEE_P_3620187407;
char *IEEE_P_3499444699;
char *IEEE_P_1242562249;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_0832606739_3212880686_init();
work_a_2602956921_2372691052_init();
xsi_register_tops("work_a_2602956921_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
return xsi_run_simulation(argc, argv);
}

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/alu_test_isim_beh.exe_main.lin64.o Normal file
View file

Binary file not shown.

16
xilinx/ALU/isim/isim_usage_statistics.html Normal file
View file

@ -0,0 +1,16 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>920 ms, 1722952 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>22</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>91</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>12</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.19 sec, 256135 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>

0
xilinx/ALU/isim/lockfile Normal file
View file

0
xilinx/ALU/isim/lockfile1 Normal file
View file

1
xilinx/ALU/isim/pn_info Normal file
View file

@ -0,0 +1 @@
13.4

34667
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.c Normal file
View file

File diff suppressed because one or more lines are too long

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.lin64.o Normal file
View file

Binary file not shown.

8819
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.c Normal file
View file

File diff suppressed because it is too large Load diff

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o Normal file
View file

Binary file not shown.

25136
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.c Normal file
View file

File diff suppressed because one or more lines are too long

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.lin64.o Normal file
View file

Binary file not shown.

2482
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.c Normal file
View file

File diff suppressed because it is too large Load diff

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.lin64.o Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/alu.vdb Normal file
View file

Binary file not shown.

BIN
xilinx/ALU/isim/work/alu_test.vdb Normal file
View file

Binary file not shown.

1
xilinx/ALU/pepExtractor.prj Normal file
View file

@ -0,0 +1 @@
work "alu.vhd"

1
xilinx/ALU/xilinxsim.ini Normal file
View file

@ -0,0 +1 @@
work=isim/work

50
xilinx/BR/BR.vhd Normal file
View file

@ -0,0 +1,50 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:28:01 04/13/2021
-- Design Name:
-- Module Name: BR - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BR is
Port ( A_addr : in STD_LOGIC_VECTOR (3 downto 0);
B_addr : in STD_LOGIC_VECTOR (3 downto 0);
W_addr : in STD_LOGIC_VECTOR (3 downto 0);
W : in STD_LOGIC;
Data : in STD_LOGIC_VECTOR (7 downto 0);
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
QA : out STD_LOGIC_VECTOR (7 downto 0);
QB : out STD_LOGIC_VECTOR (7 downto 0));
end BR;
architecture Behavioral of BR is
begin
end Behavioral;