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- --------------------------------------------------------------------------------
- -- Company:
- -- Engineer:
- --
- -- Create Date: 10:50:53 04/13/2021
- -- Design Name:
- -- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd
- -- Project Name: ALU
- -- Target Device:
- -- Tool versions:
- -- Description:
- --
- -- VHDL Test Bench Created by ISE for module: alu
- --
- -- Dependencies:
- --
- -- Revision:
- -- Revision 0.01 - File Created
- -- Additional Comments:
- --
- -- Notes:
- -- This testbench has been automatically generated using types std_logic and
- -- std_logic_vector for the ports of the unit under test. Xilinx recommends
- -- that these types always be used for the top-level I/O of a design in order
- -- to guarantee that the testbench will bind correctly to the post-implementation
- -- simulation model.
- --------------------------------------------------------------------------------
- LIBRARY ieee;
- USE ieee.std_logic_1164.ALL;
-
- -- Uncomment the following library declaration if using
- -- arithmetic functions with Signed or Unsigned values
- --USE ieee.numeric_std.ALL;
-
- ENTITY alu_test IS
- END alu_test;
-
- ARCHITECTURE behavior OF alu_test IS
-
- -- Component Declaration for the Unit Under Test (UUT)
-
- COMPONENT alu
- PORT(
- A : IN std_logic_vector(7 downto 0);
- B : IN std_logic_vector(7 downto 0);
- Ctrl_Alu : IN std_logic_vector(2 downto 0);
- N : OUT std_logic;
- O : OUT std_logic;
- Z : OUT std_logic;
- C : OUT std_logic;
- S : OUT std_logic_vector(7 downto 0)
- );
- END COMPONENT;
-
-
- --Inputs
- signal A : std_logic_vector(7 downto 0) := (others => '0');
- signal B : std_logic_vector(7 downto 0) := (others => '0');
- signal Ctrl_Alu : std_logic_vector(2 downto 0) := (others => '0');
-
- --Outputs
- signal N : std_logic;
- signal O : std_logic;
- signal Z : std_logic;
- signal C : std_logic;
- signal S : std_logic_vector(7 downto 0);
- -- No clocks detected in port list. Replace <clock> below with
- -- appropriate port name
-
- BEGIN
-
- -- Instantiate the Unit Under Test (UUT)
- uut: alu PORT MAP (
- A => A,
- B => B,
- Ctrl_Alu => Ctrl_Alu,
- N => N,
- O => O,
- Z => Z,
- C => C,
- S => S
- );
-
-
-
-
- -- Stimulus process
- stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
- B<="11111111";
- A<="11111111";
- Ctrl_Alu<="001" after 4 ns;
- Ctrl_Alu<="010" after 8 ns;
- Ctrl_Alu<="011" after 12 ns;
- wait;
- end process;
-
- END;
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