Browse Source

compilateur ok + alu ok + br a finir

Foussats Morgane 7 months ago
parent
commit
56676de078
72 changed files with 76464 additions and 1981 deletions
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BIN
a.out View File


+ 726
- 713
analyse_syntaxique.output
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+ 851
- 951
analyse_syntaxique.tab.c
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+ 68
- 91
analyse_syntaxique.tab.h View File

@@ -1,14 +1,13 @@
1
-/* A Bison parser, made by GNU Bison 2.3.  */
1
+/* A Bison parser, made by GNU Bison 3.0.4.  */
2 2
 
3
-/* Skeleton interface for Bison's Yacc-like parsers in C
3
+/* Bison interface for Yacc-like parsers in C
4 4
 
5
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
6
-   Free Software Foundation, Inc.
5
+   Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc.
7 6
 
8
-   This program is free software; you can redistribute it and/or modify
7
+   This program is free software: you can redistribute it and/or modify
9 8
    it under the terms of the GNU General Public License as published by
10
-   the Free Software Foundation; either version 2, or (at your option)
11
-   any later version.
9
+   the Free Software Foundation, either version 3 of the License, or
10
+   (at your option) any later version.
12 11
 
13 12
    This program is distributed in the hope that it will be useful,
14 13
    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -16,9 +15,7 @@
16 15
    GNU General Public License for more details.
17 16
 
18 17
    You should have received a copy of the GNU General Public License
19
-   along with this program; if not, write to the Free Software
20
-   Foundation, Inc., 51 Franklin Street, Fifth Floor,
21
-   Boston, MA 02110-1301, USA.  */
18
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22 19
 
23 20
 /* As a special exception, you may create a larger work that contains
24 21
    part or all of the Bison parser skeleton and distribute that work
@@ -33,97 +30,77 @@
33 30
    This special exception was added by the Free Software Foundation in
34 31
    version 2.2 of Bison.  */
35 32
 
36
-/* Tokens.  */
33
+#ifndef YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
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+# define YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED
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+/* Debug traces.  */
36
+#ifndef YYDEBUG
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+# define YYDEBUG 1
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+#endif
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+#if YYDEBUG
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+extern int yydebug;
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+#endif
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+
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+/* Token type.  */
37 44
 #ifndef YYTOKENTYPE
38 45
 # define YYTOKENTYPE
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-   /* Put the tokens into the symbol table, so that GDB and other debuggers
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-      know about them.  */
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-   enum yytokentype {
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-     tENTIER = 258,
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-     tENTIEREXP = 259,
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-     tADD = 260,
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-     tSUB = 261,
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-     tMUL = 262,
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-     tDIV = 263,
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-     tPO = 264,
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-     tPF = 265,
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-     tAO = 266,
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-     tAF = 267,
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-     tERROR = 268,
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-     tPV = 269,
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-     tVIRGULE = 270,
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-     tAFFECTATION = 271,
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-     tEGAL = 272,
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-     tDIFF = 273,
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-     tLT = 274,
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-     tGT = 275,
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-     tGTE = 276,
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-     tLTE = 277,
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-     tMAIN = 278,
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-     tINT = 279,
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-     tPRINT = 280,
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-     tRETURN = 281,
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-     tOR = 282,
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-     tAND = 283,
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-     tIF = 284,
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-     tELSE = 285,
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-     tWHILE = 286,
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-     tCONST = 287,
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-     tVAR = 288,
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-     tNOT = 289
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-   };
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+  enum yytokentype
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+  {
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+    tENTIER = 258,
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+    tENTIEREXP = 259,
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+    tADD = 260,
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+    tSUB = 261,
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+    tMUL = 262,
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+    tDIV = 263,
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+    tPO = 264,
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+    tPF = 265,
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+    tAO = 266,
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+    tAF = 267,
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+    tERROR = 268,
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+    tPV = 269,
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+    tVIRGULE = 270,
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+    tAFFECTATION = 271,
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+    tEGAL = 272,
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+    tDIFF = 273,
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+    tLT = 274,
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+    tGT = 275,
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+    tGTE = 276,
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+    tLTE = 277,
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+    tMAIN = 278,
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+    tINT = 279,
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+    tPRINT = 280,
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+    tRETURN = 281,
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+    tOR = 282,
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+    tAND = 283,
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+    tIF = 284,
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+    tELSE = 285,
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+    tWHILE = 286,
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+    tCONST = 287,
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+    tVAR = 288,
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+    tNOT = 289
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+  };
75 81
 #endif
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-/* Tokens.  */
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-#define tENTIER 258
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-#define tENTIEREXP 259
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-#define tADD 260
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-#define tSUB 261
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-#define tMUL 262
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-#define tDIV 263
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-#define tPO 264
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-#define tPF 265
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-#define tAO 266
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-#define tAF 267
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-#define tERROR 268
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-#define tPV 269
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-#define tVIRGULE 270
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-#define tAFFECTATION 271
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-#define tEGAL 272
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-#define tDIFF 273
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-#define tLT 274
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-#define tGT 275
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-#define tGTE 276
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-#define tLTE 277
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-#define tMAIN 278
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-#define tINT 279
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-#define tPRINT 280
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-#define tRETURN 281
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-#define tOR 282
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-#define tAND 283
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-#define tIF 284
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-#define tELSE 285
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-#define tWHILE 286
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-#define tCONST 287
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-#define tVAR 288
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-#define tNOT 289
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-
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-
111
-
112 82
 
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+/* Value type.  */
113 84
 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
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-typedef union YYSTYPE
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-#line 1 "analyse_syntaxique.y"
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+
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+union YYSTYPE
116 87
 {
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+#line 1 "analyse_syntaxique.y" /* yacc.c:1909  */
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+
117 90
 int nombre;
118 91
 char id[30];
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-}
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-/* Line 1529 of yacc.c.  */
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-#line 122 "analyse_syntaxique.tab.h"
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-	YYSTYPE;
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-# define yystype YYSTYPE /* obsolescent; will be withdrawn */
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-# define YYSTYPE_IS_DECLARED 1
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+
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+#line 94 "analyse_syntaxique.tab.h" /* yacc.c:1909  */
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+};
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+
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+typedef union YYSTYPE YYSTYPE;
125 97
 # define YYSTYPE_IS_TRIVIAL 1
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+# define YYSTYPE_IS_DECLARED 1
126 99
 #endif
127 100
 
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+
128 102
 extern YYSTYPE yylval;
129 103
 
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+int yyparse (void);
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+
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+#endif /* !YY_YY_ANALYSE_SYNTAXIQUE_TAB_H_INCLUDED  */

+ 6
- 6
analyse_syntaxique.y View File

@@ -22,6 +22,7 @@ int whileCondition;
22 22
 %type<nombre> E
23 23
 %type<nombre> Return
24 24
 %type<nombre> Cond
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+%type<nombre> While
25 26
 
26 27
 
27 28
 
@@ -149,12 +150,11 @@ Else : tELSE tAO Instructions tAF {printf("else\n");} ;
149 150
 Else : ;
150 151
 Else : tELSE tIF tPO Cond tPF tAO Instructions tAF Else {printf("elsif\n");} ;
151 152
 
152
-/*While : tWHILE tPO {
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-	$2 = array.index + 1 ;
154
-} Cond tPF {*/
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-While : tWHILE tPO Cond tPF {
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-	//gen_jmpf(&table, &array, $3, -1);
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-	generate_instruction_2(&array, JMF, $3, -1);
153
+While : tWHILE tPO {
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+	$2 = array.index ;
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+} Cond tPF {
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+	//gen_jmpf(&table, &array, $4, -1);
157
+	generate_instruction_2(&array, JMF, $4, -1);
158 158
 	free_temp(&table);
159 159
 	$1 = array.index;
160 160
 }

+ 1
- 1
instructions.txt View File

@@ -8,7 +8,7 @@
8 8
 7	 JPF 49 10
9 9
 8	 AFC 49 1
10 10
 9	 AFC 49 4
11
-10	 JPM 4
11
+10	 JPM 5
12 12
 11	 CPY 49 1
13 13
 12	 PRI 49
14 14
 13	 AFC 49 5

+ 227
- 219
lex.yy.c
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+ 101
- 0
xilinx/ALU/ALU.gise View File

@@ -0,0 +1,101 @@
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+
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+
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+  <!--             For tool use only. Do not edit.              -->
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+
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+  <!--                                                          -->
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+
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+
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+
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+  <!-- allowing preservation of process status.                 -->
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+
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+  <!--                                                          -->
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+
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+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
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+
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+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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+
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+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ALU.xise"/>
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+
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+  <files xmlns="http://www.xilinx.com/XMLSchema">
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+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
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+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
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+  </files>
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+    <transform xil_pn:end_ts="1618304818" xil_pn:in_ck="-4068278894953614943" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5179862647015444475" xil_pn:start_ts="1618304818">
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+      <status xil_pn:value="SuccessfullyRun"/>
91
+      <status xil_pn:value="ReadyToRun"/>
92
+      <status xil_pn:value="OutOfDateForInputs"/>
93
+      <status xil_pn:value="OutOfDateForPredecessor"/>
94
+      <status xil_pn:value="OutOfDateForOutputs"/>
95
+      <status xil_pn:value="InputRemoved"/>
96
+      <status xil_pn:value="OutputChanged"/>
97
+      <status xil_pn:value="OutputRemoved"/>
98
+    </transform>
99
+  </transforms>
100
+
101
+</generated_project>

+ 410
- 0
xilinx/ALU/ALU.xise View File

@@ -0,0 +1,410 @@
1
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
+
4
+  <header>
5
+    <!-- ISE source project file created by Project Navigator.             -->
6
+    <!--                                                                   -->
7
+    <!-- This file contains project source information including a list of -->
8
+    <!-- project source files, project and process properties.  This file, -->
9
+    <!-- along with the project source files, is sufficient to open and    -->
10
+    <!-- implement in ISE Project Navigator.                               -->
11
+    <!--                                                                   -->
12
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
13
+  </header>
14
+
15
+  <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
16
+
17
+  <files>
18
+    <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
19
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
21
+    </file>
22
+    <file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
23
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
24
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
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+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
26
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
27
+    </file>
28
+    <file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
29
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
30
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
31
+    </file>
32
+  </files>
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+
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+  <properties>
35
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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+    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
37
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
38
+    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
40
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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+    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
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+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
72
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
80
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
81
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
82
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
87
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
88
+    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
89
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
90
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
91
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
92
+    <property xil_pn:name="Device" xil_pn:value="xc6slx16" xil_pn:valueState="non-default"/>
93
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
94
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
98
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
100
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
107
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
109
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
110
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
111
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
112
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
113
+    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
114
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
128
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
129
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
134
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
140
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
141
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
142
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
144
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
145
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
146
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
147
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
148
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
149
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
150
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
151
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
152
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
153
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
154
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
155
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
157
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
159
+    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
160
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
161
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
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+    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
164
+    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
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+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
167
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|alu|Behavioral" xil_pn:valueState="non-default"/>
169
+    <property xil_pn:name="Implementation Top File" xil_pn:value="alu.vhd" xil_pn:valueState="non-default"/>
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+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/alu" xil_pn:valueState="non-default"/>
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+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
172
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
173
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
177
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
178
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
179
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
180
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
181
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
182
+    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
184
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
185
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
186
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
187
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
188
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
189
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
190
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
192
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
194
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
195
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
196
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
197
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
198
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
199
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
200
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
201
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
202
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
203
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
204
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
205
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
206
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
207
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
208
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
209
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
210
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
211
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
212
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
213
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
214
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
215
+    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
216
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
217
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
218
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
219
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
220
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
221
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
222
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
223
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
224
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
225
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
226
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
227
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
228
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
229
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
230
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
231
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
232
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
233
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
234
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
235
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
236
+    <property xil_pn:name="Output File Name" xil_pn:value="alu" xil_pn:valueState="default"/>
237
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
238
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
239
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
240
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
241
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
242
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
243
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
244
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
245
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
246
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
247
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
248
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
249
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
250
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="alu_map.vhd" xil_pn:valueState="default"/>
251
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
252
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
253
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
254
+    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
255
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
256
+    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
257
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
258
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
259
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
260
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
261
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
262
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
263
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
264
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
265
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
266
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
267
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
268
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
269
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
270
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
271
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
272
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
273
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
274
+    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
275
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
276
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
277
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
278
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="alu" xil_pn:valueState="default"/>
279
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
280
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
281
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
282
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
283
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
284
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
285
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
286
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
287
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
288
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
289
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
290
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
291
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
292
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
293
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
294
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
295
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
296
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
297
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
298
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
299
+    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
300
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
301
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
302
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
303
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="non-default"/>
304
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
305
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
306
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
307
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
308
+    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
309
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
310
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
311
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
312
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
313
+    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
314
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
315
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
316
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
317
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
318
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
319
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
320
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
321
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
322
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
323
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.alu_test" xil_pn:valueState="default"/>
324
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
325
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
326
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
327
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
328
+    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
329
+    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
330
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
331
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
332
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
333
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
334
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
335
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
336
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
337
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
338
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
339
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
340
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
341
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
342
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
343
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
344
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
345
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
346
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
347
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
348
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
349
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
350
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
351
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
352
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
353
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
354
+    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
355
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
356
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
357
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
358
+    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
359
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
360
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
361
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
362
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
363
+    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
364
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
365
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
366
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
367
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
368
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
369
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
370
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
371
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
372
+    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
373
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
374
+    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
375
+    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
376
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
377
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
378
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
379
+    <!--                                                                                  -->
380
+    <!-- The following properties are for internal use only. These should not be modified.-->
381
+    <!--                                                                                  -->
382
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|alu_test|behavior" xil_pn:valueState="non-default"/>
383
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
384
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
385
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
386
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
387
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
388
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
389
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
390
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
391
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-04-13T10:09:14" xil_pn:valueState="non-default"/>
392
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E745AC3463D83535AAF1ABA5736091BC" xil_pn:valueState="non-default"/>
393
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
394
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
395
+  </properties>
396
+
397
+  <bindings/>
398
+
399
+  <libraries/>
400
+
401
+  <autoManagedFiles>
402
+    <!-- The following files are identified by `include statements in verilog -->
403
+    <!-- source files and are automatically managed by Project Navigator.     -->
404
+    <!--                                                                      -->
405
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
406
+    <!-- project is analyzed based on files automatically identified as       -->
407
+    <!-- include files.                                                       -->
408
+  </autoManagedFiles>
409
+
410
+</project>

+ 18
- 0
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File

@@ -0,0 +1,18 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- IMPORTANT: This is an internal file that has been generated   -->
3
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
4
+<!--     changes made to this file may result in unpredictable     -->
5
+<!--     behavior or data corruption.  It is strongly advised that -->
6
+<!--     users do not edit the contents of this file.              -->
7
+<!--                                                               -->
8
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9
+
10
+<messages>
11
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd&quot; into library work</arg>
12
+</msg>
13
+
14
+<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd</arg>&quot; Line <arg fmt="%d" index="2">47</arg>. <arg fmt="%s" index="3">Syntax error near &quot;CLK&quot;.</arg>
15
+</msg>
16
+
17
+</messages>
18
+

+ 74
- 0
xilinx/ALU/alu.vhd View File

@@ -0,0 +1,74 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date:    10:12:38 04/13/2021 
6
+-- Design Name: 
7
+-- Module Name:    alu - Behavioral 
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool versions: 
11
+-- Description: 
12
+--
13
+-- Dependencies: 
14
+--
15
+-- Revision: 
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments: 
18
+--
19
+----------------------------------------------------------------------------------
20
+library IEEE;
21
+use IEEE.STD_LOGIC_1164.ALL;
22
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
23
+
24
+-- Uncomment the following library declaration if using
25
+-- arithmetic functions with Signed or Unsigned values
26
+use IEEE.NUMERIC_STD.ALL;
27
+
28
+-- Uncomment the following library declaration if instantiating
29
+-- any Xilinx primitives in this code.
30
+--library UNISIM;
31
+--use UNISIM.VComponents.all;
32
+
33
+entity alu is
34
+    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
35
+           B : in  STD_LOGIC_VECTOR (7 downto 0);
36
+           Ctrl_Alu : in  STD_LOGIC_VECTOR (2 downto 0);
37
+           N : out  STD_LOGIC;
38
+           O : out  STD_LOGIC;
39
+           Z : out  STD_LOGIC;
40
+           C : out  STD_LOGIC;
41
+           S : out  STD_LOGIC_VECTOR (7 downto 0));
42
+end alu;
43
+
44
+architecture Behavioral of alu is
45
+	signal A9: STD_LOGIC_VECTOR(8 downto 0);
46
+	signal B9: STD_LOGIC_VECTOR(8 downto 0);
47
+	signal ADD: STD_LOGIC_VECTOR(8 downto 0);
48
+	signal SUB: STD_LOGIC_VECTOR(8 downto 0);
49
+	signal MUL: STD_LOGIC_VECTOR(15 downto 0);
50
+	signal SBIS: STD_LOGIC_VECTOR(7 downto 0);
51
+	
52
+begin
53
+
54
+		A9 <= "0"& A;
55
+		B9 <= "0"& B;
56
+		ADD <= A9 + B9;
57
+		SUB <= A9 - B9;
58
+		MUL <= A * B;
59
+		
60
+		SBIS <= ADD(7 downto 0) when Ctrl_Alu = "01" else
61
+			  SUB(7 downto 0) when Ctrl_Alu = "10" else
62
+			  MUL(7 downto 0) when Ctrl_Alu = "11" else
63
+			  (others => '0');
64
+		O <= '1' when MUL(15 downto 8) /= "00000000" and Ctrl_Alu = "011" else
65
+			  '0';
66
+		C <= '1' when ADD(8) = '1' and Ctrl_Alu = "01" else
67
+			  '0';
68
+		N <= '1' when SUB(8) = '1' and Ctrl_Alu = "10" else
69
+			  '0';
70
+		Z <= '1' when SBIS = "00000000" else
71
+			  '0';
72
+		S <= SBIS;
73
+end Behavioral;
74
+

BIN
xilinx/ALU/alu_isim_beh.exe View File


BIN
xilinx/ALU/alu_isim_beh1.wdb View File


+ 80
- 0
xilinx/ALU/alu_summary.html View File

@@ -0,0 +1,80 @@
1
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5
+<TD ALIGN=CENTER COLSPAN='4'><B>alu Project Status</B></TD></TR>
6
+<TR ALIGN=LEFT>
7
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8
+<TD>ALU.xise</TD>
9
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10
+<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
11
+</TR>
12
+<TR ALIGN=LEFT>
13
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14
+<TD>alu</TD>
15
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16
+<TD>New</TD>
17
+</TR>
18
+<TR ALIGN=LEFT>
19
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20
+<TD>xc6slx16-3csg324</TD>
21
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22
+<TD>&nbsp;</TD>
23
+</TR>
24
+<TR ALIGN=LEFT>
25
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD>
26
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
27
+<TD>&nbsp;</TD>
28
+</TR>
29
+<TR ALIGN=LEFT>
30
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
31
+<TD>Balanced</TD>
32
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
33
+<TD>
34
+&nbsp;</TD>
35
+</TR>
36
+<TR ALIGN=LEFT>
37
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
38
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
39
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
40
+<TD>&nbsp;</TD>
41
+</TR>
42
+<TR ALIGN=LEFT>
43
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
44
+<TD>&nbsp;</TD>
45
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
46
+<TD>&nbsp;&nbsp;</TD>
47
+</TR>
48
+</TABLE>
49
+
50
+
51
+
52
+
53
+
54
+
55
+
56
+
57
+
58
+
59
+
60
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
61
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
62
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
63
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
64
+<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
65
+<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
66
+<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
67
+<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
68
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
69
+<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
70
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
71
+</TABLE>
72
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
73
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
74
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
75
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. avr. 13 11:14:16 2021</TD></TR>
76
+</TABLE>
77
+
78
+
79
+<br><center><b>Date Generated:</b> 04/13/2021 - 11:53:22</center>
80
+</BODY></HTML>

+ 100
- 0
xilinx/ALU/alu_test.vhd View File

@@ -0,0 +1,100 @@
1
+--------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer:
4
+--
5
+-- Create Date:   10:50:53 04/13/2021
6
+-- Design Name:   
7
+-- Module Name:   /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd
8
+-- Project Name:  ALU
9
+-- Target Device:  
10
+-- Tool versions:  
11
+-- Description:   
12
+-- 
13
+-- VHDL Test Bench Created by ISE for module: alu
14
+-- 
15
+-- Dependencies:
16
+-- 
17
+-- Revision:
18
+-- Revision 0.01 - File Created
19
+-- Additional Comments:
20
+--
21
+-- Notes: 
22
+-- This testbench has been automatically generated using types std_logic and
23
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
+-- that these types always be used for the top-level I/O of a design in order
25
+-- to guarantee that the testbench will bind correctly to the post-implementation 
26
+-- simulation model.
27
+--------------------------------------------------------------------------------
28
+LIBRARY ieee;
29
+USE ieee.std_logic_1164.ALL;
30
+ 
31
+-- Uncomment the following library declaration if using
32
+-- arithmetic functions with Signed or Unsigned values
33
+--USE ieee.numeric_std.ALL;
34
+ 
35
+ENTITY alu_test IS
36
+END alu_test;
37
+ 
38
+ARCHITECTURE behavior OF alu_test IS 
39
+ 
40
+    -- Component Declaration for the Unit Under Test (UUT)
41
+ 
42
+    COMPONENT alu
43
+    PORT(
44
+         A : IN  std_logic_vector(7 downto 0);
45
+         B : IN  std_logic_vector(7 downto 0);
46
+         Ctrl_Alu : IN  std_logic_vector(2 downto 0);
47
+         N : OUT  std_logic;
48
+         O : OUT  std_logic;
49
+         Z : OUT  std_logic;
50
+         C : OUT  std_logic;
51
+         S : OUT  std_logic_vector(7 downto 0)
52
+        );
53
+    END COMPONENT;
54
+    
55
+
56
+   --Inputs
57
+   signal A : std_logic_vector(7 downto 0) := (others => '0');
58
+   signal B : std_logic_vector(7 downto 0) := (others => '0');
59
+   signal Ctrl_Alu : std_logic_vector(2 downto 0) := (others => '0');
60
+
61
+ 	--Outputs
62
+   signal N : std_logic;
63
+   signal O : std_logic;
64
+   signal Z : std_logic;
65
+   signal C : std_logic;
66
+   signal S : std_logic_vector(7 downto 0);
67
+   -- No clocks detected in port list. Replace <clock> below with 
68
+   -- appropriate port name 
69
+ 
70
+BEGIN
71
+ 
72
+	-- Instantiate the Unit Under Test (UUT)
73
+   uut: alu PORT MAP (
74
+          A => A,
75
+          B => B,
76
+          Ctrl_Alu => Ctrl_Alu,
77
+          N => N,
78
+          O => O,
79
+          Z => Z,
80
+          C => C,
81
+          S => S
82
+        );
83
+
84
+
85
+ 
86
+
87
+   -- Stimulus process
88
+   stim_proc: process
89
+   begin		
90
+      -- hold reset state for 100 ns.
91
+      wait for 100 ns;	
92
+			B<="11111111";
93
+			A<="11111111";
94
+			Ctrl_Alu<="001" after 4 ns;
95
+			Ctrl_Alu<="010" after 8 ns;
96
+			Ctrl_Alu<="011" after 12 ns;
97
+      wait;
98
+   end process;
99
+
100
+END;

+ 2
- 0
xilinx/ALU/alu_test_beh.prj View File

@@ -0,0 +1,2 @@
1
+vhdl work "alu.vhd"
2
+vhdl work "alu_test.vhd"

BIN
xilinx/ALU/alu_test_isim_beh.exe View File


BIN
xilinx/ALU/alu_test_isim_beh.wdb View File


+ 61
- 0
xilinx/ALU/br.vhd View File

@@ -0,0 +1,61 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date:    11:29:59 04/13/2021 
6
+-- Design Name: 
7
+-- Module Name:    br - Behavioral 
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool versions: 
11
+-- Description: 
12
+--
13
+-- Dependencies: 
14
+--
15
+-- Revision: 
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments: 
18
+--
19
+----------------------------------------------------------------------------------
20
+library IEEE;
21
+use IEEE.STD_LOGIC_1164.ALL;
22
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
23
+use IEEE.NUMERIC_STD.ALL;
24
+
25
+--use UNISIM.VComponents.all;
26
+
27
+entity br is
28
+    Port ( A_addr : in  STD_LOGIC_VECTOR (3 downto 0);
29
+           B_addr : in  STD_LOGIC_VECTOR (3 downto 0);
30
+           W_addr : in  STD_LOGIC_VECTOR (3 downto 0);
31
+           W : in  STD_LOGIC;
32
+           Data : in  STD_LOGIC_VECTOR (7 downto 0);
33
+           RST : in  STD_LOGIC;
34
+           CLK : in  STD_LOGIC;
35
+           QA : out  STD_LOGIC_VECTOR (7 downto 0);
36
+           QB : out  STD_LOGIC_VECTOR (7 downto 0));
37
+end br;
38
+
39
+architecture Behavioral of br is
40
+
41
+type reg is array (0 to 15) of STD_LOGIC_VECTOR(7 downto 0);
42
+signal registres: reg;
43
+
44
+begin
45
+	process
46
+		begin
47
+			wait until CLK'event CLK = '1';
48
+			if W = '1' then
49
+				registres(W_addr) <= Data;
50
+			else
51
+				
52
+			end if;
53
+			if RST='0' then 
54
+				QA <= "00000000";
55
+				QB <= "00000000";
56
+			end if;
57
+			
58
+	end process;
59
+
60
+end Behavioral;
61
+

+ 25
- 0
xilinx/ALU/fuse.log View File

@@ -0,0 +1,25 @@
1
+Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test" 
2
+ISim O.87xd (signature 0x8ddf5b5d)
3
+Number of CPUs detected in this system: 12
4
+Turning on mult-threading, number of parallel sub-compilation jobs: 24 
5
+Determining compilation order of HDL files
6
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
7
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd" into library work
8
+Starting static elaboration
9
+Completed static elaboration
10
+Fuse Memory Usage: 98500 KB
11
+Fuse CPU Usage: 810 ms
12
+Compiling package standard
13
+Compiling package std_logic_1164
14
+Compiling package std_logic_arith
15
+Compiling package std_logic_unsigned
16
+Compiling package numeric_std
17
+Compiling architecture behavioral of entity alu [alu_default]
18
+Compiling architecture behavior of entity alu_test
19
+Time Resolution for simulation is 1ps.
20
+Waiting for 1 sub-compilation(s) to finish...
21
+Compiled 8 VHDL Units
22
+Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe
23
+Fuse Memory Usage: 1722952 KB
24
+Fuse CPU Usage: 920 ms
25
+GCC CPU Usage: 80 ms

+ 9
- 0
xilinx/ALU/fuse.xmsgs View File

@@ -0,0 +1,9 @@
1
+<?xml version="1.0" encoding="UTF-8"?>
2
+<!-- IMPORTANT: This is an internal file that has been generated
3
+     by the Xilinx ISE software.  Any direct editing or
4
+     changes made to this file may result in unpredictable
5
+     behavior or data corruption.  It is strongly advised that
6
+     users do not edit the contents of this file. -->
7
+<messages>
8
+</messages>
9
+

+ 1
- 0
xilinx/ALU/fuseRelaunch.cmd View File

@@ -0,0 +1 @@
1
+-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test" 

+ 131
- 0
xilinx/ALU/iseconfig/ALU.projectmgr View File

@@ -0,0 +1,131 @@
1
+<?xml version="1.0" encoding="utf-8"?>
2
+<!--This is an ISE project configuration file.-->
3
+<!--It holds project specific layout data for the projectmgr plugin.-->
4
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
5
+<Project version="2" owner="projectmgr" name="ALU" >
6
+   <!--This is an ISE project configuration file.-->
7
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
8
+      <ClosedNodes>
9
+         <ClosedNodesVersion>2</ClosedNodesVersion>
10
+      </ClosedNodes>
11
+      <SelectedItems>
12
+         <SelectedItem>ALU</SelectedItem>
13
+      </SelectedItems>
14
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000200000064ffffffff000000810000000300000002000001040000000100000003000000000000000100000003</ViewHeaderState>
17
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18
+      <CurrentItem>ALU</CurrentItem>
19
+   </ItemView>
20
+   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21
+      <ClosedNodes>
22
+         <ClosedNodesVersion>1</ClosedNodesVersion>
23
+         <ClosedNode>Design Utilities</ClosedNode>
24
+      </ClosedNodes>
25
+      <SelectedItems>
26
+         <SelectedItem></SelectedItem>
27
+      </SelectedItems>
28
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
29
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
30
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
31
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
32
+      <CurrentItem></CurrentItem>
33
+   </ItemView>
34
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+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="alu_pad.txt" label="Pad Report" >
179
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
180
+   </view>
181
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="alu.unroutes" label="Unroutes Report" >
182
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183
+   </view>
184
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu_preroute.tsi" label="Post-Map Constraints Interaction Report" >
185
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
186
+   </view>
187
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.grf" label="Guide Results Report" />
188
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.dly" label="Asynchronous Delay Report" />
189
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.clk_rgn" label="Clock Region Report" />
190
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.tsi" label="Post-Place and Route Constraints Interaction Report" >
191
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
192
+   </view>
193
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
194
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/alu_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
195
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="alu_sta.nlf" label="Primetime Netlist Report" >
196
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
197
+   </view>
198
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="alu.ibs" label="IBIS Model" >
199
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
200
+    <toc-item title="Component" target="Component " />
201
+   </view>
202
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lck" label="Back-annotate Pin Report" >
203
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
204
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
205
+   </view>
206
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="alu.lpc" label="Locked Pin Constraints" >
207
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
208
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
209
+   </view>
210
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/alu_timesim.nlf" label="Post-Fit Simulation Model Report" />
211
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
212
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
213
+  </viewgroup>
214
+ </body>
215
+</report-views>

+ 3
- 0
xilinx/ALU/isim.cmd View File

@@ -0,0 +1,3 @@
1
+onerror {resume}
2
+wave add /
3
+run 1000 ns;

+ 33
- 0
xilinx/ALU/isim.log View File

@@ -0,0 +1,33 @@
1
+ISim log file
2
+Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.wdb 
3
+ISim O.87xd (signature 0x8ddf5b5d)
4
+WARNING: A WEBPACK license was found.
5
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
6
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
7
+This is a Lite version of ISim.
8
+Time resolution is 1 ps
9
+# onerror resume
10
+# wave add /
11
+# run 1000 ns
12
+Simulator is doing circuit initialization process.
13
+at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
14
+Finished circuit initialization process.
15
+ISim O.87xd (signature 0x8ddf5b5d)
16
+WARNING: A WEBPACK license was found.
17
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
18
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
19
+This is a Lite version of ISim.
20
+# run 1000 ns
21
+Simulator is doing circuit initialization process.
22
+at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
23
+Finished circuit initialization process.
24
+ISim O.87xd (signature 0x8ddf5b5d)
25
+WARNING: A WEBPACK license was found.
26
+WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
27
+WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
28
+This is a Lite version of ISim.
29
+# run 1000 ns
30
+Simulator is doing circuit initialization process.
31
+at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
32
+Finished circuit initialization process.
33
+# exit 0

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe View File


+ 0
- 0
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimcrash.log View File


+ 29
- 0
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimkernel.log View File

@@ -0,0 +1,29 @@
1
+Command line:
2
+   alu_isim_beh.exe
3
+     -simmode  gui
4
+     -simrunnum  1
5
+     -socket  46007
6
+
7
+Tue Apr 13 11:05:00 2021
8
+
9
+
10
+ Elaboration Time: 0 sec
11
+
12
+ Current Memory Usage: 181.678 Meg
13
+
14
+ Total Signals          : 14
15
+ Total Nets             : 91
16
+ Total Signal Drivers   : 11
17
+ Total Blocks           : 5
18
+ Total Primitive Blocks : 5
19
+ Total Processes        : 11
20
+ Total Traceable Variables  : 15
21
+ Total Scalar Nets and Variables : 592
22
+Total Line Count : 11
23
+
24
+ Total Simulation Time: 0.08 sec
25
+
26
+ Current Memory Usage: 257.18 Meg
27
+
28
+Tue Apr 13 11:05:21 2021
29
+

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/netId1.dat View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/tmp_save/_1 View File


+ 931
- 0
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.c View File

@@ -0,0 +1,931 @@
1
+/**********************************************************************/
2
+/*   ____  ____                                                       */
3
+/*  /   /\/   /                                                       */
4
+/* /___/  \  /                                                        */
5
+/* \   \   \/                                                       */
6
+/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
+/*  /   /          All Right Reserved.                                 */
8
+/* /---/   /\                                                         */
9
+/* \   \  /  \                                                      */
10
+/*  \___\/\___\                                                    */
11
+/***********************************************************************/
12
+
13
+/* This file is designed for use with ISim build 0x8ddf5b5d */
14
+
15
+#define XSI_HIDE_SYMBOL_SPEC true
16
+#include "xsi.h"
17
+#include <memory.h>
18
+#ifdef __GNUC__
19
+#include <stdlib.h>
20
+#else
21
+#include <malloc.h>
22
+#define alloca _alloca
23
+#endif
24
+static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
25
+extern char *IEEE_P_2592010699;
26
+extern char *IEEE_P_3620187407;
27
+
28
+unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
29
+char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
30
+char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
31
+char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
32
+
33
+
34
+static void work_a_2725559894_3212880686_p_0(char *t0)
35
+{
36
+    char t5[16];
37
+    char t7[16];
38
+    char *t1;
39
+    char *t3;
40
+    char *t4;
41
+    char *t6;
42
+    char *t8;
43
+    char *t9;
44
+    int t10;
45
+    unsigned int t11;
46
+    unsigned char t12;
47
+    char *t13;
48
+    char *t14;
49
+    char *t15;
50
+    char *t16;
51
+    char *t17;
52
+    char *t18;
53
+
54
+LAB0:    xsi_set_current_line(54, ng0);
55
+
56
+LAB3:    t1 = (t0 + 11471);
57
+    t3 = (t0 + 1032U);
58
+    t4 = *((char **)t3);
59
+    t6 = ((IEEE_P_2592010699) + 4000);
60
+    t8 = (t7 + 0U);
61
+    t9 = (t8 + 0U);
62
+    *((int *)t9) = 0;
63
+    t9 = (t8 + 4U);
64
+    *((int *)t9) = 0;
65
+    t9 = (t8 + 8U);
66
+    *((int *)t9) = 1;
67
+    t10 = (0 - 0);
68
+    t11 = (t10 * 1);
69
+    t11 = (t11 + 1);
70
+    t9 = (t8 + 12U);
71
+    *((unsigned int *)t9) = t11;
72
+    t9 = (t0 + 11224U);
73
+    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
74
+    t11 = (1U + 8U);
75
+    t12 = (9U != t11);
76
+    if (t12 == 1)
77
+        goto LAB5;
78
+
79
+LAB6:    t13 = (t0 + 7304);
80
+    t14 = (t13 + 56U);
81
+    t15 = *((char **)t14);
82
+    t16 = (t15 + 56U);
83
+    t17 = *((char **)t16);
84
+    memcpy(t17, t3, 9U);
85
+    xsi_driver_first_trans_fast(t13);
86
+
87
+LAB2:    t18 = (t0 + 7064);
88
+    *((int *)t18) = 1;
89
+
90
+LAB1:    return;
91
+LAB4:    goto LAB2;
92
+
93
+LAB5:    xsi_size_not_matching(9U, t11, 0);
94
+    goto LAB6;
95
+
96
+}
97
+
98
+static void work_a_2725559894_3212880686_p_1(char *t0)
99
+{
100
+    char t5[16];
101
+    char t7[16];
102
+    char *t1;
103
+    char *t3;
104
+    char *t4;
105
+    char *t6;
106
+    char *t8;
107
+    char *t9;
108
+    int t10;
109
+    unsigned int t11;
110
+    unsigned char t12;
111
+    char *t13;
112
+    char *t14;
113
+    char *t15;
114
+    char *t16;
115
+    char *t17;
116
+    char *t18;
117
+
118
+LAB0:    xsi_set_current_line(55, ng0);
119
+
120
+LAB3:    t1 = (t0 + 11472);
121
+    t3 = (t0 + 1192U);
122
+    t4 = *((char **)t3);
123
+    t6 = ((IEEE_P_2592010699) + 4000);
124
+    t8 = (t7 + 0U);
125
+    t9 = (t8 + 0U);
126
+    *((int *)t9) = 0;
127
+    t9 = (t8 + 4U);
128
+    *((int *)t9) = 0;
129
+    t9 = (t8 + 8U);
130
+    *((int *)t9) = 1;
131
+    t10 = (0 - 0);
132
+    t11 = (t10 * 1);
133
+    t11 = (t11 + 1);
134
+    t9 = (t8 + 12U);
135
+    *((unsigned int *)t9) = t11;
136
+    t9 = (t0 + 11240U);
137
+    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
138
+    t11 = (1U + 8U);
139
+    t12 = (9U != t11);
140
+    if (t12 == 1)
141
+        goto LAB5;
142
+
143
+LAB6:    t13 = (t0 + 7368);
144
+    t14 = (t13 + 56U);
145
+    t15 = *((char **)t14);
146
+    t16 = (t15 + 56U);
147
+    t17 = *((char **)t16);
148
+    memcpy(t17, t3, 9U);
149
+    xsi_driver_first_trans_fast(t13);
150
+
151
+LAB2:    t18 = (t0 + 7080);
152
+    *((int *)t18) = 1;
153
+
154
+LAB1:    return;
155
+LAB4:    goto LAB2;
156
+
157
+LAB5:    xsi_size_not_matching(9U, t11, 0);
158
+    goto LAB6;
159
+
160
+}
161
+
162
+static void work_a_2725559894_3212880686_p_2(char *t0)
163
+{
164
+    char t1[16];
165
+    char *t2;
166
+    char *t3;
167
+    char *t4;
168
+    char *t5;
169
+    char *t6;
170
+    char *t7;
171
+    unsigned int t8;
172
+    unsigned int t9;
173
+    unsigned char t10;
174
+    char *t11;
175
+    char *t12;
176
+    char *t13;
177
+    char *t14;
178
+    char *t15;
179
+    char *t16;
180
+
181
+LAB0:    xsi_set_current_line(56, ng0);
182
+
183
+LAB3:    t2 = (t0 + 2312U);
184
+    t3 = *((char **)t2);
185
+    t2 = (t0 + 11288U);
186
+    t4 = (t0 + 2472U);
187
+    t5 = *((char **)t4);
188
+    t4 = (t0 + 11304U);
189
+    t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
190
+    t7 = (t1 + 12U);
191
+    t8 = *((unsigned int *)t7);
192
+    t9 = (1U * t8);
193
+    t10 = (9U != t9);
194
+    if (t10 == 1)
195
+        goto LAB5;
196
+
197
+LAB6:    t11 = (t0 + 7432);
198
+    t12 = (t11 + 56U);
199
+    t13 = *((char **)t12);
200
+    t14 = (t13 + 56U);
201
+    t15 = *((char **)t14);
202
+    memcpy(t15, t6, 9U);
203
+    xsi_driver_first_trans_fast(t11);
204
+
205
+LAB2:    t16 = (t0 + 7096);
206
+    *((int *)t16) = 1;
207
+
208
+LAB1:    return;
209
+LAB4:    goto LAB2;
210
+
211
+LAB5:    xsi_size_not_matching(9U, t9, 0);
212
+    goto LAB6;
213
+
214
+}
215
+
216
+static void work_a_2725559894_3212880686_p_3(char *t0)
217
+{
218
+    char t1[16];
219
+    char *t2;
220
+    char *t3;
221
+    char *t4;
222
+    char *t5;
223
+    char *t6;
224
+    char *t7;
225
+    unsigned int t8;
226
+    unsigned int t9;
227
+    unsigned char t10;
228
+    char *t11;
229
+    char *t12;
230
+    char *t13;
231
+    char *t14;
232
+    char *t15;
233
+    char *t16;
234
+
235
+LAB0:    xsi_set_current_line(57, ng0);
236
+
237
+LAB3:    t2 = (t0 + 2312U);
238
+    t3 = *((char **)t2);
239
+    t2 = (t0 + 11288U);
240
+    t4 = (t0 + 2472U);
241
+    t5 = *((char **)t4);
242
+    t4 = (t0 + 11304U);
243
+    t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
244
+    t7 = (t1 + 12U);
245
+    t8 = *((unsigned int *)t7);
246
+    t9 = (1U * t8);
247
+    t10 = (9U != t9);
248
+    if (t10 == 1)
249
+        goto LAB5;
250
+
251
+LAB6:    t11 = (t0 + 7496);
252
+    t12 = (t11 + 56U);
253
+    t13 = *((char **)t12);
254
+    t14 = (t13 + 56U);
255
+    t15 = *((char **)t14);
256
+    memcpy(t15, t6, 9U);
257
+    xsi_driver_first_trans_fast(t11);
258
+
259
+LAB2:    t16 = (t0 + 7112);
260
+    *((int *)t16) = 1;
261
+
262
+LAB1:    return;
263
+LAB4:    goto LAB2;
264
+
265
+LAB5:    xsi_size_not_matching(9U, t9, 0);
266
+    goto LAB6;
267
+
268
+}
269
+
270
+static void work_a_2725559894_3212880686_p_4(char *t0)
271
+{
272
+    char t1[16];
273
+    char *t2;
274
+    char *t3;
275
+    char *t4;
276
+    char *t5;
277
+    char *t6;
278
+    char *t7;
279
+    unsigned int t8;
280
+    unsigned int t9;
281
+    unsigned char t10;
282
+    char *t11;
283
+    char *t12;
284
+    char *t13;
285
+    char *t14;
286
+    char *t15;
287
+    char *t16;
288
+
289
+LAB0:    xsi_set_current_line(58, ng0);
290
+
291
+LAB3:    t2 = (t0 + 1032U);
292
+    t3 = *((char **)t2);
293
+    t2 = (t0 + 11224U);
294
+    t4 = (t0 + 1192U);
295
+    t5 = *((char **)t4);
296
+    t4 = (t0 + 11240U);
297
+    t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
298
+    t7 = (t1 + 12U);
299
+    t8 = *((unsigned int *)t7);
300
+    t9 = (1U * t8);
301
+    t10 = (16U != t9);
302
+    if (t10 == 1)
303
+        goto LAB5;
304
+
305
+LAB6:    t11 = (t0 + 7560);
306
+    t12 = (t11 + 56U);
307
+    t13 = *((char **)t12);
308
+    t14 = (t13 + 56U);
309
+    t15 = *((char **)t14);
310
+    memcpy(t15, t6, 16U);
311
+    xsi_driver_first_trans_fast(t11);
312
+
313
+LAB2:    t16 = (t0 + 7128);
314
+    *((int *)t16) = 1;
315
+
316
+LAB1:    return;
317
+LAB4:    goto LAB2;
318
+
319
+LAB5:    xsi_size_not_matching(16U, t9, 0);
320
+    goto LAB6;
321
+
322
+}
323
+
324
+static void work_a_2725559894_3212880686_p_5(char *t0)
325
+{
326
+    char t5[16];
327
+    char t23[16];
328
+    char t41[16];
329
+    char *t1;
330
+    char *t2;
331
+    char *t3;
332
+    char *t6;
333
+    char *t7;
334
+    int t8;
335
+    unsigned int t9;
336
+    unsigned char t10;
337
+    char *t11;
338
+    unsigned int t12;
339
+    unsigned int t13;
340
+    char *t14;
341
+    char *t15;
342
+    char *t16;
343
+    char *t17;
344
+    char *t18;
345
+    char *t19;
346
+    char *t20;
347
+    char *t21;
348
+    char *t24;
349
+    char *t25;
350
+    int t26;
351
+    unsigned int t27;
352
+    unsigned char t28;
353
+    char *t29;
354
+    unsigned int t30;
355
+    unsigned int t31;
356
+    char *t32;
357
+    char *t33;
358
+    char *t34;
359
+    char *t35;
360
+    char *t36;
361
+    char *t37;
362
+    char *t38;
363
+    char *t39;
364
+    char *t42;
365
+    char *t43;
366
+    int t44;
367
+    unsigned int t45;
368
+    unsigned char t46;
369
+    char *t47;
370
+    unsigned int t48;
371
+    unsigned int t49;
372
+    char *t50;
373
+    char *t51;
374
+    char *t52;
375
+    char *t53;
376
+    char *t54;
377
+    char *t55;
378
+    char *t56;
379
+    char *t57;
380
+    char *t58;
381
+    char *t59;
382
+    char *t60;
383
+    char *t61;
384
+    char *t62;
385
+
386
+LAB0:    xsi_set_current_line(60, ng0);
387
+    t1 = (t0 + 1352U);
388
+    t2 = *((char **)t1);
389
+    t1 = (t0 + 11256U);
390
+    t3 = (t0 + 11473);
391
+    t6 = (t5 + 0U);
392
+    t7 = (t6 + 0U);
393
+    *((int *)t7) = 0;
394
+    t7 = (t6 + 4U);
395
+    *((int *)t7) = 1;
396
+    t7 = (t6 + 8U);
397
+    *((int *)t7) = 1;
398
+    t8 = (1 - 0);
399
+    t9 = (t8 * 1);
400
+    t9 = (t9 + 1);
401
+    t7 = (t6 + 12U);
402
+    *((unsigned int *)t7) = t9;
403
+    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
404
+    if (t10 != 0)
405
+        goto LAB3;
406
+
407
+LAB4:    t19 = (t0 + 1352U);
408
+    t20 = *((char **)t19);
409
+    t19 = (t0 + 11256U);
410
+    t21 = (t0 + 11475);
411
+    t24 = (t23 + 0U);
412
+    t25 = (t24 + 0U);
413
+    *((int *)t25) = 0;
414
+    t25 = (t24 + 4U);
415
+    *((int *)t25) = 1;
416
+    t25 = (t24 + 8U);
417
+    *((int *)t25) = 1;
418
+    t26 = (1 - 0);
419
+    t27 = (t26 * 1);
420
+    t27 = (t27 + 1);
421
+    t25 = (t24 + 12U);
422
+    *((unsigned int *)t25) = t27;
423
+    t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
424
+    if (t28 != 0)
425
+        goto LAB5;
426
+
427
+LAB6:    t37 = (t0 + 1352U);
428
+    t38 = *((char **)t37);
429
+    t37 = (t0 + 11256U);
430
+    t39 = (t0 + 11477);
431
+    t42 = (t41 + 0U);
432
+    t43 = (t42 + 0U);
433
+    *((int *)t43) = 0;
434
+    t43 = (t42 + 4U);
435
+    *((int *)t43) = 1;
436
+    t43 = (t42 + 8U);
437
+    *((int *)t43) = 1;
438
+    t44 = (1 - 0);
439
+    t45 = (t44 * 1);
440
+    t45 = (t45 + 1);
441
+    t43 = (t42 + 12U);
442
+    *((unsigned int *)t43) = t45;
443
+    t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
444
+    if (t46 != 0)
445
+        goto LAB7;
446
+
447
+LAB8:
448
+LAB9:    t55 = xsi_get_transient_memory(8U);
449
+    memset(t55, 0, 8U);
450
+    t56 = t55;
451
+    memset(t56, (unsigned char)2, 8U);
452
+    t57 = (t0 + 7624);
453
+    t58 = (t57 + 56U);
454
+    t59 = *((char **)t58);
455
+    t60 = (t59 + 56U);
456
+    t61 = *((char **)t60);
457
+    memcpy(t61, t55, 8U);
458
+    xsi_driver_first_trans_fast(t57);
459
+
460
+LAB2:    t62 = (t0 + 7144);
461
+    *((int *)t62) = 1;
462
+
463
+LAB1:    return;
464
+LAB3:    t7 = (t0 + 2632U);
465
+    t11 = *((char **)t7);
466
+    t9 = (8 - 7);
467
+    t12 = (t9 * 1U);
468
+    t13 = (0 + t12);
469
+    t7 = (t11 + t13);
470
+    t14 = (t0 + 7624);
471
+    t15 = (t14 + 56U);
472
+    t16 = *((char **)t15);
473
+    t17 = (t16 + 56U);
474
+    t18 = *((char **)t17);
475
+    memcpy(t18, t7, 8U);
476
+    xsi_driver_first_trans_fast(t14);
477
+    goto LAB2;
478
+
479
+LAB5:    t25 = (t0 + 2792U);
480
+    t29 = *((char **)t25);
481
+    t27 = (8 - 7);
482
+    t30 = (t27 * 1U);
483
+    t31 = (0 + t30);
484
+    t25 = (t29 + t31);
485
+    t32 = (t0 + 7624);
486
+    t33 = (t32 + 56U);
487
+    t34 = *((char **)t33);
488
+    t35 = (t34 + 56U);
489
+    t36 = *((char **)t35);
490
+    memcpy(t36, t25, 8U);
491
+    xsi_driver_first_trans_fast(t32);
492
+    goto LAB2;
493
+
494
+LAB7:    t43 = (t0 + 2952U);
495
+    t47 = *((char **)t43);
496
+    t45 = (15 - 7);
497
+    t48 = (t45 * 1U);
498
+    t49 = (0 + t48);
499
+    t43 = (t47 + t49);
500
+    t50 = (t0 + 7624);
501
+    t51 = (t50 + 56U);
502
+    t52 = *((char **)t51);
503
+    t53 = (t52 + 56U);
504
+    t54 = *((char **)t53);
505
+    memcpy(t54, t43, 8U);
506
+    xsi_driver_first_trans_fast(t50);
507
+    goto LAB2;
508
+
509
+LAB10:    goto LAB2;
510
+
511
+}
512
+
513
+static void work_a_2725559894_3212880686_p_6(char *t0)
514
+{
515
+    char t7[16];
516
+    char t13[16];
517
+    char t21[16];
518
+    unsigned char t1;
519
+    char *t2;
520
+    char *t3;
521
+    unsigned int t4;
522
+    unsigned int t5;
523
+    unsigned int t6;
524
+    char *t8;
525
+    char *t9;
526
+    int t10;
527
+    unsigned int t11;
528
+    char *t14;
529
+    char *t15;
530
+    int t16;
531
+    unsigned char t17;
532
+    char *t18;
533
+    char *t19;
534
+    char *t22;
535
+    char *t23;
536
+    int t24;
537
+    unsigned char t25;
538
+    char *t26;
539
+    char *t27;
540
+    char *t28;
541
+    char *t29;
542
+    char *t30;
543
+    char *t31;
544
+    char *t32;
545
+    char *t33;
546
+    char *t34;
547
+    char *t35;
548
+
549
+LAB0:    xsi_set_current_line(64, ng0);
550
+    t2 = (t0 + 2952U);
551
+    t3 = *((char **)t2);
552
+    t4 = (15 - 15);
553
+    t5 = (t4 * 1U);
554
+    t6 = (0 + t5);
555
+    t2 = (t3 + t6);
556
+    t8 = (t7 + 0U);
557
+    t9 = (t8 + 0U);
558
+    *((int *)t9) = 15;
559
+    t9 = (t8 + 4U);
560
+    *((int *)t9) = 8;
561
+    t9 = (t8 + 8U);
562
+    *((int *)t9) = -1;
563
+    t10 = (8 - 15);
564
+    t11 = (t10 * -1);
565
+    t11 = (t11 + 1);
566
+    t9 = (t8 + 12U);
567
+    *((unsigned int *)t9) = t11;
568
+    t9 = (t0 + 11479);
569
+    t14 = (t13 + 0U);
570
+    t15 = (t14 + 0U);
571
+    *((int *)t15) = 0;
572
+    t15 = (t14 + 4U);
573
+    *((int *)t15) = 7;
574
+    t15 = (t14 + 8U);
575
+    *((int *)t15) = 1;
576
+    t16 = (7 - 0);
577
+    t11 = (t16 * 1);
578
+    t11 = (t11 + 1);
579
+    t15 = (t14 + 12U);
580
+    *((unsigned int *)t15) = t11;
581
+    t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
582
+    if (t17 == 1)
583
+        goto LAB5;
584
+
585
+LAB6:    t1 = (unsigned char)0;
586
+
587
+LAB7:    if (t1 != 0)
588
+        goto LAB3;
589
+
590
+LAB4:
591
+LAB8:    t30 = (t0 + 7688);
592
+    t31 = (t30 + 56U);
593
+    t32 = *((char **)t31);
594
+    t33 = (t32 + 56U);
595
+    t34 = *((char **)t33);
596
+    *((unsigned char *)t34) = (unsigned char)2;
597
+    xsi_driver_first_trans_fast_port(t30);
598
+
599
+LAB2:    t35 = (t0 + 7160);
600
+    *((int *)t35) = 1;
601
+
602
+LAB1:    return;
603
+LAB3:    t23 = (t0 + 7688);
604
+    t26 = (t23 + 56U);
605
+    t27 = *((char **)t26);
606
+    t28 = (t27 + 56U);
607
+    t29 = *((char **)t28);
608
+    *((unsigned char *)t29) = (unsigned char)3;
609
+    xsi_driver_first_trans_fast_port(t23);
610
+    goto LAB2;
611
+
612
+LAB5:    t15 = (t0 + 1352U);
613
+    t18 = *((char **)t15);
614
+    t15 = (t0 + 11256U);
615
+    t19 = (t0 + 11487);
616
+    t22 = (t21 + 0U);
617
+    t23 = (t22 + 0U);
618
+    *((int *)t23) = 0;
619
+    t23 = (t22 + 4U);
620
+    *((int *)t23) = 2;
621
+    t23 = (t22 + 8U);
622
+    *((int *)t23) = 1;
623
+    t24 = (2 - 0);
624
+    t11 = (t24 * 1);
625
+    t11 = (t11 + 1);
626
+    t23 = (t22 + 12U);
627
+    *((unsigned int *)t23) = t11;
628
+    t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
629
+    t1 = t25;
630
+    goto LAB7;
631
+
632
+LAB9:    goto LAB2;
633
+
634
+}
635
+
636
+static void work_a_2725559894_3212880686_p_7(char *t0)
637
+{
638
+    char t14[16];
639
+    unsigned char t1;
640
+    char *t2;
641
+    char *t3;
642
+    int t4;
643
+    unsigned int t5;
644
+    unsigned int t6;
645
+    unsigned int t7;
646
+    unsigned char t8;
647
+    unsigned char t9;
648
+    char *t10;
649
+    char *t11;
650
+    char *t12;
651
+    char *t15;
652
+    char *t16;
653
+    int t17;
654
+    unsigned int t18;
655
+    unsigned char t19;
656
+    char *t20;
657
+    char *t21;
658
+    char *t22;
659
+    char *t23;
660
+    char *t24;
661
+    char *t25;
662
+    char *t26;
663
+    char *t27;
664
+    char *t28;
665
+    char *t29;
666
+
667
+LAB0:    xsi_set_current_line(66, ng0);
668
+    t2 = (t0 + 2632U);
669
+    t3 = *((char **)t2);
670
+    t4 = (8 - 8);
671
+    t5 = (t4 * -1);
672
+    t6 = (1U * t5);
673
+    t7 = (0 + t6);
674
+    t2 = (t3 + t7);
675
+    t8 = *((unsigned char *)t2);
676
+    t9 = (t8 == (unsigned char)3);
677
+    if (t9 == 1)
678
+        goto LAB5;
679
+
680
+LAB6:    t1 = (unsigned char)0;
681
+
682
+LAB7:    if (t1 != 0)
683
+        goto LAB3;
684
+
685
+LAB4:
686
+LAB8:    t24 = (t0 + 7752);
687
+    t25 = (t24 + 56U);
688
+    t26 = *((char **)t25);
689
+    t27 = (t26 + 56U);
690
+    t28 = *((char **)t27);
691
+    *((unsigned char *)t28) = (unsigned char)2;
692
+    xsi_driver_first_trans_fast_port(t24);
693
+
694
+LAB2:    t29 = (t0 + 7176);
695
+    *((int *)t29) = 1;
696
+
697
+LAB1:    return;
698
+LAB3:    t16 = (t0 + 7752);
699
+    t20 = (t16 + 56U);
700
+    t21 = *((char **)t20);
701
+    t22 = (t21 + 56U);
702
+    t23 = *((char **)t22);
703
+    *((unsigned char *)t23) = (unsigned char)3;
704
+    xsi_driver_first_trans_fast_port(t16);
705
+    goto LAB2;
706
+
707
+LAB5:    t10 = (t0 + 1352U);
708
+    t11 = *((char **)t10);
709
+    t10 = (t0 + 11256U);
710
+    t12 = (t0 + 11490);
711
+    t15 = (t14 + 0U);
712
+    t16 = (t15 + 0U);
713
+    *((int *)t16) = 0;
714
+    t16 = (t15 + 4U);
715
+    *((int *)t16) = 1;
716
+    t16 = (t15 + 8U);
717
+    *((int *)t16) = 1;
718
+    t17 = (1 - 0);
719
+    t18 = (t17 * 1);
720
+    t18 = (t18 + 1);
721
+    t16 = (t15 + 12U);
722
+    *((unsigned int *)t16) = t18;
723
+    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
724
+    t1 = t19;
725
+    goto LAB7;
726
+
727
+LAB9:    goto LAB2;
728
+
729
+}
730
+
731
+static void work_a_2725559894_3212880686_p_8(char *t0)
732
+{
733
+    char t14[16];
734
+    unsigned char t1;
735
+    char *t2;
736
+    char *t3;
737
+    int t4;
738
+    unsigned int t5;
739
+    unsigned int t6;
740
+    unsigned int t7;
741
+    unsigned char t8;
742
+    unsigned char t9;
743
+    char *t10;
744
+    char *t11;
745
+    char *t12;
746
+    char *t15;
747
+    char *t16;
748
+    int t17;
749
+    unsigned int t18;
750
+    unsigned char t19;
751
+    char *t20;
752
+    char *t21;
753
+    char *t22;
754
+    char *t23;
755
+    char *t24;
756
+    char *t25;
757
+    char *t26;
758
+    char *t27;
759
+    char *t28;
760
+    char *t29;
761
+
762
+LAB0:    xsi_set_current_line(68, ng0);
763
+    t2 = (t0 + 2792U);
764
+    t3 = *((char **)t2);
765
+    t4 = (8 - 8);
766
+    t5 = (t4 * -1);
767
+    t6 = (1U * t5);
768
+    t7 = (0 + t6);
769
+    t2 = (t3 + t7);
770
+    t8 = *((unsigned char *)t2);
771
+    t9 = (t8 == (unsigned char)3);
772
+    if (t9 == 1)
773
+        goto LAB5;
774
+
775
+LAB6:    t1 = (unsigned char)0;
776
+
777
+LAB7:    if (t1 != 0)
778
+        goto LAB3;
779
+
780
+LAB4:
781
+LAB8:    t24 = (t0 + 7816);
782
+    t25 = (t24 + 56U);
783
+    t26 = *((char **)t25);
784
+    t27 = (t26 + 56U);
785
+    t28 = *((char **)t27);
786
+    *((unsigned char *)t28) = (unsigned char)2;
787
+    xsi_driver_first_trans_fast_port(t24);
788
+
789
+LAB2:    t29 = (t0 + 7192);
790
+    *((int *)t29) = 1;
791
+
792
+LAB1:    return;
793
+LAB3:    t16 = (t0 + 7816);
794
+    t20 = (t16 + 56U);
795
+    t21 = *((char **)t20);
796
+    t22 = (t21 + 56U);
797
+    t23 = *((char **)t22);
798
+    *((unsigned char *)t23) = (unsigned char)3;
799
+    xsi_driver_first_trans_fast_port(t16);
800
+    goto LAB2;
801
+
802
+LAB5:    t10 = (t0 + 1352U);
803
+    t11 = *((char **)t10);
804
+    t10 = (t0 + 11256U);
805
+    t12 = (t0 + 11492);
806
+    t15 = (t14 + 0U);
807
+    t16 = (t15 + 0U);
808
+    *((int *)t16) = 0;
809
+    t16 = (t15 + 4U);
810
+    *((int *)t16) = 1;
811
+    t16 = (t15 + 8U);
812
+    *((int *)t16) = 1;
813
+    t17 = (1 - 0);
814
+    t18 = (t17 * 1);
815
+    t18 = (t18 + 1);
816
+    t16 = (t15 + 12U);
817
+    *((unsigned int *)t16) = t18;
818
+    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
819
+    t1 = t19;
820
+    goto LAB7;
821
+
822
+LAB9:    goto LAB2;
823
+
824
+}
825
+
826
+static void work_a_2725559894_3212880686_p_9(char *t0)
827
+{
828
+    char t5[16];
829
+    char *t1;
830
+    char *t2;
831