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BR OK + BM OK + Tests et pipeline à faire

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This commit is contained in:
Foussats Morgane 2021-04-15 11:07:53 +02:00
parent 56676de078
commit 344eba4dde
69 changed files with 768 additions and 2249 deletions
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65
xilinx/ALU/ALU.gise
View file

@ -23,13 +23,14 @@
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="alu_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="alu_test_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
@ -40,23 +41,28 @@
</transform>
<transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1618303356">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618304610">
<transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618476857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/>
<outfile xil_pn:name="bm_instr.vhd"/>
<outfile xil_pn:name="bm_instr_test.vhd"/>
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-6587339501330506153" xil_pn:start_ts="1618304817">
<transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3025547276878941811" xil_pn:start_ts="1618476689">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1575583835443101483" xil_pn:start_ts="1618304817">
<transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-323741304737568527" xil_pn:start_ts="1618476689">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
@ -64,37 +70,44 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618304610">
<transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618476857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="alu.vhd"/>
<outfile xil_pn:name="alu_test.vhd"/>
<outfile xil_pn:name="bm.vhd"/>
<outfile xil_pn:name="bm_instr.vhd"/>
<outfile xil_pn:name="bm_instr_test.vhd"/>
<outfile xil_pn:name="br.vhd"/>
<outfile xil_pn:name="br_test.vhd"/>
</transform>
<transform xil_pn:end_ts="1618304818" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="5625932807789681934" xil_pn:start_ts="1618304817">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1618304818" xil_pn:in_ck="-4068278894953614943" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5179862647015444475" xil_pn:start_ts="1618304818">
<transform xil_pn:end_ts="1618476859" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6397320030221382938" xil_pn:start_ts="1618476857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="bm_instr_test_beh.prj"/>
<outfile xil_pn:name="bm_instr_test_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1618476860" xil_pn:in_ck="-6291911114616255345" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1618476859">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="bm_instr_test_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
</transform>
</transforms>

69
xilinx/ALU/ALU.xise
View file

@ -16,26 +16,44 @@
<files>
<file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@ -49,8 +67,6 @@
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@ -67,56 +83,45 @@
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx16" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
@ -124,12 +129,10 @@
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@ -156,12 +159,9 @@
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -179,7 +179,6 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
@ -200,7 +199,6 @@
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
@ -212,7 +210,6 @@
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@ -243,7 +240,6 @@
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
@ -251,9 +247,7 @@
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@ -271,7 +265,6 @@
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@ -296,7 +289,6 @@
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
@ -305,12 +297,10 @@
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@ -325,8 +315,6 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@ -351,35 +339,28 @@
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|alu_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_instr_test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

5
xilinx/ALU/_xmsgs/pn_parser.xmsgs
View file

@ -8,10 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd&quot; into library work</arg>
</msg>
<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd</arg>&quot; Line <arg fmt="%d" index="2">47</arg>. <arg fmt="%s" index="3">Syntax error near &quot;CLK&quot;.</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
</msg>
</messages>

6
xilinx/ALU/alu_summary.html
View file

@ -7,7 +7,7 @@
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>ALU.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
@ -72,9 +72,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. avr. 13 11:14:16 2021</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>jeu. avr. 15 10:54:50 2021</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 04/13/2021 - 11:53:22</center>
<br><center><b>Date Generated:</b> 04/15/2021 - 10:56:37</center>
</BODY></HTML>

2
xilinx/ALU/alu_test_beh.prj
View file

@ -1,2 +0,0 @@
vhdl work "alu.vhd"
vhdl work "alu_test.vhd"

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xilinx/ALU/alu_test_isim_beh.wdb
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55
xilinx/ALU/bm.vhd Normal file
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@ -0,0 +1,55 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:32:11 04/15/2021
-- Design Name:
-- Module Name: bm_data - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bm_data is
Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
IN_data : in STD_LOGIC_VECTOR (7 downto 0);
RW : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
OUT_data : out STD_LOGIC_VECTOR (7 downto 0));
end bm_data;
architecture Behavioral of bm_data is
type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
signal data_memory: mem;
begin
process
begin
wait until rising_edge(CLK);
if RW = '1' then
OUT_data <= data_memory(to_integer(unsigned(IN_addr)));
else
data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
end if;
if RST='0' then
registres <= (others => "00000000");
end if;
end process;
end Behavioral;

44
xilinx/ALU/bm_instr.vhd Normal file
View file

@ -0,0 +1,44 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:40:07 04/15/2021
-- Design Name:
-- Module Name: bm_instr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bm_instr is
Port ( IN_addr : in STD_LOGIC_VECTOR (7 downto 0);
OUT_data : out STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC);
end bm_instr;
architecture Behavioral of bm_instr is
type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
signal instr_memory: mem := (1 => "00000001", others =>"00000000");
begin
OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));
end Behavioral;

97
xilinx/ALU/bm_instr_test.vhd Normal file
View file

@ -0,0 +1,97 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:42:17 04/15/2021
-- Design Name:
-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: bm_instr
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY bm_instr_test IS
END bm_instr_test;
ARCHITECTURE behavior OF bm_instr_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT bm_instr
PORT(
IN_addr : IN std_logic_vector(7 downto 0);
OUT_data : OUT std_logic_vector(7 downto 0);
CLK : IN std_logic
);
END COMPONENT;
--Inputs
signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal OUT_data : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: bm_instr PORT MAP (
IN_addr => IN_addr,
OUT_data => OUT_data,
CLK => CLK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
IN_addr <= "00000001";
wait for 100 ns;
IN_addr <= "00001001";
wait;
end process;
END;

2
xilinx/ALU/bm_instr_test_beh.prj Normal file
View file

@ -0,0 +1,2 @@
vhdl work "bm_instr.vhd"
vhdl work "bm_instr_test.vhd"

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xilinx/ALU/bm_instr_test_isim_beh.exe Executable file
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xilinx/ALU/bm_instr_test_isim_beh.wdb Normal file
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15
xilinx/ALU/br.vhd
View file

@ -44,18 +44,17 @@ signal registres: reg;
begin
process
begin
wait until CLK'event CLK = '1';
wait until rising_edge(CLK);
if W = '1' then
registres(W_addr) <= Data;
else
registres(to_integer(unsigned(W_addr))) <= Data;
end if;
if RST='0' then
QA <= "00000000";
QB <= "00000000";
registres <= (others => "00000000");
end if;
end process;
QA <= registres(to_integer(unsigned(A_addr))) when W ='0' or A_addr /= W_addr
else Data;
QB <= registres(to_integer(unsigned(B_addr))) when W ='0' or B_addr /= W_addr
else Data;
end Behavioral;

126
xilinx/ALU/br_test.vhd Normal file
View file

@ -0,0 +1,126 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:35:26 04/15/2021
-- Design Name:
-- Module Name: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd
-- Project Name: ALU
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: br
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY br_test IS
END br_test;
ARCHITECTURE behavior OF br_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT br
PORT(
A_addr : IN std_logic_vector(3 downto 0);
B_addr : IN std_logic_vector(3 downto 0);
W_addr : IN std_logic_vector(3 downto 0);
W : IN std_logic;
Data : IN std_logic_vector(7 downto 0);
RST : IN std_logic;
CLK : IN std_logic;
QA : OUT std_logic_vector(7 downto 0);
QB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal A_addr : std_logic_vector(3 downto 0) := (others => '0');
signal B_addr : std_logic_vector(3 downto 0) := (others => '0');
signal W_addr : std_logic_vector(3 downto 0) := (others => '0');
signal W : std_logic := '0';
signal Data : std_logic_vector(7 downto 0) := (others => '0');
signal RST : std_logic := '0';
signal CLK : std_logic := '0';
--Outputs
signal QA : std_logic_vector(7 downto 0);
signal QB : std_logic_vector(7 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: br PORT MAP (
A_addr => A_addr,
B_addr => B_addr,
W_addr => W_addr,
W => W,
Data => Data,
RST => RST,
CLK => CLK,
QA => QA,
QB => QB
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period*10;
RST <= '1';
wait for 100 ns ;
DATA <= "10000000";
wait for 100 ns ;
W_addr <= "0000";
wait for 100 ns ;
W <= '1';
wait for 100 ns ;
W <= '0';
wait for 100 ns ;
A_addr <= "0000" ;
B_addr <= "0001" ;
wait;
end process;
END;

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24
xilinx/ALU/fuse.log
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@ -1,25 +1,25 @@
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test"
Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj work.bm_instr_test
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 12
Turning on mult-threading, number of parallel sub-compilation jobs: 24
Number of CPUs detected in this system: 6
Turning on mult-threading, number of parallel sub-compilation jobs: 12
Determining compilation order of HDL files
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 98500 KB
Fuse CPU Usage: 810 ms
Fuse CPU Usage: 750 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package numeric_std
Compiling architecture behavioral of entity alu [alu_default]
Compiling architecture behavior of entity alu_test
Compiling architecture behavioral of entity bm_instr [bm_instr_default]
Compiling architecture behavior of entity bm_instr_test
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 8 VHDL Units
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe
Fuse Memory Usage: 1722952 KB
Fuse CPU Usage: 920 ms
GCC CPU Usage: 80 ms
Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe
Fuse Memory Usage: 936380 KB
Fuse CPU Usage: 840 ms
GCC CPU Usage: 1640 ms

2
xilinx/ALU/fuseRelaunch.cmd
View file

@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test"
-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj" "work.bm_instr_test"

33
xilinx/ALU/iseconfig/ALU.projectmgr
View file

@ -1,4 +1,4 @@
<?xml version="1.0" encoding="utf-8"?>
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
@ -9,13 +9,13 @@
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>ALU</SelectedItem>
<SelectedItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000200000064ffffffff000000810000000300000002000001040000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000145000000020000000000000000000000000200000064ffffffff000000810000000300000002000001450000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>ALU</CurrentItem>
<CurrentItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
@ -23,13 +23,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
@ -40,7 +40,7 @@
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004f0000000100000000000000390000000100000000000000830000000100000000000002960000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>alu.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
@ -50,7 +50,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000010001000100000000000000000000000064ffffffff000000810000000000000001000003a10000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
@ -68,21 +68,20 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode></ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000b0000000020000000000000000000000000200000064ffffffff000000810000000300000002000000b00000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000184000000020000000000000000000000000200000064ffffffff000000810000000300000002000001840000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</CurrentItem>
</ItemView>
@ -104,13 +103,13 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
@ -118,13 +117,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<SourceProcessView>000000ff0000000000000002000001620000011b01000000040100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>

4
xilinx/ALU/iseconfig/alu.xreport
View file

@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2021-04-13T11:53:22</DateModified>
<DateModified>2021-04-15T10:56:37</DateModified>
<ModuleName>alu</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
<ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
<DateInitialized>2021-04-13T10:12:38</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>

21
xilinx/ALU/isim.log
View file

@ -1,5 +1,5 @@
ISim log file
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.wdb
Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@ -10,24 +10,5 @@ Time resolution is 1 ps
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
ISim O.87xd (signature 0x8ddf5b5d)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
Finished circuit initialization process.
# exit 0

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe
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Binary file not shown.

29
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimkernel.log
View file

@ -1,29 +0,0 @@
Command line:
alu_isim_beh.exe
-simmode gui
-simrunnum 1
-socket 46007
Tue Apr 13 11:05:00 2021
Elaboration Time: 0 sec
Current Memory Usage: 181.678 Meg
Total Signals : 14
Total Nets : 91
Total Signal Drivers : 11
Total Blocks : 5
Total Primitive Blocks : 5
Total Processes : 11
Total Traceable Variables : 15
Total Scalar Nets and Variables : 592
Total Line Count : 11
Total Simulation Time: 0.08 sec
Current Memory Usage: 257.18 Meg
Tue Apr 13 11:05:21 2021

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/netId1.dat
View file

Binary file not shown.

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/tmp_save/_1
View file

Binary file not shown.

931
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.c
View file

@ -1,931 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_3620187407;
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
static void work_a_2725559894_3212880686_p_0(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(54, ng0);
LAB3: t1 = (t0 + 11471);
t3 = (t0 + 1032U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11224U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7304);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7064);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_1(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(55, ng0);
LAB3: t1 = (t0 + 11472);
t3 = (t0 + 1192U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11240U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7368);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7080);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(56, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7096);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_3(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(57, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7496);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7112);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(58, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 11224U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 11240U);
t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (16U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 16U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7128);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(16U, t9, 0);
goto LAB6;
}
static void work_a_2725559894_3212880686_p_5(char *t0)
{
char t5[16];
char t23[16];
char t41[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
unsigned int t12;
unsigned int t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t24;
char *t25;
int t26;
unsigned int t27;
unsigned char t28;
char *t29;
unsigned int t30;
unsigned int t31;
char *t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
char *t38;
char *t39;
char *t42;
char *t43;
int t44;
unsigned int t45;
unsigned char t46;
char *t47;
unsigned int t48;
unsigned int t49;
char *t50;
char *t51;
char *t52;
char *t53;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
LAB0: xsi_set_current_line(60, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t1 = (t0 + 11256U);
t3 = (t0 + 11473);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 1;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (1 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4: t19 = (t0 + 1352U);
t20 = *((char **)t19);
t19 = (t0 + 11256U);
t21 = (t0 + 11475);
t24 = (t23 + 0U);
t25 = (t24 + 0U);
*((int *)t25) = 0;
t25 = (t24 + 4U);
*((int *)t25) = 1;
t25 = (t24 + 8U);
*((int *)t25) = 1;
t26 = (1 - 0);
t27 = (t26 * 1);
t27 = (t27 + 1);
t25 = (t24 + 12U);
*((unsigned int *)t25) = t27;
t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
if (t28 != 0)
goto LAB5;
LAB6: t37 = (t0 + 1352U);
t38 = *((char **)t37);
t37 = (t0 + 11256U);
t39 = (t0 + 11477);
t42 = (t41 + 0U);
t43 = (t42 + 0U);
*((int *)t43) = 0;
t43 = (t42 + 4U);
*((int *)t43) = 1;
t43 = (t42 + 8U);
*((int *)t43) = 1;
t44 = (1 - 0);
t45 = (t44 * 1);
t45 = (t45 + 1);
t43 = (t42 + 12U);
*((unsigned int *)t43) = t45;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
if (t46 != 0)
goto LAB7;
LAB8:
LAB9: t55 = xsi_get_transient_memory(8U);
memset(t55, 0, 8U);
t56 = t55;
memset(t56, (unsigned char)2, 8U);
t57 = (t0 + 7624);
t58 = (t57 + 56U);
t59 = *((char **)t58);
t60 = (t59 + 56U);
t61 = *((char **)t60);
memcpy(t61, t55, 8U);
xsi_driver_first_trans_fast(t57);
LAB2: t62 = (t0 + 7144);
*((int *)t62) = 1;
LAB1: return;
LAB3: t7 = (t0 + 2632U);
t11 = *((char **)t7);
t9 = (8 - 7);
t12 = (t9 * 1U);
t13 = (0 + t12);
t7 = (t11 + t13);
t14 = (t0 + 7624);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t7, 8U);
xsi_driver_first_trans_fast(t14);
goto LAB2;
LAB5: t25 = (t0 + 2792U);
t29 = *((char **)t25);
t27 = (8 - 7);
t30 = (t27 * 1U);
t31 = (0 + t30);
t25 = (t29 + t31);
t32 = (t0 + 7624);
t33 = (t32 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
memcpy(t36, t25, 8U);
xsi_driver_first_trans_fast(t32);
goto LAB2;
LAB7: t43 = (t0 + 2952U);
t47 = *((char **)t43);
t45 = (15 - 7);
t48 = (t45 * 1U);
t49 = (0 + t48);
t43 = (t47 + t49);
t50 = (t0 + 7624);
t51 = (t50 + 56U);
t52 = *((char **)t51);
t53 = (t52 + 56U);
t54 = *((char **)t53);
memcpy(t54, t43, 8U);
xsi_driver_first_trans_fast(t50);
goto LAB2;
LAB10: goto LAB2;
}
static void work_a_2725559894_3212880686_p_6(char *t0)
{
char t7[16];
char t13[16];
char t21[16];
unsigned char t1;
char *t2;
char *t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
char *t14;
char *t15;
int t16;
unsigned char t17;
char *t18;
char *t19;
char *t22;
char *t23;
int t24;
unsigned char t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
char *t32;
char *t33;
char *t34;
char *t35;
LAB0: xsi_set_current_line(64, ng0);
t2 = (t0 + 2952U);
t3 = *((char **)t2);
t4 = (15 - 15);
t5 = (t4 * 1U);
t6 = (0 + t5);
t2 = (t3 + t6);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 15;
t9 = (t8 + 4U);
*((int *)t9) = 8;
t9 = (t8 + 8U);
*((int *)t9) = -1;
t10 = (8 - 15);
t11 = (t10 * -1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11479);
t14 = (t13 + 0U);
t15 = (t14 + 0U);
*((int *)t15) = 0;
t15 = (t14 + 4U);
*((int *)t15) = 7;
t15 = (t14 + 8U);
*((int *)t15) = 1;
t16 = (7 - 0);
t11 = (t16 * 1);
t11 = (t11 + 1);
t15 = (t14 + 12U);
*((unsigned int *)t15) = t11;
t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
if (t17 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t30 = (t0 + 7688);
t31 = (t30 + 56U);
t32 = *((char **)t31);
t33 = (t32 + 56U);
t34 = *((char **)t33);
*((unsigned char *)t34) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t30);
LAB2: t35 = (t0 + 7160);
*((int *)t35) = 1;
LAB1: return;
LAB3: t23 = (t0 + 7688);
t26 = (t23 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
*((unsigned char *)t29) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t23);
goto LAB2;
LAB5: t15 = (t0 + 1352U);
t18 = *((char **)t15);
t15 = (t0 + 11256U);
t19 = (t0 + 11487);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
t23 = (t22 + 4U);
*((int *)t23) = 2;
t23 = (t22 + 8U);
*((int *)t23) = 1;
t24 = (2 - 0);
t11 = (t24 * 1);
t11 = (t11 + 1);
t23 = (t22 + 12U);
*((unsigned int *)t23) = t11;
t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
t1 = t25;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_7(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(66, ng0);
t2 = (t0 + 2632U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7752);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7176);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7752);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11490);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_8(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(68, ng0);
t2 = (t0 + 2792U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7816);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7192);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7816);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11492);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_2725559894_3212880686_p_9(char *t0)
{
char t5[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
LAB0: xsi_set_current_line(70, ng0);
t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 11368U);
t3 = (t0 + 11494);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 7;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (7 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4:
LAB5: t15 = (t0 + 7880);
t16 = (t15 + 56U);
t17 = *((char **)t16);
t18 = (t17 + 56U);
t19 = *((char **)t18);
*((unsigned char *)t19) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t15);
LAB2: t20 = (t0 + 7208);
*((int *)t20) = 1;
LAB1: return;
LAB3: t7 = (t0 + 7880);
t11 = (t7 + 56U);
t12 = *((char **)t11);
t13 = (t12 + 56U);
t14 = *((char **)t13);
*((unsigned char *)t14) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t7);
goto LAB2;
LAB6: goto LAB2;
}
static void work_a_2725559894_3212880686_p_10(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(72, ng0);
LAB3: t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 7944);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 7224);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_2725559894_3212880686_init()
{
static char *pe[] = {(void *)work_a_2725559894_3212880686_p_0,(void *)work_a_2725559894_3212880686_p_1,(void *)work_a_2725559894_3212880686_p_2,(void *)work_a_2725559894_3212880686_p_3,(void *)work_a_2725559894_3212880686_p_4,(void *)work_a_2725559894_3212880686_p_5,(void *)work_a_2725559894_3212880686_p_6,(void *)work_a_2725559894_3212880686_p_7,(void *)work_a_2725559894_3212880686_p_8,(void *)work_a_2725559894_3212880686_p_9,(void *)work_a_2725559894_3212880686_p_10};
xsi_register_didat("work_a_2725559894_3212880686", "isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat
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xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.lin64.o
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xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.lin64.o
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xilinx/ALU/isim/alu_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
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xilinx/ALU/isim/alu_test_isim_beh.exe.sim/alu_test_isim_beh.exe
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29
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimkernel.log
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@ -1,29 +0,0 @@
Command line:
alu_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 38597
Tue Apr 13 11:10:10 2021
Elaboration Time: 0.01 sec
Current Memory Usage: 181.686 Meg
Total Signals : 22
Total Nets : 91
Total Signal Drivers : 14
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 12
Total Traceable Variables : 15
Total Scalar Nets and Variables : 592
Total Line Count : 18
Total Simulation Time: 0.19 sec
Current Memory Usage: 257.188 Meg
Tue Apr 13 11:14:15 2021

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xilinx/ALU/isim/alu_test_isim_beh.exe.sim/netId.dat
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931
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c
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@ -1,931 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_3620187407;
unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
static void work_a_0832606739_3212880686_p_0(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(54, ng0);
LAB3: t1 = (t0 + 11471);
t3 = (t0 + 1032U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11224U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7304);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7064);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_1(char *t0)
{
char t5[16];
char t7[16];
char *t1;
char *t3;
char *t4;
char *t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(55, ng0);
LAB3: t1 = (t0 + 11472);
t3 = (t0 + 1192U);
t4 = *((char **)t3);
t6 = ((IEEE_P_2592010699) + 4000);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 0;
t9 = (t8 + 4U);
*((int *)t9) = 0;
t9 = (t8 + 8U);
*((int *)t9) = 1;
t10 = (0 - 0);
t11 = (t10 * 1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11240U);
t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
t11 = (1U + 8U);
t12 = (9U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 7368);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t3, 9U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 7080);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t11, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(56, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7096);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_3(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(57, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 11288U);
t4 = (t0 + 2472U);
t5 = *((char **)t4);
t4 = (t0 + 11304U);
t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (9U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7496);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 9U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7112);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(9U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(58, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 11224U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 11240U);
t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (16U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 7560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 16U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 7128);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(16U, t9, 0);
goto LAB6;
}
static void work_a_0832606739_3212880686_p_5(char *t0)
{
char t5[16];
char t23[16];
char t41[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
unsigned int t12;
unsigned int t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t24;
char *t25;
int t26;
unsigned int t27;
unsigned char t28;
char *t29;
unsigned int t30;
unsigned int t31;
char *t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
char *t38;
char *t39;
char *t42;
char *t43;
int t44;
unsigned int t45;
unsigned char t46;
char *t47;
unsigned int t48;
unsigned int t49;
char *t50;
char *t51;
char *t52;
char *t53;
char *t54;
char *t55;
char *t56;
char *t57;
char *t58;
char *t59;
char *t60;
char *t61;
char *t62;
LAB0: xsi_set_current_line(60, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t1 = (t0 + 11256U);
t3 = (t0 + 11473);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 1;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (1 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4: t19 = (t0 + 1352U);
t20 = *((char **)t19);
t19 = (t0 + 11256U);
t21 = (t0 + 11475);
t24 = (t23 + 0U);
t25 = (t24 + 0U);
*((int *)t25) = 0;
t25 = (t24 + 4U);
*((int *)t25) = 1;
t25 = (t24 + 8U);
*((int *)t25) = 1;
t26 = (1 - 0);
t27 = (t26 * 1);
t27 = (t27 + 1);
t25 = (t24 + 12U);
*((unsigned int *)t25) = t27;
t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
if (t28 != 0)
goto LAB5;
LAB6: t37 = (t0 + 1352U);
t38 = *((char **)t37);
t37 = (t0 + 11256U);
t39 = (t0 + 11477);
t42 = (t41 + 0U);
t43 = (t42 + 0U);
*((int *)t43) = 0;
t43 = (t42 + 4U);
*((int *)t43) = 1;
t43 = (t42 + 8U);
*((int *)t43) = 1;
t44 = (1 - 0);
t45 = (t44 * 1);
t45 = (t45 + 1);
t43 = (t42 + 12U);
*((unsigned int *)t43) = t45;
t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
if (t46 != 0)
goto LAB7;
LAB8:
LAB9: t55 = xsi_get_transient_memory(8U);
memset(t55, 0, 8U);
t56 = t55;
memset(t56, (unsigned char)2, 8U);
t57 = (t0 + 7624);
t58 = (t57 + 56U);
t59 = *((char **)t58);
t60 = (t59 + 56U);
t61 = *((char **)t60);
memcpy(t61, t55, 8U);
xsi_driver_first_trans_fast(t57);
LAB2: t62 = (t0 + 7144);
*((int *)t62) = 1;
LAB1: return;
LAB3: t7 = (t0 + 2632U);
t11 = *((char **)t7);
t9 = (8 - 7);
t12 = (t9 * 1U);
t13 = (0 + t12);
t7 = (t11 + t13);
t14 = (t0 + 7624);
t15 = (t14 + 56U);
t16 = *((char **)t15);
t17 = (t16 + 56U);
t18 = *((char **)t17);
memcpy(t18, t7, 8U);
xsi_driver_first_trans_fast(t14);
goto LAB2;
LAB5: t25 = (t0 + 2792U);
t29 = *((char **)t25);
t27 = (8 - 7);
t30 = (t27 * 1U);
t31 = (0 + t30);
t25 = (t29 + t31);
t32 = (t0 + 7624);
t33 = (t32 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
memcpy(t36, t25, 8U);
xsi_driver_first_trans_fast(t32);
goto LAB2;
LAB7: t43 = (t0 + 2952U);
t47 = *((char **)t43);
t45 = (15 - 7);
t48 = (t45 * 1U);
t49 = (0 + t48);
t43 = (t47 + t49);
t50 = (t0 + 7624);
t51 = (t50 + 56U);
t52 = *((char **)t51);
t53 = (t52 + 56U);
t54 = *((char **)t53);
memcpy(t54, t43, 8U);
xsi_driver_first_trans_fast(t50);
goto LAB2;
LAB10: goto LAB2;
}
static void work_a_0832606739_3212880686_p_6(char *t0)
{
char t7[16];
char t13[16];
char t21[16];
unsigned char t1;
char *t2;
char *t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
char *t8;
char *t9;
int t10;
unsigned int t11;
char *t14;
char *t15;
int t16;
unsigned char t17;
char *t18;
char *t19;
char *t22;
char *t23;
int t24;
unsigned char t25;
char *t26;
char *t27;
char *t28;
char *t29;
char *t30;
char *t31;
char *t32;
char *t33;
char *t34;
char *t35;
LAB0: xsi_set_current_line(64, ng0);
t2 = (t0 + 2952U);
t3 = *((char **)t2);
t4 = (15 - 15);
t5 = (t4 * 1U);
t6 = (0 + t5);
t2 = (t3 + t6);
t8 = (t7 + 0U);
t9 = (t8 + 0U);
*((int *)t9) = 15;
t9 = (t8 + 4U);
*((int *)t9) = 8;
t9 = (t8 + 8U);
*((int *)t9) = -1;
t10 = (8 - 15);
t11 = (t10 * -1);
t11 = (t11 + 1);
t9 = (t8 + 12U);
*((unsigned int *)t9) = t11;
t9 = (t0 + 11479);
t14 = (t13 + 0U);
t15 = (t14 + 0U);
*((int *)t15) = 0;
t15 = (t14 + 4U);
*((int *)t15) = 7;
t15 = (t14 + 8U);
*((int *)t15) = 1;
t16 = (7 - 0);
t11 = (t16 * 1);
t11 = (t11 + 1);
t15 = (t14 + 12U);
*((unsigned int *)t15) = t11;
t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
if (t17 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t30 = (t0 + 7688);
t31 = (t30 + 56U);
t32 = *((char **)t31);
t33 = (t32 + 56U);
t34 = *((char **)t33);
*((unsigned char *)t34) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t30);
LAB2: t35 = (t0 + 7160);
*((int *)t35) = 1;
LAB1: return;
LAB3: t23 = (t0 + 7688);
t26 = (t23 + 56U);
t27 = *((char **)t26);
t28 = (t27 + 56U);
t29 = *((char **)t28);
*((unsigned char *)t29) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t23);
goto LAB2;
LAB5: t15 = (t0 + 1352U);
t18 = *((char **)t15);
t15 = (t0 + 11256U);
t19 = (t0 + 11487);
t22 = (t21 + 0U);
t23 = (t22 + 0U);
*((int *)t23) = 0;
t23 = (t22 + 4U);
*((int *)t23) = 2;
t23 = (t22 + 8U);
*((int *)t23) = 1;
t24 = (2 - 0);
t11 = (t24 * 1);
t11 = (t11 + 1);
t23 = (t22 + 12U);
*((unsigned int *)t23) = t11;
t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
t1 = t25;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_7(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(66, ng0);
t2 = (t0 + 2632U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7752);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7176);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7752);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11490);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_8(char *t0)
{
char t14[16];
unsigned char t1;
char *t2;
char *t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t15;
char *t16;
int t17;
unsigned int t18;
unsigned char t19;
char *t20;
char *t21;
char *t22;
char *t23;
char *t24;
char *t25;
char *t26;
char *t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(68, ng0);
t2 = (t0 + 2792U);
t3 = *((char **)t2);
t4 = (8 - 8);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t2 = (t3 + t7);
t8 = *((unsigned char *)t2);
t9 = (t8 == (unsigned char)3);
if (t9 == 1)
goto LAB5;
LAB6: t1 = (unsigned char)0;
LAB7: if (t1 != 0)
goto LAB3;
LAB4:
LAB8: t24 = (t0 + 7816);
t25 = (t24 + 56U);
t26 = *((char **)t25);
t27 = (t26 + 56U);
t28 = *((char **)t27);
*((unsigned char *)t28) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t24);
LAB2: t29 = (t0 + 7192);
*((int *)t29) = 1;
LAB1: return;
LAB3: t16 = (t0 + 7816);
t20 = (t16 + 56U);
t21 = *((char **)t20);
t22 = (t21 + 56U);
t23 = *((char **)t22);
*((unsigned char *)t23) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t16);
goto LAB2;
LAB5: t10 = (t0 + 1352U);
t11 = *((char **)t10);
t10 = (t0 + 11256U);
t12 = (t0 + 11492);
t15 = (t14 + 0U);
t16 = (t15 + 0U);
*((int *)t16) = 0;
t16 = (t15 + 4U);
*((int *)t16) = 1;
t16 = (t15 + 8U);
*((int *)t16) = 1;
t17 = (1 - 0);
t18 = (t17 * 1);
t18 = (t18 + 1);
t16 = (t15 + 12U);
*((unsigned int *)t16) = t18;
t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
t1 = t19;
goto LAB7;
LAB9: goto LAB2;
}
static void work_a_0832606739_3212880686_p_9(char *t0)
{
char t5[16];
char *t1;
char *t2;
char *t3;
char *t6;
char *t7;
int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
LAB0: xsi_set_current_line(70, ng0);
t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 11368U);
t3 = (t0 + 11494);
t6 = (t5 + 0U);
t7 = (t6 + 0U);
*((int *)t7) = 0;
t7 = (t6 + 4U);
*((int *)t7) = 7;
t7 = (t6 + 8U);
*((int *)t7) = 1;
t8 = (7 - 0);
t9 = (t8 * 1);
t9 = (t9 + 1);
t7 = (t6 + 12U);
*((unsigned int *)t7) = t9;
t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
if (t10 != 0)
goto LAB3;
LAB4:
LAB5: t15 = (t0 + 7880);
t16 = (t15 + 56U);
t17 = *((char **)t16);
t18 = (t17 + 56U);
t19 = *((char **)t18);
*((unsigned char *)t19) = (unsigned char)2;
xsi_driver_first_trans_fast_port(t15);
LAB2: t20 = (t0 + 7208);
*((int *)t20) = 1;
LAB1: return;
LAB3: t7 = (t0 + 7880);
t11 = (t7 + 56U);
t12 = *((char **)t11);
t13 = (t12 + 56U);
t14 = *((char **)t13);
*((unsigned char *)t14) = (unsigned char)3;
xsi_driver_first_trans_fast_port(t7);
goto LAB2;
LAB6: goto LAB2;
}
static void work_a_0832606739_3212880686_p_10(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(72, ng0);
LAB3: t1 = (t0 + 3112U);
t2 = *((char **)t1);
t1 = (t0 + 7944);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 7224);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0832606739_3212880686_init()
{
static char *pe[] = {(void *)work_a_0832606739_3212880686_p_0,(void *)work_a_0832606739_3212880686_p_1,(void *)work_a_0832606739_3212880686_p_2,(void *)work_a_0832606739_3212880686_p_3,(void *)work_a_0832606739_3212880686_p_4,(void *)work_a_0832606739_3212880686_p_5,(void *)work_a_0832606739_3212880686_p_6,(void *)work_a_0832606739_3212880686_p_7,(void *)work_a_0832606739_3212880686_p_8,(void *)work_a_0832606739_3212880686_p_9,(void *)work_a_0832606739_3212880686_p_10};
xsi_register_didat("work_a_0832606739_3212880686", "isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat");
xsi_register_executes(pe);
}

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
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BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o
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132
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.c
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@ -1,132 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd";
static void work_a_2602956921_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 3304U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(100, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3112);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(103, ng0);
t2 = (t0 + 6215);
t5 = (t0 + 3688);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 8U);
xsi_driver_first_trans_fast(t5);
xsi_set_current_line(104, ng0);
t2 = (t0 + 6223);
t5 = (t0 + 3752);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 8U);
xsi_driver_first_trans_fast(t5);
xsi_set_current_line(105, ng0);
t3 = (4 * 1000LL);
t2 = (t0 + 6231);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(106, ng0);
t3 = (8 * 1000LL);
t2 = (t0 + 6234);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(107, ng0);
t3 = (12 * 1000LL);
t2 = (t0 + 6237);
t5 = (t0 + 3816);
t6 = (t5 + 56U);
t7 = *((char **)t6);
t8 = (t7 + 56U);
t9 = *((char **)t8);
memcpy(t9, t2, 3U);
xsi_driver_first_trans_delta(t5, 0U, 3U, t3);
t10 = (t0 + 3816);
xsi_driver_intertial_reject(t10, t3, t3);
xsi_set_current_line(108, ng0);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
extern void work_a_2602956921_2372691052_init()
{
static char *pe[] = {(void *)work_a_2602956921_2372691052_p_0};
xsi_register_didat("work_a_2602956921_2372691052", "isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.lin64.o
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49
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/alu_test_isim_beh.exe_main.c
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@ -1,49 +0,0 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
char *IEEE_P_3620187407;
char *IEEE_P_3499444699;
char *IEEE_P_1242562249;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_0832606739_3212880686_init();
work_a_2602956921_2372691052_init();
xsi_register_tops("work_a_2602956921_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
IEEE_P_1242562249 = xsi_get_engine_memory("ieee_p_1242562249");
return xsi_run_simulation(argc, argv);
}

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe Executable file
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0
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log
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29
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log Normal file
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@ -0,0 +1,29 @@
Command line:
bm_instr_test_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 58139
Thu Apr 15 10:54:21 2021
Elaboration Time: 0 sec
Current Memory Usage: 182.768 Meg
Total Signals : 7
Total Nets : 2065
Total Signal Drivers : 3
Total Blocks : 6
Total Primitive Blocks : 5
Total Processes : 3
Total Traceable Variables : 16
Total Scalar Nets and Variables : 2567
Total Line Count : 12
Total Simulation Time: 0.02 sec
Current Memory Usage: 258.269 Meg
Thu Apr 15 10:54:49 2021

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat Normal file
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106
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c Normal file
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@ -0,0 +1,106 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd";
extern char *IEEE_P_2592010699;
extern char *IEEE_P_1242562249;
int ieee_p_1242562249_sub_17802405650254020620_1035706684(char *, char *, char *);
unsigned char ieee_p_2592010699_sub_2763492388968962707_503743352(char *, char *, unsigned int , unsigned int );
static void work_a_1802466774_3212880686_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
unsigned char t4;
char *t5;
int t6;
int t7;
unsigned int t8;
unsigned int t9;
unsigned int t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: t1 = (t0 + 2664U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(40, ng0);
LAB6: t2 = (t0 + 2984);
*((int *)t2) = 1;
*((char **)t1) = &&LAB7;
LAB1: return;
LAB4: t5 = (t0 + 2984);
*((int *)t5) = 0;
xsi_set_current_line(41, ng0);
t2 = (t0 + 1512U);
t3 = *((char **)t2);
t2 = (t0 + 1032U);
t5 = *((char **)t2);
t2 = (t0 + 5232U);
t6 = ieee_p_1242562249_sub_17802405650254020620_1035706684(IEEE_P_1242562249, t5, t2);
t7 = (t6 - 0);
t8 = (t7 * 1);
xsi_vhdl_check_range_of_index(0, 255, 1, t6);
t9 = (8U * t8);
t10 = (0 + t9);
t11 = (t3 + t10);
t12 = (t0 + 3064);
t13 = (t12 + 56U);
t14 = *((char **)t13);
t15 = (t14 + 56U);
t16 = *((char **)t15);
memcpy(t16, t11, 8U);
xsi_driver_first_trans_fast_port(t12);
goto LAB2;
LAB5: t3 = (t0 + 1312U);
t4 = ieee_p_2592010699_sub_2763492388968962707_503743352(IEEE_P_2592010699, t3, 0U, 0U);
if (t4 == 1)
goto LAB4;
else
goto LAB6;
LAB7: goto LAB5;
}
extern void work_a_1802466774_3212880686_init()
{
static char *pe[] = {(void *)work_a_1802466774_3212880686_p_0};
xsi_register_didat("work_a_1802466774_3212880686", "isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat");
xsi_register_executes(pe);
}

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xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o Normal file
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192
xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c Normal file
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@ -0,0 +1,192 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd";
static void work_a_4060154216_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2624U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(73, ng0);
t2 = (t0 + 3256);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(74, ng0);
t2 = (t0 + 1648U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(75, ng0);
t2 = (t0 + 3256);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(76, ng0);
t2 = (t0 + 1648U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2432);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_4060154216_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
LAB0: t1 = (t0 + 2872U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(84, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(86, ng0);
t2 = (t0 + 1648U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2680);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(88, ng0);
t2 = (t0 + 5544);
t6 = (t0 + 3320);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(89, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2680);
xsi_process_wait(t2, t3);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(91, ng0);
t2 = (t0 + 5552);
t6 = (t0 + 3320);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t2, 8U);
xsi_driver_first_trans_fast(t6);
xsi_set_current_line(94, ng0);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: goto LAB2;
LAB17: goto LAB16;
LAB19: goto LAB17;
}
extern void work_a_4060154216_2372691052_init()
{
static char *pe[] = {(void *)work_a_4060154216_2372691052_p_0,(void *)work_a_4060154216_2372691052_p_1};
xsi_register_didat("work_a_4060154216_2372691052", "isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat");
xsi_register_executes(pe);
}

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5
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.c → xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c
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@ -31,10 +31,11 @@ int main(int argc, char **argv)
ieee_p_3499444699_init();
ieee_p_3620187407_init();
ieee_p_1242562249_init();
work_a_2725559894_3212880686_init();
work_a_1802466774_3212880686_init();
work_a_4060154216_2372691052_init();
xsi_register_tops("work_a_2725559894_3212880686");
xsi_register_tops("work_a_4060154216_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);

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10
xilinx/ALU/isim/isim_usage_statistics.html
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@ -2,14 +2,14 @@
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>920 ms, 1722952 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>840 ms, 936380 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>22</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>91</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>7</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>2065</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>12</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.19 sec, 256135 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.02 sec, 257216 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>

0
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimcrash.log → xilinx/ALU/isim/lockfile2
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2
xilinx/ALU/pepExtractor.prj
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@ -1 +1 @@
work "alu.vhd"
work "bm_instr.vhd"