Browse Source

BR OK + BM OK + Tests et pipeline à faire

Foussats Morgane 7 months ago
parent
commit
344eba4dde
69 changed files with 764 additions and 2245 deletions
  1. 35
    22
      xilinx/ALU/ALU.gise
  2. 25
    44
      xilinx/ALU/ALU.xise
  3. 1
    4
      xilinx/ALU/_xmsgs/pn_parser.xmsgs
  4. 3
    3
      xilinx/ALU/alu_summary.html
  5. 0
    2
      xilinx/ALU/alu_test_beh.prj
  6. BIN
      xilinx/ALU/alu_test_isim_beh.wdb
  7. 55
    0
      xilinx/ALU/bm.vhd
  8. 44
    0
      xilinx/ALU/bm_instr.vhd
  9. 97
    0
      xilinx/ALU/bm_instr_test.vhd
  10. 2
    0
      xilinx/ALU/bm_instr_test_beh.prj
  11. BIN
      xilinx/ALU/bm_instr_test_isim_beh.exe
  12. BIN
      xilinx/ALU/bm_instr_test_isim_beh.wdb
  13. 8
    9
      xilinx/ALU/br.vhd
  14. 126
    0
      xilinx/ALU/br_test.vhd
  15. BIN
      xilinx/ALU/br_test_isim_beh.exe
  16. BIN
      xilinx/ALU/br_test_isim_beh1.wdb
  17. BIN
      xilinx/ALU/br_test_isim_beh2.wdb
  18. 12
    12
      xilinx/ALU/fuse.log
  19. 1
    1
      xilinx/ALU/fuseRelaunch.cmd
  20. 16
    17
      xilinx/ALU/iseconfig/ALU.projectmgr
  21. 2
    2
      xilinx/ALU/iseconfig/alu.xreport
  22. 1
    20
      xilinx/ALU/isim.log
  23. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg
  24. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe
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      xilinx/ALU/isim/alu_isim_beh.exe.sim/isimkernel.log
  26. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/netId1.dat
  27. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/tmp_save/_1
  28. 0
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      xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.c
  29. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat
  30. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.lin64.o
  31. BIN
      xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.lin64.o
  32. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  33. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/alu_test_isim_beh.exe
  34. 0
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimkernel.log
  35. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/netId.dat
  36. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/tmp_save/_1
  37. 0
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c
  38. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.didat
  39. BIN
      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.lin64.o
  40. 0
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.c
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.didat
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_2602956921_2372691052.lin64.o
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/alu_test_isim_beh.exe_main.c
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      xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/alu_test_isim_beh.exe_main.lin64.o
  45. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
  46. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/bm_instr_test_isim_beh.exe
  47. 0
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      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimcrash.log
  48. 29
    0
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/isimkernel.log
  49. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/netId.dat
  50. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/tmp_save/_1
  51. 106
    0
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.c
  52. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.didat
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      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_1802466774_3212880686.lin64.o
  54. 192
    0
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.c
  55. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.didat
  56. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/a_4060154216_2372691052.lin64.o
  57. 3
    2
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.c
  58. BIN
      xilinx/ALU/isim/bm_instr_test_isim_beh.exe.sim/work/bm_instr_test_isim_beh.exe_main.lin64.o
  59. 5
    5
      xilinx/ALU/isim/isim_usage_statistics.html
  60. 0
    0
      xilinx/ALU/isim/lockfile2
  61. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_1242562249.didat
  62. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_2592010699.didat
  63. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3499444699.didat
  64. BIN
      xilinx/ALU/isim/precompiled.exe.sim/ieee/p_3620187407.didat
  65. BIN
      xilinx/ALU/isim/work/alu.vdb
  66. BIN
      xilinx/ALU/isim/work/alu_test.vdb
  67. BIN
      xilinx/ALU/isim/work/bm_instr.vdb
  68. BIN
      xilinx/ALU/isim/work/bm_instr_test.vdb
  69. 1
    1
      xilinx/ALU/pepExtractor.prj

+ 35
- 22
xilinx/ALU/ALU.gise View File

@@ -23,13 +23,14 @@
23 23
 
24 24
   <files xmlns="http://www.xilinx.com/XMLSchema">
25 25
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_isim_beh.exe"/>
26
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="alu_test_beh.prj"/>
27 26
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="alu_test_isim_beh.exe"/>
28
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="alu_test_isim_beh.wdb"/>
27
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="bm_instr_test_beh.prj"/>
28
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="bm_instr_test_isim_beh.exe"/>
29
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="bm_instr_test_isim_beh.wdb"/>
30
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="br_test_isim_beh.exe"/>
29 31
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
30 32
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
31 33
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
32
-    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
33 34
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
34 35
   </files>
35 36
 
@@ -40,23 +41,28 @@
40 41
     </transform>
41 42
     <transform xil_pn:end_ts="1618303356" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1618303356">
42 43
       <status xil_pn:value="SuccessfullyRun"/>
44
+      <status xil_pn:value="ReadyToRun"/>
43 45
     </transform>
44
-    <transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618304610">
46
+    <transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1618476857">
45 47
       <status xil_pn:value="SuccessfullyRun"/>
46 48
       <status xil_pn:value="ReadyToRun"/>
47 49
       <status xil_pn:value="OutOfDateForInputs"/>
48 50
       <status xil_pn:value="OutOfDateForOutputs"/>
49
-      <status xil_pn:value="InputAdded"/>
50 51
       <status xil_pn:value="InputChanged"/>
51
-      <status xil_pn:value="InputRemoved"/>
52 52
       <status xil_pn:value="OutputChanged"/>
53
-      <status xil_pn:value="OutputRemoved"/>
53
+      <outfile xil_pn:name="alu.vhd"/>
54
+      <outfile xil_pn:name="alu_test.vhd"/>
55
+      <outfile xil_pn:name="bm.vhd"/>
56
+      <outfile xil_pn:name="bm_instr.vhd"/>
57
+      <outfile xil_pn:name="bm_instr_test.vhd"/>
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+      <outfile xil_pn:name="br.vhd"/>
59
+      <outfile xil_pn:name="br_test.vhd"/>
54 60
     </transform>
55
-    <transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-6587339501330506153" xil_pn:start_ts="1618304817">
61
+    <transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3025547276878941811" xil_pn:start_ts="1618476689">
56 62
       <status xil_pn:value="SuccessfullyRun"/>
57 63
       <status xil_pn:value="ReadyToRun"/>
58 64
     </transform>
59
-    <transform xil_pn:end_ts="1618304817" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1575583835443101483" xil_pn:start_ts="1618304817">
65
+    <transform xil_pn:end_ts="1618476689" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-323741304737568527" xil_pn:start_ts="1618476689">
60 66
       <status xil_pn:value="SuccessfullyRun"/>
61 67
       <status xil_pn:value="ReadyToRun"/>
62 68
     </transform>
@@ -64,37 +70,44 @@
64 70
       <status xil_pn:value="SuccessfullyRun"/>
65 71
       <status xil_pn:value="ReadyToRun"/>
66 72
     </transform>
67
-    <transform xil_pn:end_ts="1618304610" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618304610">
73
+    <transform xil_pn:end_ts="1618476857" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1618476857">
68 74
       <status xil_pn:value="SuccessfullyRun"/>
69 75
       <status xil_pn:value="ReadyToRun"/>
70 76
       <status xil_pn:value="OutOfDateForInputs"/>
71 77
       <status xil_pn:value="OutOfDateForPredecessor"/>
72 78
       <status xil_pn:value="OutOfDateForOutputs"/>
73 79
       <status xil_pn:value="InputChanged"/>
74
-      <status xil_pn:value="InputRemoved"/>
75 80
       <status xil_pn:value="OutputChanged"/>
76
-      <status xil_pn:value="OutputRemoved"/>
81
+      <outfile xil_pn:name="alu.vhd"/>
82
+      <outfile xil_pn:name="alu_test.vhd"/>
83
+      <outfile xil_pn:name="bm.vhd"/>
84
+      <outfile xil_pn:name="bm_instr.vhd"/>
85
+      <outfile xil_pn:name="bm_instr_test.vhd"/>
86
+      <outfile xil_pn:name="br.vhd"/>
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+      <outfile xil_pn:name="br_test.vhd"/>
77 88
     </transform>
78
-    <transform xil_pn:end_ts="1618304818" xil_pn:in_ck="6733460428079175395" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="5625932807789681934" xil_pn:start_ts="1618304817">
89
+    <transform xil_pn:end_ts="1618476859" xil_pn:in_ck="3141714567836065316" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6397320030221382938" xil_pn:start_ts="1618476857">
79 90
       <status xil_pn:value="SuccessfullyRun"/>
80
-      <status xil_pn:value="NotReadyToRun"/>
91
+      <status xil_pn:value="ReadyToRun"/>
81 92
       <status xil_pn:value="OutOfDateForInputs"/>
93
+      <status xil_pn:value="OutOfDateForProperties"/>
82 94
       <status xil_pn:value="OutOfDateForPredecessor"/>
83
-      <status xil_pn:value="OutOfDateForOutputs"/>
84 95
       <status xil_pn:value="InputChanged"/>
85
-      <status xil_pn:value="InputRemoved"/>
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-      <status xil_pn:value="OutputChanged"/>
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-      <status xil_pn:value="OutputRemoved"/>
96
+      <outfile xil_pn:name="bm_instr_test_beh.prj"/>
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+      <outfile xil_pn:name="bm_instr_test_isim_beh.exe"/>
98
+      <outfile xil_pn:name="fuse.log"/>
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+      <outfile xil_pn:name="isim"/>
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+      <outfile xil_pn:name="xilinxsim.ini"/>
88 101
     </transform>
89
-    <transform xil_pn:end_ts="1618304818" xil_pn:in_ck="-4068278894953614943" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="5179862647015444475" xil_pn:start_ts="1618304818">
102
+    <transform xil_pn:end_ts="1618476860" xil_pn:in_ck="-6291911114616255345" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-7763494978879218253" xil_pn:start_ts="1618476859">
90 103
       <status xil_pn:value="SuccessfullyRun"/>
91 104
       <status xil_pn:value="ReadyToRun"/>
92
-      <status xil_pn:value="OutOfDateForInputs"/>
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+      <status xil_pn:value="OutOfDateForProperties"/>
93 106
       <status xil_pn:value="OutOfDateForPredecessor"/>
94 107
       <status xil_pn:value="OutOfDateForOutputs"/>
95
-      <status xil_pn:value="InputRemoved"/>
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       <status xil_pn:value="OutputChanged"/>
97
-      <status xil_pn:value="OutputRemoved"/>
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+      <outfile xil_pn:name="bm_instr_test_isim_beh.wdb"/>
110
+      <outfile xil_pn:name="isim.cmd"/>
98 111
     </transform>
99 112
   </transforms>
100 113
 

+ 25
- 44
xilinx/ALU/ALU.xise View File

@@ -16,26 +16,44 @@
16 16
 
17 17
   <files>
18 18
     <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
19
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
19
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
20 20
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
21 21
     </file>
22 22
     <file xil_pn:name="alu_test.vhd" xil_pn:type="FILE_VHDL">
23
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
23
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
24 24
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
25 25
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
26 26
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
27 27
     </file>
28 28
     <file xil_pn:name="br.vhd" xil_pn:type="FILE_VHDL">
29
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
29
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
30
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
31
+    </file>
32
+    <file xil_pn:name="br_test.vhd" xil_pn:type="FILE_VHDL">
33
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
34
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="13"/>
35
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="13"/>
36
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
37
+    </file>
38
+    <file xil_pn:name="bm.vhd" xil_pn:type="FILE_VHDL">
39
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
30 40
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
31 41
     </file>
42
+    <file xil_pn:name="bm_instr.vhd" xil_pn:type="FILE_VHDL">
43
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
44
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
45
+    </file>
46
+    <file xil_pn:name="bm_instr_test.vhd" xil_pn:type="FILE_VHDL">
47
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
48
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
49
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
50
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
51
+    </file>
32 52
   </files>
33 53
 
34 54
   <properties>
35 55
     <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
36
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
37 56
     <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
38
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
39 57
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
40 58
     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
41 59
     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -49,8 +67,6 @@
49 67
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
50 68
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
51 69
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
52
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
53
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
54 70
     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
55 71
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
56 72
     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -67,56 +83,45 @@
67 83
     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
68 84
     <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
69 85
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
70
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
71 86
     <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
72 87
     <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
73 88
     <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
74 89
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
75 90
     <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
76
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
77 91
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
78 92
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
79 93
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
80 94
     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
81 95
     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
82
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
83 96
     <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
84 97
     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
85 98
     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
86 99
     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
87 100
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
88
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
89
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
90 101
     <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
91 102
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
92 103
     <property xil_pn:name="Device" xil_pn:value="xc6slx16" xil_pn:valueState="non-default"/>
93 104
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
94 105
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
95 106
     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
96
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
97 107
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
98 108
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
99 109
     <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
100 110
     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
101 111
     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
102
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
103 112
     <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
104 113
     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
105
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
106 114
     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
107 115
     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
108
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
116
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
109 117
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
110 118
     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
111 119
     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
112 120
     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
113
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
114 121
     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
115 122
     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
116 123
     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
117
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
118 124
     <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
119
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
120 125
     <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
121 126
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
122 127
     <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -124,12 +129,10 @@
124 129
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
125 130
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
126 131
     <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
127
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
128 132
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
129 133
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
130 134
     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
131 135
     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
132
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
133 136
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
134 137
     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
135 138
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
@@ -156,12 +159,9 @@
156 159
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
157 160
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
158 161
     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
159
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
160 162
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
161 163
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
162
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
163 164
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
164
-    <property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/>
165 165
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
166 166
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
167 167
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -179,7 +179,6 @@
179 179
     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
180 180
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
181 181
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
182
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
183 182
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
184 183
     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
185 184
     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -200,7 +199,6 @@
200 199
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
201 200
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
202 201
     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
203
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
204 202
     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
205 203
     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
206 204
     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
@@ -212,7 +210,6 @@
212 210
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
213 211
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
214 212
     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
215
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
216 213
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
217 214
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
218 215
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -243,7 +240,6 @@
243 240
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
244 241
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
245 242
     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
246
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
247 243
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
248 244
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
249 245
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
@@ -251,9 +247,7 @@
251 247
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="alu_timesim.vhd" xil_pn:valueState="default"/>
252 248
     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="alu_synthesis.vhd" xil_pn:valueState="default"/>
253 249
     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="alu_translate.vhd" xil_pn:valueState="default"/>
254
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
255 250
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
256
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
257 251
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
258 252
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
259 253
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@@ -271,7 +265,6 @@
271 265
     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
272 266
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
273 267
     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
274
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
275 268
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
276 269
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
277 270
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@@ -296,7 +289,6 @@
296 289
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
297 290
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
298 291
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
299
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
300 292
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
301 293
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
302 294
     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/alu_test" xil_pn:valueState="non-default"/>
@@ -305,12 +297,10 @@
305 297
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
306 298
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
307 299
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
308
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
309 300
     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
310 301
     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
311 302
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
312 303
     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
313
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
314 304
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
315 305
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
316 306
     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -325,8 +315,6 @@
325 315
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
326 316
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
327 317
     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
328
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
329
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
330 318
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
331 319
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
332 320
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
@@ -351,35 +339,28 @@
351 339
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
352 340
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
353 341
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
354
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
355 342
     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
356 343
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
357 344
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
358
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
359 345
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
360 346
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
361 347
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
362 348
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
363
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
364 349
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
365 350
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
366 351
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
367 352
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
368 353
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
369 354
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
370
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
371 355
     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
372
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
373 356
     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
374
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
375
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
376 357
     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
377 358
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
378 359
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
379 360
     <!--                                                                                  -->
380 361
     <!-- The following properties are for internal use only. These should not be modified.-->
381 362
     <!--                                                                                  -->
382
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|alu_test|behavior" xil_pn:valueState="non-default"/>
363
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|bm_instr_test|behavior" xil_pn:valueState="non-default"/>
383 364
     <property xil_pn:name="PROP_DesignName" xil_pn:value="ALU" xil_pn:valueState="non-default"/>
384 365
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
385 366
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

+ 1
- 4
xilinx/ALU/_xmsgs/pn_parser.xmsgs View File

@@ -8,10 +8,7 @@
8 8
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
9 9
 
10 10
 <messages>
11
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd&quot; into library work</arg>
12
-</msg>
13
-
14
-<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br.vhd</arg>&quot; Line <arg fmt="%d" index="2">47</arg>. <arg fmt="%s" index="3">Syntax error near &quot;CLK&quot;.</arg>
11
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd&quot; into library work</arg>
15 12
 </msg>
16 13
 
17 14
 </messages>

+ 3
- 3
xilinx/ALU/alu_summary.html View File

@@ -7,7 +7,7 @@
7 7
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8 8
 <TD>ALU.xise</TD>
9 9
 <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10
-<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
10
+<TD> No Errors </TD>
11 11
 </TR>
12 12
 <TR ALIGN=LEFT>
13 13
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
@@ -72,9 +72,9 @@
72 72
 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
73 73
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
74 74
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
75
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>mar. avr. 13 11:14:16 2021</TD></TR>
75
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>jeu. avr. 15 10:54:50 2021</TD></TR>
76 76
 </TABLE>
77 77
 
78 78
 
79
-<br><center><b>Date Generated:</b> 04/13/2021 - 11:53:22</center>
79
+<br><center><b>Date Generated:</b> 04/15/2021 - 10:56:37</center>
80 80
 </BODY></HTML>

+ 0
- 2
xilinx/ALU/alu_test_beh.prj View File

@@ -1,2 +0,0 @@
1
-vhdl work "alu.vhd"
2
-vhdl work "alu_test.vhd"

BIN
xilinx/ALU/alu_test_isim_beh.wdb View File


+ 55
- 0
xilinx/ALU/bm.vhd View File

@@ -0,0 +1,55 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date:    10:32:11 04/15/2021 
6
+-- Design Name: 
7
+-- Module Name:    bm_data - Behavioral 
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool versions: 
11
+-- Description: 
12
+--
13
+-- Dependencies: 
14
+--
15
+-- Revision: 
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments: 
18
+--
19
+----------------------------------------------------------------------------------
20
+library IEEE;
21
+use IEEE.STD_LOGIC_1164.ALL;
22
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
23
+use IEEE.NUMERIC_STD.ALL;
24
+
25
+entity bm_data is
26
+    Port ( IN_addr : in  STD_LOGIC_VECTOR (7 downto 0);
27
+           IN_data : in  STD_LOGIC_VECTOR (7 downto 0);
28
+           RW : in  STD_LOGIC;
29
+           RST : in  STD_LOGIC;
30
+           CLK : in  STD_LOGIC;
31
+           OUT_data : out  STD_LOGIC_VECTOR (7 downto 0));
32
+end bm_data;
33
+
34
+architecture Behavioral of bm_data is
35
+
36
+type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
37
+signal data_memory: mem;
38
+
39
+begin
40
+	process
41
+		begin
42
+			wait until rising_edge(CLK);
43
+			if RW = '1' then
44
+				OUT_data <= data_memory(to_integer(unsigned(IN_addr)));
45
+			else
46
+				data_memory(to_integer(unsigned(IN_addr))) <= IN_data;
47
+			end if;
48
+			if RST='0' then 
49
+				registres <= (others => "00000000");
50
+			end if;	
51
+	end process;
52
+
53
+
54
+end Behavioral;
55
+

+ 44
- 0
xilinx/ALU/bm_instr.vhd View File

@@ -0,0 +1,44 @@
1
+----------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer: 
4
+-- 
5
+-- Create Date:    10:40:07 04/15/2021 
6
+-- Design Name: 
7
+-- Module Name:    bm_instr - Behavioral 
8
+-- Project Name: 
9
+-- Target Devices: 
10
+-- Tool versions: 
11
+-- Description: 
12
+--
13
+-- Dependencies: 
14
+--
15
+-- Revision: 
16
+-- Revision 0.01 - File Created
17
+-- Additional Comments: 
18
+--
19
+----------------------------------------------------------------------------------
20
+library IEEE;
21
+use IEEE.STD_LOGIC_1164.ALL;
22
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
23
+use IEEE.NUMERIC_STD.ALL;
24
+
25
+
26
+entity bm_instr is
27
+    Port ( IN_addr : in  STD_LOGIC_VECTOR (7 downto 0);
28
+           OUT_data : out  STD_LOGIC_VECTOR (7 downto 0);
29
+           CLK : in  STD_LOGIC);
30
+end bm_instr;
31
+
32
+architecture Behavioral of bm_instr is
33
+
34
+type mem is array (0 to 255) of STD_LOGIC_VECTOR(7 downto 0);
35
+signal instr_memory: mem := (1 => "00000001", others =>"00000000");
36
+
37
+begin
38
+
39
+		OUT_data <= instr_memory(to_integer(unsigned(IN_addr)));
40
+
41
+
42
+
43
+end Behavioral;
44
+

+ 97
- 0
xilinx/ALU/bm_instr_test.vhd View File

@@ -0,0 +1,97 @@
1
+--------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer:
4
+--
5
+-- Create Date:   10:42:17 04/15/2021
6
+-- Design Name:   
7
+-- Module Name:   /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd
8
+-- Project Name:  ALU
9
+-- Target Device:  
10
+-- Tool versions:  
11
+-- Description:   
12
+-- 
13
+-- VHDL Test Bench Created by ISE for module: bm_instr
14
+-- 
15
+-- Dependencies:
16
+-- 
17
+-- Revision:
18
+-- Revision 0.01 - File Created
19
+-- Additional Comments:
20
+--
21
+-- Notes: 
22
+-- This testbench has been automatically generated using types std_logic and
23
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
+-- that these types always be used for the top-level I/O of a design in order
25
+-- to guarantee that the testbench will bind correctly to the post-implementation 
26
+-- simulation model.
27
+--------------------------------------------------------------------------------
28
+LIBRARY ieee;
29
+USE ieee.std_logic_1164.ALL;
30
+ 
31
+-- Uncomment the following library declaration if using
32
+-- arithmetic functions with Signed or Unsigned values
33
+--USE ieee.numeric_std.ALL;
34
+ 
35
+ENTITY bm_instr_test IS
36
+END bm_instr_test;
37
+ 
38
+ARCHITECTURE behavior OF bm_instr_test IS 
39
+ 
40
+    -- Component Declaration for the Unit Under Test (UUT)
41
+ 
42
+    COMPONENT bm_instr
43
+    PORT(
44
+         IN_addr : IN  std_logic_vector(7 downto 0);
45
+         OUT_data : OUT  std_logic_vector(7 downto 0);
46
+         CLK : IN  std_logic
47
+        );
48
+    END COMPONENT;
49
+    
50
+
51
+   --Inputs
52
+   signal IN_addr : std_logic_vector(7 downto 0) := (others => '0');
53
+   signal CLK : std_logic := '0';
54
+
55
+ 	--Outputs
56
+   signal OUT_data : std_logic_vector(7 downto 0);
57
+
58
+   -- Clock period definitions
59
+   constant CLK_period : time := 10 ns;
60
+ 
61
+BEGIN
62
+ 
63
+	-- Instantiate the Unit Under Test (UUT)
64
+   uut: bm_instr PORT MAP (
65
+          IN_addr => IN_addr,
66
+          OUT_data => OUT_data,
67
+          CLK => CLK
68
+        );
69
+
70
+   -- Clock process definitions
71
+   CLK_process :process
72
+   begin
73
+		CLK <= '0';
74
+		wait for CLK_period/2;
75
+		CLK <= '1';
76
+		wait for CLK_period/2;
77
+   end process;
78
+ 
79
+
80
+   -- Stimulus process
81
+   stim_proc: process
82
+   begin		
83
+      -- hold reset state for 100 ns.
84
+      wait for 100 ns;	
85
+
86
+      wait for CLK_period*10;
87
+
88
+      IN_addr <= "00000001";
89
+		wait for 100 ns;
90
+		
91
+		IN_addr <= "00001001";
92
+		
93
+
94
+      wait;
95
+   end process;
96
+
97
+END;

+ 2
- 0
xilinx/ALU/bm_instr_test_beh.prj View File

@@ -0,0 +1,2 @@
1
+vhdl work "bm_instr.vhd"
2
+vhdl work "bm_instr_test.vhd"

BIN
xilinx/ALU/bm_instr_test_isim_beh.exe View File


BIN
xilinx/ALU/bm_instr_test_isim_beh.wdb View File


+ 8
- 9
xilinx/ALU/br.vhd View File

@@ -44,18 +44,17 @@ signal registres: reg;
44 44
 begin
45 45
 	process
46 46
 		begin
47
-			wait until CLK'event CLK = '1';
47
+			wait until rising_edge(CLK);
48 48
 			if W = '1' then
49
-				registres(W_addr) <= Data;
50
-			else
51
-				
49
+				registres(to_integer(unsigned(W_addr))) <= Data;
52 50
 			end if;
53 51
 			if RST='0' then 
54
-				QA <= "00000000";
55
-				QB <= "00000000";
56
-			end if;
57
-			
52
+				registres <= (others => "00000000");
53
+			end if;	
58 54
 	end process;
59
-
55
+	QA <= registres(to_integer(unsigned(A_addr))) when W ='0' or A_addr /= W_addr
56
+			else Data;
57
+	QB <= registres(to_integer(unsigned(B_addr))) when W ='0' or B_addr /= W_addr
58
+			else Data;
60 59
 end Behavioral;
61 60
 

+ 126
- 0
xilinx/ALU/br_test.vhd View File

@@ -0,0 +1,126 @@
1
+--------------------------------------------------------------------------------
2
+-- Company: 
3
+-- Engineer:
4
+--
5
+-- Create Date:   09:35:26 04/15/2021
6
+-- Design Name:   
7
+-- Module Name:   /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/br_test.vhd
8
+-- Project Name:  ALU
9
+-- Target Device:  
10
+-- Tool versions:  
11
+-- Description:   
12
+-- 
13
+-- VHDL Test Bench Created by ISE for module: br
14
+-- 
15
+-- Dependencies:
16
+-- 
17
+-- Revision:
18
+-- Revision 0.01 - File Created
19
+-- Additional Comments:
20
+--
21
+-- Notes: 
22
+-- This testbench has been automatically generated using types std_logic and
23
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
+-- that these types always be used for the top-level I/O of a design in order
25
+-- to guarantee that the testbench will bind correctly to the post-implementation 
26
+-- simulation model.
27
+--------------------------------------------------------------------------------
28
+LIBRARY ieee;
29
+USE ieee.std_logic_1164.ALL;
30
+ 
31
+-- Uncomment the following library declaration if using
32
+-- arithmetic functions with Signed or Unsigned values
33
+--USE ieee.numeric_std.ALL;
34
+ 
35
+ENTITY br_test IS
36
+END br_test;
37
+ 
38
+ARCHITECTURE behavior OF br_test IS 
39
+ 
40
+    -- Component Declaration for the Unit Under Test (UUT)
41
+ 
42
+    COMPONENT br
43
+    PORT(
44
+         A_addr : IN  std_logic_vector(3 downto 0);
45
+         B_addr : IN  std_logic_vector(3 downto 0);
46
+         W_addr : IN  std_logic_vector(3 downto 0);
47
+         W : IN  std_logic;
48
+         Data : IN  std_logic_vector(7 downto 0);
49
+         RST : IN  std_logic;
50
+         CLK : IN  std_logic;
51
+         QA : OUT  std_logic_vector(7 downto 0);
52
+         QB : OUT  std_logic_vector(7 downto 0)
53
+        );
54
+    END COMPONENT;
55
+    
56
+
57
+   --Inputs
58
+   signal A_addr : std_logic_vector(3 downto 0) := (others => '0');
59
+   signal B_addr : std_logic_vector(3 downto 0) := (others => '0');
60
+   signal W_addr : std_logic_vector(3 downto 0) := (others => '0');
61
+   signal W : std_logic := '0';
62
+   signal Data : std_logic_vector(7 downto 0) := (others => '0');
63
+   signal RST : std_logic := '0';
64
+   signal CLK : std_logic := '0';
65
+
66
+ 	--Outputs
67
+   signal QA : std_logic_vector(7 downto 0);
68
+   signal QB : std_logic_vector(7 downto 0);
69
+
70
+   -- Clock period definitions
71
+   constant CLK_period : time := 10 ns;
72
+ 
73
+BEGIN
74
+ 
75
+	-- Instantiate the Unit Under Test (UUT)
76
+   uut: br PORT MAP (
77
+          A_addr => A_addr,
78
+          B_addr => B_addr,
79
+          W_addr => W_addr,
80
+          W => W,
81
+          Data => Data,
82
+          RST => RST,
83
+          CLK => CLK,
84
+          QA => QA,
85
+          QB => QB
86
+        );
87
+
88
+   -- Clock process definitions
89
+   CLK_process :process
90
+   begin
91
+		CLK <= '0';
92
+		wait for CLK_period/2;
93
+		CLK <= '1';
94
+		wait for CLK_period/2;
95
+   end process;
96
+ 
97
+
98
+   -- Stimulus process
99
+   stim_proc: process
100
+   begin		
101
+      -- hold reset state for 100 ns.
102
+      wait for 100 ns;	
103
+
104
+      wait for CLK_period*10;
105
+
106
+      RST <= '1';
107
+		wait for 100 ns ;
108
+		DATA <= "10000000";
109
+		wait for 100 ns ;
110
+		W_addr <= "0000";
111
+		wait for 100 ns ;
112
+		W <= '1';
113
+		wait for 100 ns ;
114
+		
115
+		W <= '0';
116
+		wait for 100 ns ;
117
+		
118
+		A_addr <= "0000" ;
119
+		B_addr <= "0001" ;
120
+		
121
+		
122
+
123
+      wait;
124
+   end process;
125
+
126
+END;

BIN
xilinx/ALU/br_test_isim_beh.exe View File


BIN
xilinx/ALU/br_test_isim_beh1.wdb View File


BIN
xilinx/ALU/br_test_isim_beh2.wdb View File


+ 12
- 12
xilinx/ALU/fuse.log View File

@@ -1,25 +1,25 @@
1
-Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test" 
1
+Running: /usr/local/insa/Xilinx.ISE/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -prj /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj work.bm_instr_test 
2 2
 ISim O.87xd (signature 0x8ddf5b5d)
3
-Number of CPUs detected in this system: 12
4
-Turning on mult-threading, number of parallel sub-compilation jobs: 24 
3
+Number of CPUs detected in this system: 6
4
+Turning on mult-threading, number of parallel sub-compilation jobs: 12 
5 5
 Determining compilation order of HDL files
6
-Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd" into library work
7
-Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd" into library work
6
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd" into library work
7
+Parsing VHDL file "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test.vhd" into library work
8 8
 Starting static elaboration
9 9
 Completed static elaboration
10 10
 Fuse Memory Usage: 98500 KB
11
-Fuse CPU Usage: 810 ms
11
+Fuse CPU Usage: 750 ms
12 12
 Compiling package standard
13 13
 Compiling package std_logic_1164
14 14
 Compiling package std_logic_arith
15 15
 Compiling package std_logic_unsigned
16 16
 Compiling package numeric_std
17
-Compiling architecture behavioral of entity alu [alu_default]
18
-Compiling architecture behavior of entity alu_test
17
+Compiling architecture behavioral of entity bm_instr [bm_instr_default]
18
+Compiling architecture behavior of entity bm_instr_test
19 19
 Time Resolution for simulation is 1ps.
20 20
 Waiting for 1 sub-compilation(s) to finish...
21 21
 Compiled 8 VHDL Units
22
-Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe
23
-Fuse Memory Usage: 1722952 KB
24
-Fuse CPU Usage: 920 ms
25
-GCC CPU Usage: 80 ms
22
+Built simulation executable /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe
23
+Fuse Memory Usage: 936380 KB
24
+Fuse CPU Usage: 840 ms
25
+GCC CPU Usage: 1640 ms

+ 1
- 1
xilinx/ALU/fuseRelaunch.cmd View File

@@ -1 +1 @@
1
--intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_beh.prj" "work.alu_test" 
1
+-intstyle "ise" -incremental -lib "secureip" -o "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe" -prj "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_beh.prj" "work.bm_instr_test" 

+ 16
- 17
xilinx/ALU/iseconfig/ALU.projectmgr View File

@@ -1,4 +1,4 @@
1
-<?xml version="1.0" encoding="utf-8"?>
1
+<?xml version='1.0' encoding='utf-8'?>
2 2
 <!--This is an ISE project configuration file.-->
3 3
 <!--It holds project specific layout data for the projectmgr plugin.-->
4 4
 <!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
@@ -9,13 +9,13 @@
9 9
          <ClosedNodesVersion>2</ClosedNodesVersion>
10 10
       </ClosedNodes>
11 11
       <SelectedItems>
12
-         <SelectedItem>ALU</SelectedItem>
12
+         <SelectedItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</SelectedItem>
13 13
       </SelectedItems>
14 14
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15 15
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000104000000020000000000000000000000000200000064ffffffff000000810000000300000002000001040000000100000003000000000000000100000003</ViewHeaderState>
16
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000145000000020000000000000000000000000200000064ffffffff000000810000000300000002000001450000000100000003000000000000000100000003</ViewHeaderState>
17 17
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18
-      <CurrentItem>ALU</CurrentItem>
18
+      <CurrentItem>bm_instr - Behavioral (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr.vhd)</CurrentItem>
19 19
    </ItemView>
20 20
    <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21 21
       <ClosedNodes>
@@ -23,13 +23,13 @@
23 23
          <ClosedNode>Design Utilities</ClosedNode>
24 24
       </ClosedNodes>
25 25
       <SelectedItems>
26
-         <SelectedItem></SelectedItem>
26
+         <SelectedItem/>
27 27
       </SelectedItems>
28 28
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
29 29
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
30
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
30
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
31 31
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
32
-      <CurrentItem></CurrentItem>
32
+      <CurrentItem/>
33 33
    </ItemView>
34 34
    <ItemView guiview="File" >
35 35
       <ClosedNodes>
@@ -40,7 +40,7 @@
40 40
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
41 41
       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004f0000000100000000000000390000000100000000000000830000000100000000000002960000000100000000</ViewHeaderState>
42 42
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
43
-      <CurrentItem></CurrentItem>
43
+      <CurrentItem>alu.vhd</CurrentItem>
44 44
    </ItemView>
45 45
    <ItemView guiview="Library" >
46 46
       <ClosedNodes>
@@ -50,7 +50,7 @@
50 50
       <SelectedItems/>
51 51
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
52 52
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
53
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003a1000000010001000100000000000000000000000064ffffffff000000810000000000000001000003a10000000100000000</ViewHeaderState>
53
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000148000000010001000100000000000000000000000064ffffffff000000810000000000000001000001480000000100000000</ViewHeaderState>
54 54
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
55 55
       <CurrentItem>work</CurrentItem>
56 56
    </ItemView>
@@ -68,21 +68,20 @@
68 68
       </SelectedItems>
69 69
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
70 70
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
71
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
71
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
72 72
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
73 73
       <CurrentItem></CurrentItem>
74 74
    </ItemView>
75 75
    <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
76 76
       <ClosedNodes>
77 77
          <ClosedNodesVersion>2</ClosedNodesVersion>
78
-         <ClosedNode></ClosedNode>
79 78
       </ClosedNodes>
80 79
       <SelectedItems>
81 80
          <SelectedItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</SelectedItem>
82 81
       </SelectedItems>
83 82
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
84 83
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
85
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000b0000000020000000000000000000000000200000064ffffffff000000810000000300000002000000b00000000100000003000000000000000100000003</ViewHeaderState>
84
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000184000000020000000000000000000000000200000064ffffffff000000810000000300000002000001840000000100000003000000000000000100000003</ViewHeaderState>
86 85
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
87 86
       <CurrentItem>alu_test - behavior (/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test.vhd)</CurrentItem>
88 87
    </ItemView>
@@ -104,13 +103,13 @@
104 103
          <ClosedNodesVersion>1</ClosedNodesVersion>
105 104
       </ClosedNodes>
106 105
       <SelectedItems>
107
-         <SelectedItem></SelectedItem>
106
+         <SelectedItem>Simulate Behavioral Model</SelectedItem>
108 107
       </SelectedItems>
109 108
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
110 109
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
111
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
110
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000103000000010000000100000000000000000000000064ffffffff000000810000000000000001000001030000000100000000</ViewHeaderState>
112 111
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
113
-      <CurrentItem></CurrentItem>
112
+      <CurrentItem>Simulate Behavioral Model</CurrentItem>
114 113
    </ItemView>
115 114
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
116 115
       <ClosedNodes>
@@ -118,13 +117,13 @@
118 117
          <ClosedNode>Design Utilities</ClosedNode>
119 118
       </ClosedNodes>
120 119
       <SelectedItems>
121
-         <SelectedItem></SelectedItem>
120
+         <SelectedItem/>
122 121
       </SelectedItems>
123 122
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
124 123
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
125 124
       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f6000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f60000000100000000</ViewHeaderState>
126 125
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
127
-      <CurrentItem></CurrentItem>
126
+      <CurrentItem/>
128 127
    </ItemView>
129 128
    <SourceProcessView>000000ff0000000000000002000001620000011b01000000040100000002</SourceProcessView>
130 129
    <CurrentView>Implementation</CurrentView>

+ 2
- 2
xilinx/ALU/iseconfig/alu.xreport View File

@@ -1,11 +1,11 @@
1 1
 <?xml version='1.0' encoding='UTF-8'?>
2 2
 <report-views version="2.0" >
3 3
  <header>
4
-  <DateModified>2021-04-13T11:53:22</DateModified>
4
+  <DateModified>2021-04-15T10:56:37</DateModified>
5 5
   <ModuleName>alu</ModuleName>
6 6
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
7 7
   <SavedFilePath>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/iseconfig/alu.xreport</SavedFilePath>
8
-  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU</ImplementationReportsDirectory>
8
+  <ImplementationReportsDirectory>/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/</ImplementationReportsDirectory>
9 9
   <DateInitialized>2021-04-13T10:12:38</DateInitialized>
10 10
   <EnableMessageFiltering>false</EnableMessageFiltering>
11 11
  </header>

+ 1
- 20
xilinx/ALU/isim.log View File

@@ -1,5 +1,5 @@
1 1
 ISim log file
2
-Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu_test_isim_beh.wdb 
2
+Running: /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/bm_instr_test_isim_beh.wdb 
3 3
 ISim O.87xd (signature 0x8ddf5b5d)
4 4
 WARNING: A WEBPACK license was found.
5 5
 WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
@@ -10,24 +10,5 @@ Time resolution is 1 ps
10 10
 # wave add /
11 11
 # run 1000 ns
12 12
 Simulator is doing circuit initialization process.
13
-at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
14
-Finished circuit initialization process.
15
-ISim O.87xd (signature 0x8ddf5b5d)
16
-WARNING: A WEBPACK license was found.
17
-WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
18
-WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
19
-This is a Lite version of ISim.
20
-# run 1000 ns
21
-Simulator is doing circuit initialization process.
22
-at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
23
-Finished circuit initialization process.
24
-ISim O.87xd (signature 0x8ddf5b5d)
25
-WARNING: A WEBPACK license was found.
26
-WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
27
-WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
28
-This is a Lite version of ISim.
29
-# run 1000 ns
30
-Simulator is doing circuit initialization process.
31
-at 0 ps, Instance /alu_test/uut/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
32 13
 Finished circuit initialization process.
33 14
 # exit 0

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/ISimEngine-DesignHierarchy1.dbg View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/alu_isim_beh.exe View File


+ 0
- 29
xilinx/ALU/isim/alu_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   alu_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  1
5
-     -socket  46007
6
-
7
-Tue Apr 13 11:05:00 2021
8
-
9
-
10
- Elaboration Time: 0 sec
11
-
12
- Current Memory Usage: 181.678 Meg
13
-
14
- Total Signals          : 14
15
- Total Nets             : 91
16
- Total Signal Drivers   : 11
17
- Total Blocks           : 5
18
- Total Primitive Blocks : 5
19
- Total Processes        : 11
20
- Total Traceable Variables  : 15
21
- Total Scalar Nets and Variables : 592
22
-Total Line Count : 11
23
-
24
- Total Simulation Time: 0.08 sec
25
-
26
- Current Memory Usage: 257.18 Meg
27
-
28
-Tue Apr 13 11:05:21 2021
29
-

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/netId1.dat View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/tmp_save/_1 View File


+ 0
- 931
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.c View File

@@ -1,931 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
25
-extern char *IEEE_P_2592010699;
26
-extern char *IEEE_P_3620187407;
27
-
28
-unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
29
-char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
30
-char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
31
-char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
32
-
33
-
34
-static void work_a_2725559894_3212880686_p_0(char *t0)
35
-{
36
-    char t5[16];
37
-    char t7[16];
38
-    char *t1;
39
-    char *t3;
40
-    char *t4;
41
-    char *t6;
42
-    char *t8;
43
-    char *t9;
44
-    int t10;
45
-    unsigned int t11;
46
-    unsigned char t12;
47
-    char *t13;
48
-    char *t14;
49
-    char *t15;
50
-    char *t16;
51
-    char *t17;
52
-    char *t18;
53
-
54
-LAB0:    xsi_set_current_line(54, ng0);
55
-
56
-LAB3:    t1 = (t0 + 11471);
57
-    t3 = (t0 + 1032U);
58
-    t4 = *((char **)t3);
59
-    t6 = ((IEEE_P_2592010699) + 4000);
60
-    t8 = (t7 + 0U);
61
-    t9 = (t8 + 0U);
62
-    *((int *)t9) = 0;
63
-    t9 = (t8 + 4U);
64
-    *((int *)t9) = 0;
65
-    t9 = (t8 + 8U);
66
-    *((int *)t9) = 1;
67
-    t10 = (0 - 0);
68
-    t11 = (t10 * 1);
69
-    t11 = (t11 + 1);
70
-    t9 = (t8 + 12U);
71
-    *((unsigned int *)t9) = t11;
72
-    t9 = (t0 + 11224U);
73
-    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
74
-    t11 = (1U + 8U);
75
-    t12 = (9U != t11);
76
-    if (t12 == 1)
77
-        goto LAB5;
78
-
79
-LAB6:    t13 = (t0 + 7304);
80
-    t14 = (t13 + 56U);
81
-    t15 = *((char **)t14);
82
-    t16 = (t15 + 56U);
83
-    t17 = *((char **)t16);
84
-    memcpy(t17, t3, 9U);
85
-    xsi_driver_first_trans_fast(t13);
86
-
87
-LAB2:    t18 = (t0 + 7064);
88
-    *((int *)t18) = 1;
89
-
90
-LAB1:    return;
91
-LAB4:    goto LAB2;
92
-
93
-LAB5:    xsi_size_not_matching(9U, t11, 0);
94
-    goto LAB6;
95
-
96
-}
97
-
98
-static void work_a_2725559894_3212880686_p_1(char *t0)
99
-{
100
-    char t5[16];
101
-    char t7[16];
102
-    char *t1;
103
-    char *t3;
104
-    char *t4;
105
-    char *t6;
106
-    char *t8;
107
-    char *t9;
108
-    int t10;
109
-    unsigned int t11;
110
-    unsigned char t12;
111
-    char *t13;
112
-    char *t14;
113
-    char *t15;
114
-    char *t16;
115
-    char *t17;
116
-    char *t18;
117
-
118
-LAB0:    xsi_set_current_line(55, ng0);
119
-
120
-LAB3:    t1 = (t0 + 11472);
121
-    t3 = (t0 + 1192U);
122
-    t4 = *((char **)t3);
123
-    t6 = ((IEEE_P_2592010699) + 4000);
124
-    t8 = (t7 + 0U);
125
-    t9 = (t8 + 0U);
126
-    *((int *)t9) = 0;
127
-    t9 = (t8 + 4U);
128
-    *((int *)t9) = 0;
129
-    t9 = (t8 + 8U);
130
-    *((int *)t9) = 1;
131
-    t10 = (0 - 0);
132
-    t11 = (t10 * 1);
133
-    t11 = (t11 + 1);
134
-    t9 = (t8 + 12U);
135
-    *((unsigned int *)t9) = t11;
136
-    t9 = (t0 + 11240U);
137
-    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
138
-    t11 = (1U + 8U);
139
-    t12 = (9U != t11);
140
-    if (t12 == 1)
141
-        goto LAB5;
142
-
143
-LAB6:    t13 = (t0 + 7368);
144
-    t14 = (t13 + 56U);
145
-    t15 = *((char **)t14);
146
-    t16 = (t15 + 56U);
147
-    t17 = *((char **)t16);
148
-    memcpy(t17, t3, 9U);
149
-    xsi_driver_first_trans_fast(t13);
150
-
151
-LAB2:    t18 = (t0 + 7080);
152
-    *((int *)t18) = 1;
153
-
154
-LAB1:    return;
155
-LAB4:    goto LAB2;
156
-
157
-LAB5:    xsi_size_not_matching(9U, t11, 0);
158
-    goto LAB6;
159
-
160
-}
161
-
162
-static void work_a_2725559894_3212880686_p_2(char *t0)
163
-{
164
-    char t1[16];
165
-    char *t2;
166
-    char *t3;
167
-    char *t4;
168
-    char *t5;
169
-    char *t6;
170
-    char *t7;
171
-    unsigned int t8;
172
-    unsigned int t9;
173
-    unsigned char t10;
174
-    char *t11;
175
-    char *t12;
176
-    char *t13;
177
-    char *t14;
178
-    char *t15;
179
-    char *t16;
180
-
181
-LAB0:    xsi_set_current_line(56, ng0);
182
-
183
-LAB3:    t2 = (t0 + 2312U);
184
-    t3 = *((char **)t2);
185
-    t2 = (t0 + 11288U);
186
-    t4 = (t0 + 2472U);
187
-    t5 = *((char **)t4);
188
-    t4 = (t0 + 11304U);
189
-    t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
190
-    t7 = (t1 + 12U);
191
-    t8 = *((unsigned int *)t7);
192
-    t9 = (1U * t8);
193
-    t10 = (9U != t9);
194
-    if (t10 == 1)
195
-        goto LAB5;
196
-
197
-LAB6:    t11 = (t0 + 7432);
198
-    t12 = (t11 + 56U);
199
-    t13 = *((char **)t12);
200
-    t14 = (t13 + 56U);
201
-    t15 = *((char **)t14);
202
-    memcpy(t15, t6, 9U);
203
-    xsi_driver_first_trans_fast(t11);
204
-
205
-LAB2:    t16 = (t0 + 7096);
206
-    *((int *)t16) = 1;
207
-
208
-LAB1:    return;
209
-LAB4:    goto LAB2;
210
-
211
-LAB5:    xsi_size_not_matching(9U, t9, 0);
212
-    goto LAB6;
213
-
214
-}
215
-
216
-static void work_a_2725559894_3212880686_p_3(char *t0)
217
-{
218
-    char t1[16];
219
-    char *t2;
220
-    char *t3;
221
-    char *t4;
222
-    char *t5;
223
-    char *t6;
224
-    char *t7;
225
-    unsigned int t8;
226
-    unsigned int t9;
227
-    unsigned char t10;
228
-    char *t11;
229
-    char *t12;
230
-    char *t13;
231
-    char *t14;
232
-    char *t15;
233
-    char *t16;
234
-
235
-LAB0:    xsi_set_current_line(57, ng0);
236
-
237
-LAB3:    t2 = (t0 + 2312U);
238
-    t3 = *((char **)t2);
239
-    t2 = (t0 + 11288U);
240
-    t4 = (t0 + 2472U);
241
-    t5 = *((char **)t4);
242
-    t4 = (t0 + 11304U);
243
-    t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
244
-    t7 = (t1 + 12U);
245
-    t8 = *((unsigned int *)t7);
246
-    t9 = (1U * t8);
247
-    t10 = (9U != t9);
248
-    if (t10 == 1)
249
-        goto LAB5;
250
-
251
-LAB6:    t11 = (t0 + 7496);
252
-    t12 = (t11 + 56U);
253
-    t13 = *((char **)t12);
254
-    t14 = (t13 + 56U);
255
-    t15 = *((char **)t14);
256
-    memcpy(t15, t6, 9U);
257
-    xsi_driver_first_trans_fast(t11);
258
-
259
-LAB2:    t16 = (t0 + 7112);
260
-    *((int *)t16) = 1;
261
-
262
-LAB1:    return;
263
-LAB4:    goto LAB2;
264
-
265
-LAB5:    xsi_size_not_matching(9U, t9, 0);
266
-    goto LAB6;
267
-
268
-}
269
-
270
-static void work_a_2725559894_3212880686_p_4(char *t0)
271
-{
272
-    char t1[16];
273
-    char *t2;
274
-    char *t3;
275
-    char *t4;
276
-    char *t5;
277
-    char *t6;
278
-    char *t7;
279
-    unsigned int t8;
280
-    unsigned int t9;
281
-    unsigned char t10;
282
-    char *t11;
283
-    char *t12;
284
-    char *t13;
285
-    char *t14;
286
-    char *t15;
287
-    char *t16;
288
-
289
-LAB0:    xsi_set_current_line(58, ng0);
290
-
291
-LAB3:    t2 = (t0 + 1032U);
292
-    t3 = *((char **)t2);
293
-    t2 = (t0 + 11224U);
294
-    t4 = (t0 + 1192U);
295
-    t5 = *((char **)t4);
296
-    t4 = (t0 + 11240U);
297
-    t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
298
-    t7 = (t1 + 12U);
299
-    t8 = *((unsigned int *)t7);
300
-    t9 = (1U * t8);
301
-    t10 = (16U != t9);
302
-    if (t10 == 1)
303
-        goto LAB5;
304
-
305
-LAB6:    t11 = (t0 + 7560);
306
-    t12 = (t11 + 56U);
307
-    t13 = *((char **)t12);
308
-    t14 = (t13 + 56U);
309
-    t15 = *((char **)t14);
310
-    memcpy(t15, t6, 16U);
311
-    xsi_driver_first_trans_fast(t11);
312
-
313
-LAB2:    t16 = (t0 + 7128);
314
-    *((int *)t16) = 1;
315
-
316
-LAB1:    return;
317
-LAB4:    goto LAB2;
318
-
319
-LAB5:    xsi_size_not_matching(16U, t9, 0);
320
-    goto LAB6;
321
-
322
-}
323
-
324
-static void work_a_2725559894_3212880686_p_5(char *t0)
325
-{
326
-    char t5[16];
327
-    char t23[16];
328
-    char t41[16];
329
-    char *t1;
330
-    char *t2;
331
-    char *t3;
332
-    char *t6;
333
-    char *t7;
334
-    int t8;
335
-    unsigned int t9;
336
-    unsigned char t10;
337
-    char *t11;
338
-    unsigned int t12;
339
-    unsigned int t13;
340
-    char *t14;
341
-    char *t15;
342
-    char *t16;
343
-    char *t17;
344
-    char *t18;
345
-    char *t19;
346
-    char *t20;
347
-    char *t21;
348
-    char *t24;
349
-    char *t25;
350
-    int t26;
351
-    unsigned int t27;
352
-    unsigned char t28;
353
-    char *t29;
354
-    unsigned int t30;
355
-    unsigned int t31;
356
-    char *t32;
357
-    char *t33;
358
-    char *t34;
359
-    char *t35;
360
-    char *t36;
361
-    char *t37;
362
-    char *t38;
363
-    char *t39;
364
-    char *t42;
365
-    char *t43;
366
-    int t44;
367
-    unsigned int t45;
368
-    unsigned char t46;
369
-    char *t47;
370
-    unsigned int t48;
371
-    unsigned int t49;
372
-    char *t50;
373
-    char *t51;
374
-    char *t52;
375
-    char *t53;
376
-    char *t54;
377
-    char *t55;
378
-    char *t56;
379
-    char *t57;
380
-    char *t58;
381
-    char *t59;
382
-    char *t60;
383
-    char *t61;
384
-    char *t62;
385
-
386
-LAB0:    xsi_set_current_line(60, ng0);
387
-    t1 = (t0 + 1352U);
388
-    t2 = *((char **)t1);
389
-    t1 = (t0 + 11256U);
390
-    t3 = (t0 + 11473);
391
-    t6 = (t5 + 0U);
392
-    t7 = (t6 + 0U);
393
-    *((int *)t7) = 0;
394
-    t7 = (t6 + 4U);
395
-    *((int *)t7) = 1;
396
-    t7 = (t6 + 8U);
397
-    *((int *)t7) = 1;
398
-    t8 = (1 - 0);
399
-    t9 = (t8 * 1);
400
-    t9 = (t9 + 1);
401
-    t7 = (t6 + 12U);
402
-    *((unsigned int *)t7) = t9;
403
-    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
404
-    if (t10 != 0)
405
-        goto LAB3;
406
-
407
-LAB4:    t19 = (t0 + 1352U);
408
-    t20 = *((char **)t19);
409
-    t19 = (t0 + 11256U);
410
-    t21 = (t0 + 11475);
411
-    t24 = (t23 + 0U);
412
-    t25 = (t24 + 0U);
413
-    *((int *)t25) = 0;
414
-    t25 = (t24 + 4U);
415
-    *((int *)t25) = 1;
416
-    t25 = (t24 + 8U);
417
-    *((int *)t25) = 1;
418
-    t26 = (1 - 0);
419
-    t27 = (t26 * 1);
420
-    t27 = (t27 + 1);
421
-    t25 = (t24 + 12U);
422
-    *((unsigned int *)t25) = t27;
423
-    t28 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t20, t19, t21, t23);
424
-    if (t28 != 0)
425
-        goto LAB5;
426
-
427
-LAB6:    t37 = (t0 + 1352U);
428
-    t38 = *((char **)t37);
429
-    t37 = (t0 + 11256U);
430
-    t39 = (t0 + 11477);
431
-    t42 = (t41 + 0U);
432
-    t43 = (t42 + 0U);
433
-    *((int *)t43) = 0;
434
-    t43 = (t42 + 4U);
435
-    *((int *)t43) = 1;
436
-    t43 = (t42 + 8U);
437
-    *((int *)t43) = 1;
438
-    t44 = (1 - 0);
439
-    t45 = (t44 * 1);
440
-    t45 = (t45 + 1);
441
-    t43 = (t42 + 12U);
442
-    *((unsigned int *)t43) = t45;
443
-    t46 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t38, t37, t39, t41);
444
-    if (t46 != 0)
445
-        goto LAB7;
446
-
447
-LAB8:
448
-LAB9:    t55 = xsi_get_transient_memory(8U);
449
-    memset(t55, 0, 8U);
450
-    t56 = t55;
451
-    memset(t56, (unsigned char)2, 8U);
452
-    t57 = (t0 + 7624);
453
-    t58 = (t57 + 56U);
454
-    t59 = *((char **)t58);
455
-    t60 = (t59 + 56U);
456
-    t61 = *((char **)t60);
457
-    memcpy(t61, t55, 8U);
458
-    xsi_driver_first_trans_fast(t57);
459
-
460
-LAB2:    t62 = (t0 + 7144);
461
-    *((int *)t62) = 1;
462
-
463
-LAB1:    return;
464
-LAB3:    t7 = (t0 + 2632U);
465
-    t11 = *((char **)t7);
466
-    t9 = (8 - 7);
467
-    t12 = (t9 * 1U);
468
-    t13 = (0 + t12);
469
-    t7 = (t11 + t13);
470
-    t14 = (t0 + 7624);
471
-    t15 = (t14 + 56U);
472
-    t16 = *((char **)t15);
473
-    t17 = (t16 + 56U);
474
-    t18 = *((char **)t17);
475
-    memcpy(t18, t7, 8U);
476
-    xsi_driver_first_trans_fast(t14);
477
-    goto LAB2;
478
-
479
-LAB5:    t25 = (t0 + 2792U);
480
-    t29 = *((char **)t25);
481
-    t27 = (8 - 7);
482
-    t30 = (t27 * 1U);
483
-    t31 = (0 + t30);
484
-    t25 = (t29 + t31);
485
-    t32 = (t0 + 7624);
486
-    t33 = (t32 + 56U);
487
-    t34 = *((char **)t33);
488
-    t35 = (t34 + 56U);
489
-    t36 = *((char **)t35);
490
-    memcpy(t36, t25, 8U);
491
-    xsi_driver_first_trans_fast(t32);
492
-    goto LAB2;
493
-
494
-LAB7:    t43 = (t0 + 2952U);
495
-    t47 = *((char **)t43);
496
-    t45 = (15 - 7);
497
-    t48 = (t45 * 1U);
498
-    t49 = (0 + t48);
499
-    t43 = (t47 + t49);
500
-    t50 = (t0 + 7624);
501
-    t51 = (t50 + 56U);
502
-    t52 = *((char **)t51);
503
-    t53 = (t52 + 56U);
504
-    t54 = *((char **)t53);
505
-    memcpy(t54, t43, 8U);
506
-    xsi_driver_first_trans_fast(t50);
507
-    goto LAB2;
508
-
509
-LAB10:    goto LAB2;
510
-
511
-}
512
-
513
-static void work_a_2725559894_3212880686_p_6(char *t0)
514
-{
515
-    char t7[16];
516
-    char t13[16];
517
-    char t21[16];
518
-    unsigned char t1;
519
-    char *t2;
520
-    char *t3;
521
-    unsigned int t4;
522
-    unsigned int t5;
523
-    unsigned int t6;
524
-    char *t8;
525
-    char *t9;
526
-    int t10;
527
-    unsigned int t11;
528
-    char *t14;
529
-    char *t15;
530
-    int t16;
531
-    unsigned char t17;
532
-    char *t18;
533
-    char *t19;
534
-    char *t22;
535
-    char *t23;
536
-    int t24;
537
-    unsigned char t25;
538
-    char *t26;
539
-    char *t27;
540
-    char *t28;
541
-    char *t29;
542
-    char *t30;
543
-    char *t31;
544
-    char *t32;
545
-    char *t33;
546
-    char *t34;
547
-    char *t35;
548
-
549
-LAB0:    xsi_set_current_line(64, ng0);
550
-    t2 = (t0 + 2952U);
551
-    t3 = *((char **)t2);
552
-    t4 = (15 - 15);
553
-    t5 = (t4 * 1U);
554
-    t6 = (0 + t5);
555
-    t2 = (t3 + t6);
556
-    t8 = (t7 + 0U);
557
-    t9 = (t8 + 0U);
558
-    *((int *)t9) = 15;
559
-    t9 = (t8 + 4U);
560
-    *((int *)t9) = 8;
561
-    t9 = (t8 + 8U);
562
-    *((int *)t9) = -1;
563
-    t10 = (8 - 15);
564
-    t11 = (t10 * -1);
565
-    t11 = (t11 + 1);
566
-    t9 = (t8 + 12U);
567
-    *((unsigned int *)t9) = t11;
568
-    t9 = (t0 + 11479);
569
-    t14 = (t13 + 0U);
570
-    t15 = (t14 + 0U);
571
-    *((int *)t15) = 0;
572
-    t15 = (t14 + 4U);
573
-    *((int *)t15) = 7;
574
-    t15 = (t14 + 8U);
575
-    *((int *)t15) = 1;
576
-    t16 = (7 - 0);
577
-    t11 = (t16 * 1);
578
-    t11 = (t11 + 1);
579
-    t15 = (t14 + 12U);
580
-    *((unsigned int *)t15) = t11;
581
-    t17 = ieee_p_3620187407_sub_1306455576380142462_3965413181(IEEE_P_3620187407, t2, t7, t9, t13);
582
-    if (t17 == 1)
583
-        goto LAB5;
584
-
585
-LAB6:    t1 = (unsigned char)0;
586
-
587
-LAB7:    if (t1 != 0)
588
-        goto LAB3;
589
-
590
-LAB4:
591
-LAB8:    t30 = (t0 + 7688);
592
-    t31 = (t30 + 56U);
593
-    t32 = *((char **)t31);
594
-    t33 = (t32 + 56U);
595
-    t34 = *((char **)t33);
596
-    *((unsigned char *)t34) = (unsigned char)2;
597
-    xsi_driver_first_trans_fast_port(t30);
598
-
599
-LAB2:    t35 = (t0 + 7160);
600
-    *((int *)t35) = 1;
601
-
602
-LAB1:    return;
603
-LAB3:    t23 = (t0 + 7688);
604
-    t26 = (t23 + 56U);
605
-    t27 = *((char **)t26);
606
-    t28 = (t27 + 56U);
607
-    t29 = *((char **)t28);
608
-    *((unsigned char *)t29) = (unsigned char)3;
609
-    xsi_driver_first_trans_fast_port(t23);
610
-    goto LAB2;
611
-
612
-LAB5:    t15 = (t0 + 1352U);
613
-    t18 = *((char **)t15);
614
-    t15 = (t0 + 11256U);
615
-    t19 = (t0 + 11487);
616
-    t22 = (t21 + 0U);
617
-    t23 = (t22 + 0U);
618
-    *((int *)t23) = 0;
619
-    t23 = (t22 + 4U);
620
-    *((int *)t23) = 2;
621
-    t23 = (t22 + 8U);
622
-    *((int *)t23) = 1;
623
-    t24 = (2 - 0);
624
-    t11 = (t24 * 1);
625
-    t11 = (t11 + 1);
626
-    t23 = (t22 + 12U);
627
-    *((unsigned int *)t23) = t11;
628
-    t25 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t18, t15, t19, t21);
629
-    t1 = t25;
630
-    goto LAB7;
631
-
632
-LAB9:    goto LAB2;
633
-
634
-}
635
-
636
-static void work_a_2725559894_3212880686_p_7(char *t0)
637
-{
638
-    char t14[16];
639
-    unsigned char t1;
640
-    char *t2;
641
-    char *t3;
642
-    int t4;
643
-    unsigned int t5;
644
-    unsigned int t6;
645
-    unsigned int t7;
646
-    unsigned char t8;
647
-    unsigned char t9;
648
-    char *t10;
649
-    char *t11;
650
-    char *t12;
651
-    char *t15;
652
-    char *t16;
653
-    int t17;
654
-    unsigned int t18;
655
-    unsigned char t19;
656
-    char *t20;
657
-    char *t21;
658
-    char *t22;
659
-    char *t23;
660
-    char *t24;
661
-    char *t25;
662
-    char *t26;
663
-    char *t27;
664
-    char *t28;
665
-    char *t29;
666
-
667
-LAB0:    xsi_set_current_line(66, ng0);
668
-    t2 = (t0 + 2632U);
669
-    t3 = *((char **)t2);
670
-    t4 = (8 - 8);
671
-    t5 = (t4 * -1);
672
-    t6 = (1U * t5);
673
-    t7 = (0 + t6);
674
-    t2 = (t3 + t7);
675
-    t8 = *((unsigned char *)t2);
676
-    t9 = (t8 == (unsigned char)3);
677
-    if (t9 == 1)
678
-        goto LAB5;
679
-
680
-LAB6:    t1 = (unsigned char)0;
681
-
682
-LAB7:    if (t1 != 0)
683
-        goto LAB3;
684
-
685
-LAB4:
686
-LAB8:    t24 = (t0 + 7752);
687
-    t25 = (t24 + 56U);
688
-    t26 = *((char **)t25);
689
-    t27 = (t26 + 56U);
690
-    t28 = *((char **)t27);
691
-    *((unsigned char *)t28) = (unsigned char)2;
692
-    xsi_driver_first_trans_fast_port(t24);
693
-
694
-LAB2:    t29 = (t0 + 7176);
695
-    *((int *)t29) = 1;
696
-
697
-LAB1:    return;
698
-LAB3:    t16 = (t0 + 7752);
699
-    t20 = (t16 + 56U);
700
-    t21 = *((char **)t20);
701
-    t22 = (t21 + 56U);
702
-    t23 = *((char **)t22);
703
-    *((unsigned char *)t23) = (unsigned char)3;
704
-    xsi_driver_first_trans_fast_port(t16);
705
-    goto LAB2;
706
-
707
-LAB5:    t10 = (t0 + 1352U);
708
-    t11 = *((char **)t10);
709
-    t10 = (t0 + 11256U);
710
-    t12 = (t0 + 11490);
711
-    t15 = (t14 + 0U);
712
-    t16 = (t15 + 0U);
713
-    *((int *)t16) = 0;
714
-    t16 = (t15 + 4U);
715
-    *((int *)t16) = 1;
716
-    t16 = (t15 + 8U);
717
-    *((int *)t16) = 1;
718
-    t17 = (1 - 0);
719
-    t18 = (t17 * 1);
720
-    t18 = (t18 + 1);
721
-    t16 = (t15 + 12U);
722
-    *((unsigned int *)t16) = t18;
723
-    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
724
-    t1 = t19;
725
-    goto LAB7;
726
-
727
-LAB9:    goto LAB2;
728
-
729
-}
730
-
731
-static void work_a_2725559894_3212880686_p_8(char *t0)
732
-{
733
-    char t14[16];
734
-    unsigned char t1;
735
-    char *t2;
736
-    char *t3;
737
-    int t4;
738
-    unsigned int t5;
739
-    unsigned int t6;
740
-    unsigned int t7;
741
-    unsigned char t8;
742
-    unsigned char t9;
743
-    char *t10;
744
-    char *t11;
745
-    char *t12;
746
-    char *t15;
747
-    char *t16;
748
-    int t17;
749
-    unsigned int t18;
750
-    unsigned char t19;
751
-    char *t20;
752
-    char *t21;
753
-    char *t22;
754
-    char *t23;
755
-    char *t24;
756
-    char *t25;
757
-    char *t26;
758
-    char *t27;
759
-    char *t28;
760
-    char *t29;
761
-
762
-LAB0:    xsi_set_current_line(68, ng0);
763
-    t2 = (t0 + 2792U);
764
-    t3 = *((char **)t2);
765
-    t4 = (8 - 8);
766
-    t5 = (t4 * -1);
767
-    t6 = (1U * t5);
768
-    t7 = (0 + t6);
769
-    t2 = (t3 + t7);
770
-    t8 = *((unsigned char *)t2);
771
-    t9 = (t8 == (unsigned char)3);
772
-    if (t9 == 1)
773
-        goto LAB5;
774
-
775
-LAB6:    t1 = (unsigned char)0;
776
-
777
-LAB7:    if (t1 != 0)
778
-        goto LAB3;
779
-
780
-LAB4:
781
-LAB8:    t24 = (t0 + 7816);
782
-    t25 = (t24 + 56U);
783
-    t26 = *((char **)t25);
784
-    t27 = (t26 + 56U);
785
-    t28 = *((char **)t27);
786
-    *((unsigned char *)t28) = (unsigned char)2;
787
-    xsi_driver_first_trans_fast_port(t24);
788
-
789
-LAB2:    t29 = (t0 + 7192);
790
-    *((int *)t29) = 1;
791
-
792
-LAB1:    return;
793
-LAB3:    t16 = (t0 + 7816);
794
-    t20 = (t16 + 56U);
795
-    t21 = *((char **)t20);
796
-    t22 = (t21 + 56U);
797
-    t23 = *((char **)t22);
798
-    *((unsigned char *)t23) = (unsigned char)3;
799
-    xsi_driver_first_trans_fast_port(t16);
800
-    goto LAB2;
801
-
802
-LAB5:    t10 = (t0 + 1352U);
803
-    t11 = *((char **)t10);
804
-    t10 = (t0 + 11256U);
805
-    t12 = (t0 + 11492);
806
-    t15 = (t14 + 0U);
807
-    t16 = (t15 + 0U);
808
-    *((int *)t16) = 0;
809
-    t16 = (t15 + 4U);
810
-    *((int *)t16) = 1;
811
-    t16 = (t15 + 8U);
812
-    *((int *)t16) = 1;
813
-    t17 = (1 - 0);
814
-    t18 = (t17 * 1);
815
-    t18 = (t18 + 1);
816
-    t16 = (t15 + 12U);
817
-    *((unsigned int *)t16) = t18;
818
-    t19 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t11, t10, t12, t14);
819
-    t1 = t19;
820
-    goto LAB7;
821
-
822
-LAB9:    goto LAB2;
823
-
824
-}
825
-
826
-static void work_a_2725559894_3212880686_p_9(char *t0)
827
-{
828
-    char t5[16];
829
-    char *t1;
830
-    char *t2;
831
-    char *t3;
832
-    char *t6;
833
-    char *t7;
834
-    int t8;
835
-    unsigned int t9;
836
-    unsigned char t10;
837
-    char *t11;
838
-    char *t12;
839
-    char *t13;
840
-    char *t14;
841
-    char *t15;
842
-    char *t16;
843
-    char *t17;
844
-    char *t18;
845
-    char *t19;
846
-    char *t20;
847
-
848
-LAB0:    xsi_set_current_line(70, ng0);
849
-    t1 = (t0 + 3112U);
850
-    t2 = *((char **)t1);
851
-    t1 = (t0 + 11368U);
852
-    t3 = (t0 + 11494);
853
-    t6 = (t5 + 0U);
854
-    t7 = (t6 + 0U);
855
-    *((int *)t7) = 0;
856
-    t7 = (t6 + 4U);
857
-    *((int *)t7) = 7;
858
-    t7 = (t6 + 8U);
859
-    *((int *)t7) = 1;
860
-    t8 = (7 - 0);
861
-    t9 = (t8 * 1);
862
-    t9 = (t9 + 1);
863
-    t7 = (t6 + 12U);
864
-    *((unsigned int *)t7) = t9;
865
-    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
866
-    if (t10 != 0)
867
-        goto LAB3;
868
-
869
-LAB4:
870
-LAB5:    t15 = (t0 + 7880);
871
-    t16 = (t15 + 56U);
872
-    t17 = *((char **)t16);
873
-    t18 = (t17 + 56U);
874
-    t19 = *((char **)t18);
875
-    *((unsigned char *)t19) = (unsigned char)2;
876
-    xsi_driver_first_trans_fast_port(t15);
877
-
878
-LAB2:    t20 = (t0 + 7208);
879
-    *((int *)t20) = 1;
880
-
881
-LAB1:    return;
882
-LAB3:    t7 = (t0 + 7880);
883
-    t11 = (t7 + 56U);
884
-    t12 = *((char **)t11);
885
-    t13 = (t12 + 56U);
886
-    t14 = *((char **)t13);
887
-    *((unsigned char *)t14) = (unsigned char)3;
888
-    xsi_driver_first_trans_fast_port(t7);
889
-    goto LAB2;
890
-
891
-LAB6:    goto LAB2;
892
-
893
-}
894
-
895
-static void work_a_2725559894_3212880686_p_10(char *t0)
896
-{
897
-    char *t1;
898
-    char *t2;
899
-    char *t3;
900
-    char *t4;
901
-    char *t5;
902
-    char *t6;
903
-    char *t7;
904
-
905
-LAB0:    xsi_set_current_line(72, ng0);
906
-
907
-LAB3:    t1 = (t0 + 3112U);
908
-    t2 = *((char **)t1);
909
-    t1 = (t0 + 7944);
910
-    t3 = (t1 + 56U);
911
-    t4 = *((char **)t3);
912
-    t5 = (t4 + 56U);
913
-    t6 = *((char **)t5);
914
-    memcpy(t6, t2, 8U);
915
-    xsi_driver_first_trans_fast_port(t1);
916
-
917
-LAB2:    t7 = (t0 + 7224);
918
-    *((int *)t7) = 1;
919
-
920
-LAB1:    return;
921
-LAB4:    goto LAB2;
922
-
923
-}
924
-
925
-
926
-extern void work_a_2725559894_3212880686_init()
927
-{
928
-	static char *pe[] = {(void *)work_a_2725559894_3212880686_p_0,(void *)work_a_2725559894_3212880686_p_1,(void *)work_a_2725559894_3212880686_p_2,(void *)work_a_2725559894_3212880686_p_3,(void *)work_a_2725559894_3212880686_p_4,(void *)work_a_2725559894_3212880686_p_5,(void *)work_a_2725559894_3212880686_p_6,(void *)work_a_2725559894_3212880686_p_7,(void *)work_a_2725559894_3212880686_p_8,(void *)work_a_2725559894_3212880686_p_9,(void *)work_a_2725559894_3212880686_p_10};
929
-	xsi_register_didat("work_a_2725559894_3212880686", "isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat");
930
-	xsi_register_executes(pe);
931
-}

BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.didat View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/a_2725559894_3212880686.lin64.o View File


BIN
xilinx/ALU/isim/alu_isim_beh.exe.sim/work/alu_isim_beh.exe_main.lin64.o View File


BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg View File


BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/alu_test_isim_beh.exe View File


+ 0
- 29
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/isimkernel.log View File

@@ -1,29 +0,0 @@
1
-Command line:
2
-   alu_test_isim_beh.exe
3
-     -simmode  gui
4
-     -simrunnum  0
5
-     -socket  38597
6
-
7
-Tue Apr 13 11:10:10 2021
8
-
9
-
10
- Elaboration Time: 0.01 sec
11
-
12
- Current Memory Usage: 181.686 Meg
13
-
14
- Total Signals          : 22
15
- Total Nets             : 91
16
- Total Signal Drivers   : 14
17
- Total Blocks           : 6
18
- Total Primitive Blocks : 5
19
- Total Processes        : 12
20
- Total Traceable Variables  : 15
21
- Total Scalar Nets and Variables : 592
22
-Total Line Count : 18
23
-
24
- Total Simulation Time: 0.19 sec
25
-
26
- Current Memory Usage: 257.188 Meg
27
-
28
-Tue Apr 13 11:14:15 2021
29
-

BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/netId.dat View File


BIN
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/tmp_save/_1 View File


+ 0
- 931
xilinx/ALU/isim/alu_test_isim_beh.exe.sim/work/a_0832606739_3212880686.c View File

@@ -1,931 +0,0 @@
1
-/**********************************************************************/
2
-/*   ____  ____                                                       */
3
-/*  /   /\/   /                                                       */
4
-/* /___/  \  /                                                        */
5
-/* \   \   \/                                                       */
6
-/*  \   \        Copyright (c) 2003-2009 Xilinx, Inc.                */
7
-/*  /   /          All Right Reserved.                                 */
8
-/* /---/   /\                                                         */
9
-/* \   \  /  \                                                      */
10
-/*  \___\/\___\                                                    */
11
-/***********************************************************************/
12
-
13
-/* This file is designed for use with ISim build 0x8ddf5b5d */
14
-
15
-#define XSI_HIDE_SYMBOL_SPEC true
16
-#include "xsi.h"
17
-#include <memory.h>
18
-#ifdef __GNUC__
19
-#include <stdlib.h>
20
-#else
21
-#include <malloc.h>
22
-#define alloca _alloca
23
-#endif
24
-static const char *ng0 = "/home/foussats/Bureau/projet_system/projet_systeme/xilinx/ALU/alu.vhd";
25
-extern char *IEEE_P_2592010699;
26
-extern char *IEEE_P_3620187407;
27
-
28
-unsigned char ieee_p_3620187407_sub_1306455576380142462_3965413181(char *, char *, char *, char *, char *);
29
-char *ieee_p_3620187407_sub_1496620905533613331_3965413181(char *, char *, char *, char *, char *, char *);
30
-char *ieee_p_3620187407_sub_1496620905533649268_3965413181(char *, char *, char *, char *, char *, char *);
31
-char *ieee_p_3620187407_sub_1496620905533721142_3965413181(char *, char *, char *, char *, char *, char *);
32
-
33
-
34
-static void work_a_0832606739_3212880686_p_0(char *t0)
35
-{
36
-    char t5[16];
37
-    char t7[16];
38
-    char *t1;
39
-    char *t3;
40
-    char *t4;
41
-    char *t6;
42
-    char *t8;
43
-    char *t9;
44
-    int t10;
45
-    unsigned int t11;
46
-    unsigned char t12;
47
-    char *t13;
48
-    char *t14;
49
-    char *t15;
50
-    char *t16;
51
-    char *t17;
52
-    char *t18;
53
-
54
-LAB0:    xsi_set_current_line(54, ng0);
55
-
56
-LAB3:    t1 = (t0 + 11471);
57
-    t3 = (t0 + 1032U);
58
-    t4 = *((char **)t3);
59
-    t6 = ((IEEE_P_2592010699) + 4000);
60
-    t8 = (t7 + 0U);
61
-    t9 = (t8 + 0U);
62
-    *((int *)t9) = 0;
63
-    t9 = (t8 + 4U);
64
-    *((int *)t9) = 0;
65
-    t9 = (t8 + 8U);
66
-    *((int *)t9) = 1;
67
-    t10 = (0 - 0);
68
-    t11 = (t10 * 1);
69
-    t11 = (t11 + 1);
70
-    t9 = (t8 + 12U);
71
-    *((unsigned int *)t9) = t11;
72
-    t9 = (t0 + 11224U);
73
-    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
74
-    t11 = (1U + 8U);
75
-    t12 = (9U != t11);
76
-    if (t12 == 1)
77
-        goto LAB5;
78
-
79
-LAB6:    t13 = (t0 + 7304);
80
-    t14 = (t13 + 56U);
81
-    t15 = *((char **)t14);
82
-    t16 = (t15 + 56U);
83
-    t17 = *((char **)t16);
84
-    memcpy(t17, t3, 9U);
85
-    xsi_driver_first_trans_fast(t13);
86
-
87
-LAB2:    t18 = (t0 + 7064);
88
-    *((int *)t18) = 1;
89
-
90
-LAB1:    return;
91
-LAB4:    goto LAB2;
92
-
93
-LAB5:    xsi_size_not_matching(9U, t11, 0);
94
-    goto LAB6;
95
-
96
-}
97
-
98
-static void work_a_0832606739_3212880686_p_1(char *t0)
99
-{
100
-    char t5[16];
101
-    char t7[16];
102
-    char *t1;
103
-    char *t3;
104
-    char *t4;
105
-    char *t6;
106
-    char *t8;
107
-    char *t9;
108
-    int t10;
109
-    unsigned int t11;
110
-    unsigned char t12;
111
-    char *t13;
112
-    char *t14;
113
-    char *t15;
114
-    char *t16;
115
-    char *t17;
116
-    char *t18;
117
-
118
-LAB0:    xsi_set_current_line(55, ng0);
119
-
120
-LAB3:    t1 = (t0 + 11472);
121
-    t3 = (t0 + 1192U);
122
-    t4 = *((char **)t3);
123
-    t6 = ((IEEE_P_2592010699) + 4000);
124
-    t8 = (t7 + 0U);
125
-    t9 = (t8 + 0U);
126
-    *((int *)t9) = 0;
127
-    t9 = (t8 + 4U);
128
-    *((int *)t9) = 0;
129
-    t9 = (t8 + 8U);
130
-    *((int *)t9) = 1;
131
-    t10 = (0 - 0);
132
-    t11 = (t10 * 1);
133
-    t11 = (t11 + 1);
134
-    t9 = (t8 + 12U);
135
-    *((unsigned int *)t9) = t11;
136
-    t9 = (t0 + 11240U);
137
-    t3 = xsi_base_array_concat(t3, t5, t6, (char)97, t1, t7, (char)97, t4, t9, (char)101);
138
-    t11 = (1U + 8U);
139
-    t12 = (9U != t11);
140
-    if (t12 == 1)
141
-        goto LAB5;
142
-
143
-LAB6:    t13 = (t0 + 7368);
144
-    t14 = (t13 + 56U);
145
-    t15 = *((char **)t14);
146
-    t16 = (t15 + 56U);
147
-    t17 = *((char **)t16);
148
-    memcpy(t17, t3, 9U);
149
-    xsi_driver_first_trans_fast(t13);
150
-
151
-LAB2:    t18 = (t0 + 7080);
152
-    *((int *)t18) = 1;
153
-
154
-LAB1:    return;
155
-LAB4:    goto LAB2;
156
-
157
-LAB5:    xsi_size_not_matching(9U, t11, 0);
158
-    goto LAB6;
159
-
160
-}
161
-
162
-static void work_a_0832606739_3212880686_p_2(char *t0)
163
-{
164
-    char t1[16];
165
-    char *t2;
166
-    char *t3;
167
-    char *t4;
168
-    char *t5;
169
-    char *t6;
170
-    char *t7;
171
-    unsigned int t8;
172
-    unsigned int t9;
173
-    unsigned char t10;
174
-    char *t11;
175
-    char *t12;
176
-    char *t13;
177
-    char *t14;
178
-    char *t15;
179
-    char *t16;
180
-
181
-LAB0:    xsi_set_current_line(56, ng0);
182
-
183
-LAB3:    t2 = (t0 + 2312U);
184
-    t3 = *((char **)t2);
185
-    t2 = (t0 + 11288U);
186
-    t4 = (t0 + 2472U);
187
-    t5 = *((char **)t4);
188
-    t4 = (t0 + 11304U);
189
-    t6 = ieee_p_3620187407_sub_1496620905533649268_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
190
-    t7 = (t1 + 12U);
191
-    t8 = *((unsigned int *)t7);
192
-    t9 = (1U * t8);
193
-    t10 = (9U != t9);
194
-    if (t10 == 1)
195
-        goto LAB5;
196
-
197
-LAB6:    t11 = (t0 + 7432);
198
-    t12 = (t11 + 56U);
199
-    t13 = *((char **)t12);
200
-    t14 = (t13 + 56U);
201
-    t15 = *((char **)t14);
202
-    memcpy(t15, t6, 9U);
203
-    xsi_driver_first_trans_fast(t11);
204
-
205
-LAB2:    t16 = (t0 + 7096);
206
-    *((int *)t16) = 1;
207
-
208
-LAB1:    return;
209
-LAB4:    goto LAB2;
210
-
211
-LAB5:    xsi_size_not_matching(9U, t9, 0);
212
-    goto LAB6;
213
-
214
-}
215
-
216
-static void work_a_0832606739_3212880686_p_3(char *t0)
217
-{
218
-    char t1[16];
219
-    char *t2;
220
-    char *t3;
221
-    char *t4;
222
-    char *t5;
223
-    char *t6;
224
-    char *t7;
225
-    unsigned int t8;
226
-    unsigned int t9;
227
-    unsigned char t10;
228
-    char *t11;
229
-    char *t12;
230
-    char *t13;
231
-    char *t14;
232
-    char *t15;
233
-    char *t16;
234
-
235
-LAB0:    xsi_set_current_line(57, ng0);
236
-
237
-LAB3:    t2 = (t0 + 2312U);
238
-    t3 = *((char **)t2);
239
-    t2 = (t0 + 11288U);
240
-    t4 = (t0 + 2472U);
241
-    t5 = *((char **)t4);
242
-    t4 = (t0 + 11304U);
243
-    t6 = ieee_p_3620187407_sub_1496620905533721142_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
244
-    t7 = (t1 + 12U);
245
-    t8 = *((unsigned int *)t7);
246
-    t9 = (1U * t8);
247
-    t10 = (9U != t9);
248
-    if (t10 == 1)
249
-        goto LAB5;
250
-
251
-LAB6:    t11 = (t0 + 7496);
252
-    t12 = (t11 + 56U);
253
-    t13 = *((char **)t12);
254
-    t14 = (t13 + 56U);
255
-    t15 = *((char **)t14);
256
-    memcpy(t15, t6, 9U);
257
-    xsi_driver_first_trans_fast(t11);
258
-
259
-LAB2:    t16 = (t0 + 7112);
260
-    *((int *)t16) = 1;
261
-
262
-LAB1:    return;
263
-LAB4:    goto LAB2;
264
-
265
-LAB5:    xsi_size_not_matching(9U, t9, 0);
266
-    goto LAB6;
267
-
268
-}
269
-
270
-static void work_a_0832606739_3212880686_p_4(char *t0)
271
-{
272
-    char t1[16];
273
-    char *t2;
274
-    char *t3;
275
-    char *t4;
276
-    char *t5;
277
-    char *t6;
278
-    char *t7;
279
-    unsigned int t8;
280
-    unsigned int t9;
281
-    unsigned char t10;
282
-    char *t11;
283
-    char *t12;
284
-    char *t13;
285
-    char *t14;
286
-    char *t15;
287
-    char *t16;
288
-
289
-LAB0:    xsi_set_current_line(58, ng0);
290
-
291
-LAB3:    t2 = (t0 + 1032U);
292
-    t3 = *((char **)t2);
293
-    t2 = (t0 + 11224U);
294
-    t4 = (t0 + 1192U);
295
-    t5 = *((char **)t4);
296
-    t4 = (t0 + 11240U);
297
-    t6 = ieee_p_3620187407_sub_1496620905533613331_3965413181(IEEE_P_3620187407, t1, t3, t2, t5, t4);
298
-    t7 = (t1 + 12U);
299
-    t8 = *((unsigned int *)t7);
300
-    t9 = (1U * t8);
301
-    t10 = (16U != t9);
302
-    if (t10 == 1)
303
-        goto LAB5;
304
-
305
-LAB6:    t11 = (t0 + 7560);
306
-    t12 = (t11 + 56U);
307
-    t13 = *((char **)t12);
308
-    t14 = (t13 + 56U);
309
-    t15 = *((char **)t14);
310
-    memcpy(t15, t6, 16U);
311
-    xsi_driver_first_trans_fast(t11);
312
-
313
-LAB2:    t16 = (t0 + 7128);
314
-    *((int *)t16) = 1;
315
-
316
-LAB1:    return;
317
-LAB4:    goto LAB2;
318
-
319
-LAB5:    xsi_size_not_matching(16U, t9, 0);
320
-    goto LAB6;
321
-
322
-}
323
-
324
-static void work_a_0832606739_3212880686_p_5(char *t0)
325
-{
326
-    char t5[16];
327
-    char t23[16];
328
-    char t41[16];
329
-    char *t1;
330
-    char *t2;
331
-    char *t3;
332
-    char *t6;
333
-    char *t7;
334
-    int t8;
335
-    unsigned int t9;
336
-    unsigned char t10;
337
-    char *t11;
338
-    unsigned int t12;
339
-    unsigned int t13;
340
-    char *t14;
341
-    char *t15;
342
-    char *t16;
343
-    char *t17;
344
-    char *t18;
345
-    char *t19;
346
-    char *t20;
347
-    char *t21;
348
-    char *t24;
349
-    char *t25;
350
-    int t26;
351
-    unsigned int t27;
352
-    unsigned char t28;
353
-    char *t29;
354
-    unsigned int t30;
355
-    unsigned int t31;
356
-    char *t32;
357
-    char *t33;
358
-    char *t34;
359
-    char *t35;
360
-    char *t36;
361
-    char *t37;
362
-    char *t38;
363
-    char *t39;
364
-    char *t42;
365
-    char *t43;
366
-    int t44;
367
-    unsigned int t45;
368
-    unsigned char t46;
369
-    char *t47;
370
-    unsigned int t48;
371
-    unsigned int t49;
372
-    char *t50;
373
-    char *t51;
374
-    char *t52;
375
-    char *t53;
376
-    char *t54;
377
-    char *t55;
378
-    char *t56;
379
-    char *t57;
380
-    char *t58;
381
-    char *t59;
382
-    char *t60;
383
-    char *t61;
384
-    char *t62;
385
-
386
-LAB0:    xsi_set_current_line(60, ng0);
387
-    t1 = (t0 + 1352U);
388
-    t2 = *((char **)t1);
389
-    t1 = (t0 + 11256U);
390
-    t3 = (t0 + 11473);
391
-    t6 = (t5 + 0U);
392
-    t7 = (t6 + 0U);
393
-    *((int *)t7) = 0;
394
-    t7 = (t6 + 4U);
395
-    *((int *)t7) = 1;
396
-    t7 = (t6 + 8U);
397
-    *((int *)t7) = 1;
398
-    t8 = (1 - 0);
399
-    t9 = (t8 * 1);
400
-    t9 = (t9 + 1);
401
-    t7 = (t6 + 12U);
402
-    *((unsigned int *)t7) = t9;
403
-    t10 = ieee_std_logic_unsigned_equal_stdv_stdv(IEEE_P_3620187407, t2, t1, t3, t5);
404
-    if (t10 != 0)
405
-        goto LAB3;
406
-
407
-LAB4:    t19 = (t0 + 1352U);
408
-    t20 = *((char **)t19);
409
-    t19 = (t0 + 11256U);
410
-    t21 = (t0 + 11475);
411
-    t24 = (t23 + 0U);
412
-    t25 = (t24 + 0U);
413
-    *((int *)t25) = 0;
414
-    t25 = (t24 + 4U);
415
-    *((int *)t25) = 1;
416
-    t25 = (t24 + 8U);
417
-    *((int *)t25) = 1;
418
-    t26 = (1 - 0);
419