Yohan Simard ysimard
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  • Joined on 2019-02-14
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ysimard pushed to master at vergnet/clavardator 2020-12-05 00:30:40 +01:00
0e8ded05c9 Put id in User, async create and init ActiveUser, make CurrentUser singleton
ysimard pushed to master at ysimard/projet_voilier 2020-12-03 12:16:23 +01:00
64ea0cbd78 accelerometer and display fix
ysimard pushed to master at vergnet/clavardator 2020-12-02 19:06:01 +01:00
b75cd6de1a Add ConnectionListener + improve network classes + first work on username change impl
ysimard pushed to master at vergnet/clavardator 2020-12-02 12:02:39 +01:00
613e580b4c Implement send and receive messages + rework async error handling
ysimard pushed to master at vergnet/clavardator 2020-12-02 10:53:22 +01:00
415b477ef8 Make user comparable
ysimard pushed to master at vergnet/clavardator 2020-12-02 10:51:30 +01:00
ef8fd4d00c Make user comparable
ysimard pushed to master at vergnet/clavardator 2020-12-02 10:14:43 +01:00
1a5a62f11f Add message parameters to discovery method, and add close method
ysimard pushed to master at vergnet/clavardator 2020-11-30 18:18:39 +01:00
ab5b058498 Implement network discovery methods (working)
ysimard pushed to master at vergnet/clavardator 2020-11-26 16:19:05 +01:00
659bdd10ec Convert to beans, start implementing functions and rewrite net architecture
ysimard pushed to master at vergnet/clavardator 2020-11-23 16:28:10 +01:00
ff0be945cd Create project skeleton from UML class diagram
ysimard pushed to master at ysimard/projet_voilier 2020-11-16 20:25:14 +01:00
c8ea3f3a91 clean project
f7406c3301 clean project
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ysimard pushed to master at ysimard/projet_voilier 2020-11-16 19:43:14 +01:00
f7406c3301 clean project
542722584d Merge branch 'reel'
599b7f7c6b fix many bugs (work done during lab session)
Compare 3 commits »
ysimard pushed to reel at ysimard/projet_voilier 2020-11-16 18:42:23 +01:00
599b7f7c6b fix many bugs (work done during lab session)
ysimard pushed to master at ysimard/projet_voilier 2020-11-14 18:00:33 +01:00
e1773afbbe fix bugs and more...
ysimard pushed to YA at ysimard/projet_voilier 2020-11-09 12:15:01 +01:00
76fd320df4 implement ADC and USART
ysimard pushed to master at ysimard/projet_voilier 2020-10-13 18:02:59 +02:00
1113fd6594 Add header files
ysimard pushed to master at ysimard/projet_voilier 2020-10-13 17:42:54 +02:00
f8301a6a42 Import projet de base
ysimard created repository ysimard/projet_voilier 2020-10-13 17:12:02 +02:00
ysimard pushed to master at vergnet/be_info_mat 2020-09-21 14:18:04 +02:00
097e893f71 fin de l'activité 1
ysimard pushed to master at vergnet/be_info_mat 2020-09-18 11:02:49 +02:00
51958dab3e Réalisation timer + début intégration interruptions