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Yohan Simard 2020-10-13 17:42:25 +02:00
parent ec9271d44a
commit f8301a6a42
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/
!/README.md
!/Src/
!/Services/
!/MyDrivers/
!/LLDrivers/
!/MDK-ARM/startup_stm32f103xb.s
!/MDK-ARM/startup_stm32f103xb.s
!/MDK-ARM/NUCLEO-F103RB/
!/MDK-ARM/RTE/
!/MDK-ARM/Project.uvoptx
!/MDK-ARM/Project.uvprojx
!/Inc
!/.gitignore

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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx.h
* @author MCD Application Team
* @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F1xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx
* @{
*/
#ifndef __STM32F1XX_H
#define __STM32F1XX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F1)
#define STM32F1
#endif /* STM32F1 */
/* Uncomment the line below according to the target STM32L device used in your
application
*/
#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
!defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
!defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
/* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
/* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
/* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
/* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
/* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
/* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
/* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
/* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
/* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
/* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
/* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
/* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
/* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
/* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V4.3.1
*/
#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
#define __STM32F1_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F1_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
|(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F1_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F100xB)
#include "stm32f100xb.h"
#elif defined(STM32F100xE)
#include "stm32f100xe.h"
#elif defined(STM32F101x6)
#include "stm32f101x6.h"
#elif defined(STM32F101xB)
#include "stm32f101xb.h"
#elif defined(STM32F101xE)
#include "stm32f101xe.h"
#elif defined(STM32F101xG)
#include "stm32f101xg.h"
#elif defined(STM32F102x6)
#include "stm32f102x6.h"
#elif defined(STM32F102xB)
#include "stm32f102xb.h"
#elif defined(STM32F103x6)
#include "stm32f103x6.h"
#elif defined(STM32F103xB)
#include "stm32f103xb.h"
#elif defined(STM32F103xE)
#include "stm32f103xe.h"
#elif defined(STM32F103xG)
#include "stm32f103xg.h"
#elif defined(STM32F105xC)
#include "stm32f105xc.h"
#elif defined(STM32F107xC)
#include "stm32f107xc.h"
#else
#error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f1xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F1xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file Examples_LL/GPIO/GPIO_InfiniteLedToggling/Inc/stm32f1xx_it.h
* @author MCD Application Team
* @brief This file contains the headers of the interrupt handlers.
* !! modif : include main.h enlevé
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_IT_H
#define __STM32F1xx_IT_H
#ifdef __cplusplus
extern "C" {
#endif
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f10x.h
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F10X_H
#define __SYSTEM_STM32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F10X_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(MPU services provided only on some devices)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_CORTEX_H
#define __STM32F1xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M3 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC23 for Cortex-M3
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_CRC_H
#define STM32F1xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_exti.h
* @author MCD Application Team
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_EXTI_H
#define STM32F1xx_LL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private Macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
* @{
*/
typedef struct
{
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
} LL_EXTI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_LL_EC_LINE LINE
* @{
*/
#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
#if defined(EXTI_IMR_IM16)
#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
#endif
#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
#if defined(EXTI_IMR_IM18)
#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
#endif
#if defined(EXTI_IMR_IM19)
#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
#endif
#if defined(EXTI_IMR_IM20)
#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
#endif
#if defined(EXTI_IMR_IM21)
#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
#endif
#if defined(EXTI_IMR_IM22)
#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
#endif
#if defined(EXTI_IMR_IM23)
#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
#endif
#if defined(EXTI_IMR_IM24)
#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
#endif
#if defined(EXTI_IMR_IM25)
#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
#endif
#if defined(EXTI_IMR_IM26)
#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
#endif
#if defined(EXTI_IMR_IM27)
#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
#endif
#if defined(EXTI_IMR_IM28)
#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
#endif
#if defined(EXTI_IMR_IM29)
#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
#endif
#if defined(EXTI_IMR_IM30)
#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
#endif
#if defined(EXTI_IMR_IM31)
#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
#endif
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EC_MODE Mode
* @{
*/
#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
/**
* @}
*/
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
* @{
*/
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
* @{
*/
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in EXTI register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
/**
* @brief Read a value in EXTI register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
* @{
*/
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR, ExtiLine);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
* @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR, ExtiLine);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
* @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
* @{
*/
/**
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
* @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
* register (by writing a 1 into the bit)
* @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
* @{
*/
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
}
/**
* @brief Clear ExtLine Flags for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->PR, ExtiLine);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
uint32_t LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* EXTI */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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LLDrivers/inc/stm32f1xx_ll_fsmc.h Normal file
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@ -0,0 +1,951 @@
/**
******************************************************************************
* @file stm32f1xx_ll_fsmc.h
* @author MCD Application Team
* @brief Header file of FSMC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_FSMC_H
#define STM32F1xx_LL_FSMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup FSMC_LL
* @{
*/
/** @addtogroup FSMC_LL_Private_Macros
* @{
*/
#if defined FSMC_BANK1
#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
((__BANK__) == FSMC_NORSRAM_BANK2) || \
((__BANK__) == FSMC_NORSRAM_BANK3) || \
((__BANK__) == FSMC_NORSRAM_BANK4))
#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FSMC_PAGE_SIZE_128) || \
((__SIZE__) == FSMC_PAGE_SIZE_256) || \
((__SIZE__) == FSMC_PAGE_SIZE_512) || \
((__SIZE__) == FSMC_PAGE_SIZE_1024))
#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
((__MODE__) == FSMC_ACCESS_MODE_B) || \
((__MODE__) == FSMC_ACCESS_MODE_C) || \
((__MODE__) == FSMC_ACCESS_MODE_D))
#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
((__MODE__) == FSMC_WRAP_MODE_ENABLE))
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FSMC_WRITE_BURST_ENABLE))
#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3)
#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
((__STATE__) == FSMC_NAND_ECC_ENABLE))
#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
#endif /* FSMC_BANK4 */
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types
* @{
*/
#if defined FSMC_BANK1
#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
#endif /* FSMC_BANK4 */
#if defined FSMC_BANK1
#define FSMC_NORSRAM_DEVICE FSMC_Bank1
#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
#define FSMC_NAND_DEVICE FSMC_Bank2_3
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
#define FSMC_PCCARD_DEVICE FSMC_Bank4
#endif /* FSMC_BANK4 */
#if defined FSMC_BANK1
/**
* @brief FSMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FSMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FSMC_Wrap_Mode */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FSMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
This parameter can be a value of @ref FSMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FSMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FSMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FSMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FSMC_Write_Burst */
uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FSMC_Page_Size */
}FSMC_NORSRAM_InitTypeDef;
/**
* @brief FSMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FSMC_Access_Mode */
}FSMC_NORSRAM_TimingTypeDef;
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/**
* @brief FSMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
This parameter can be a value of @ref FSMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FSMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FSMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FSMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FSMC_NAND_InitTypeDef;
#endif
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
/**
* @brief FSMC NAND Timing parameters structure definition
*/
typedef struct
{
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
}FSMC_NAND_PCC_TimingTypeDef;
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/**
* @brief FSMC PCCARD Configuration Structure definition
*/
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FSMC_Wait_feature */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FSMC_PCCARD_InitTypeDef;
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants
* @{
*/
#if defined FSMC_BANK1
/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
* @{
*/
/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
* @{
*/
#define FSMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
#define FSMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
#define FSMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
#define FSMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
/**
* @}
*/
/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
* @{
*/
#define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup FSMC_Memory_Type FSMC Memory Type
* @{
*/
#define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
#define FSMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
/**
* @}
*/
/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width
* @{
*/
#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
/**
* @}
*/
/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
* @{
*/
#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
* @{
*/
#define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
* @{
*/
#define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
/**
* @}
*/
/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
* @{
*/
#define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
#define FSMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
* @{
*/
#define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
/**
* @}
*/
/** @defgroup FSMC_Write_Operation FSMC Write Operation
* @{
*/
#define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
/**
* @}
*/
/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
* @{
*/
#define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
/**
* @}
*/
/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
* @{
*/
#define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
/**
* @}
*/
/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
* @{
*/
#define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
/**
* @}
*/
/** @defgroup FSMC_Page_Size FSMC Page Size
* @{
*/
#define FSMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
#define FSMC_PAGE_SIZE_128 ((uint32_t)0x00010000U)
#define FSMC_PAGE_SIZE_256 ((uint32_t)0x00020000U)
#define FSMC_PAGE_SIZE_512 ((uint32_t)0x00030000U)
#define FSMC_PAGE_SIZE_1024 ((uint32_t)0x00040000U)
/**
* @}
*/
/** @defgroup FSMC_Write_Burst FSMC Write Burst
* @{
*/
#define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
#define FSMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
/**
* @}
*/
/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock
* @{
*/
#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
/**
* @}
*/
/** @defgroup FSMC_Access_Mode FSMC Access Mode
* @{
*/
#define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
#define FSMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
#define FSMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
#define FSMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller
* @{
*/
/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
* @{
*/
#define FSMC_NAND_BANK2 ((uint32_t)0x00000010U)
#define FSMC_NAND_BANK3 ((uint32_t)0x00000100U)
/**
* @}
*/
/** @defgroup FSMC_Wait_feature FSMC Wait feature
* @{
*/
#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
* @{
*/
#if defined(FSMC_BANK4)
#define FSMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
#endif
#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
/**
* @}
*/
/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
* @{
*/
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
/**
* @}
*/
/** @defgroup FSMC_ECC FSMC ECC
* @{
*/
#define FSMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
#define FSMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
/**
* @}
*/
/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
* @{
*/
#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK3 */
/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition
* @{
*/
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
#define FSMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
#define FSMC_IT_LEVEL ((uint32_t)0x00000010U)
#define FSMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
#endif /* FSMC_BANK3 */
/**
* @}
*/
/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition
* @{
*/
#if defined(FSMC_BANK3)||defined(FSMC_BANK4)
#define FSMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
#define FSMC_FLAG_LEVEL ((uint32_t)0x00000002U)
#define FSMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040U)
#endif /* FSMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros
* @{
*/
#if defined FSMC_BANK1
/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FSMC_NORSRAM Instance
* @param __BANK__ FSMC_NORSRAM Bank
* @retval None
*/
#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FSMC_NORSRAM Instance
* @param __BANK__ FSMC_NORSRAM Bank
* @retval None
*/
#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \
((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @retval None
*/
#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
/**
* @}
*/
#endif
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN)
/**
* @brief Disable the PCCARD device access.
* @param __INSTANCE__ FSMC_PCCARD Instance
* @retval None
*/
#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN)
/**
* @}
*/
#endif
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
*/
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FSMC_NAND instance
* @param __BANK__ FSMC_NAND Bank
* @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __INTERRUPT__ FSMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FSMC_NAND Instance
* @param __BANK__ FSMC_NAND Bank
* @param __FLAG__ FSMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt
* @brief macros to handle PCCARD interrupts
* @{
*/
/**
* @brief Enable the PCCARD device interrupt.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __INTERRUPT__ FSMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FSMC_IT_LEVEL: Interrupt level.
* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
* @param __INSTANCE__ FSMC_PCCARD instance
* @param __FLAG__ FSMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
* @{
*/
#if defined FSMC_BANK1
/** @defgroup FSMC_LL_NORSRAM NOR SRAM
* @{
*/
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_NAND NAND
* @{
*/
/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
* @{
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @defgroup FSMC_LL_PCCARD PCCARD
* @{
*/
/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK4 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_FSMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_IWDG_H
#define STM32F1xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
return (uint32_t)(READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
return (uint32_t)(READ_REG(IWDGx->RLR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
}
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_PWR_H
#define __STM32F1xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
* @{
*/
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
/**
* @}
*/
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
* @{
*/
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
* @{
*/
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
* @{
*/
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in PWR register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable access to the backup domain
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Disable access to the backup domain
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Check if the backup domain is enabled
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
}
/**
* @brief Set voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
* @param RegulMode This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
{
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
}
/**
* @brief Get voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
}
/**
* @brief Set Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
* @rmtoll CR LPDS LL_PWR_SetPowerMode
* @param PDMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
{
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
}
/**
* @brief Get Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
* @rmtoll CR LPDS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
}
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector
* @rmtoll CR PLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
}
/**
* @brief Get the voltage threshold detection
* @rmtoll CR PLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
}
/**
* @brief Enable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Disable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Check if Power Voltage Detector is enabled
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
}
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Disable the WakeUp PINx functionality
* @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Check if the WakeUp PINx functionality is enabled
* @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Wake-up Flag
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
}
/**
* @brief Get Standby Flag
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
}
/**
* @brief Indicate whether VDD voltage is below the selected PVD threshold
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
}
/**
* @brief Clear Standby Flag
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
SET_BIT(PWR->CR, PWR_CR_CSBF);
}
/**
* @brief Clear Wake-up Flags
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
SET_BIT(PWR->CR, PWR_CR_CWUF);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_SYSTEM_H
#define __STM32F1xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (DBGMCU)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM5_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM5_STOP */
#if defined(DBGMCU_CR_DBG_TIM6_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM6_STOP */
#if defined(DBGMCU_CR_DBG_TIM7_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM7_STOP */
#if defined(DBGMCU_CR_DBG_TIM12_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM12_STOP */
#if defined(DBGMCU_CR_DBG_TIM13_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM13_STOP */
#if defined(DBGMCU_CR_DBG_TIM14_STOP)
#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM14_STOP */
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_CR_DBG_CAN1_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_CAN2_STOP)
#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
#endif /* DBGMCU_CR_DBG_CAN2_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
#if defined(DBGMCU_CR_DBG_TIM8_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_CAN1_STOP */
#if defined(DBGMCU_CR_DBG_TIM9_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM9_STOP */
#if defined(DBGMCU_CR_DBG_TIM10_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM10_STOP */
#if defined(DBGMCU_CR_DBG_TIM11_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM11_STOP */
#if defined(DBGMCU_CR_DBG_TIM15_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM15_STOP */
#if defined(DBGMCU_CR_DBG_TIM16_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM16_STOP */
#if defined(DBGMCU_CR_DBG_TIM17_STOP)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
#endif /* DBGMCU_CR_DBG_TIM17_STOP */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#if defined(FLASH_ACR_LATENCY)
#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
#else
#endif /* FLASH_ACR_LATENCY */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @note For Low Density devices, the device ID is 0x412
* @note For Medium Density devices, the device ID is 0x410
* @note For High Density devices, the device ID is 0x414
* @note For XL Density devices, the device ID is 0x430
* @note For Connectivity Line devices, the device ID is 0x418
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
For example, it is read as revA -> 0x1000,for Low Density devices
For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
For example, it is read as revA or 1 -> 0x1003,for XL Density devices
For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->CR, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->CR, Periphs);
}
/**
* @}
*/
#if defined(FLASH_ACR_LATENCY)
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Disable Prefetch
* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
}
/**
* @brief Check if Prefetch buffer is enabled
* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Enable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Disable Flash Half Cycle Access
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
}
/**
* @brief Check if Flash Half Cycle Access is enabled or not
* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
{
return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FLASH) || defined (DBGMCU) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_SYSTEM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_USB_H
#define STM32F1xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal_def.h"
#if defined (USB) || defined (USB_OTG_FS)
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
#if defined (USB_OTG_FS)
typedef enum
{
USB_DEVICE_MODE = 0,
USB_HOST_MODE = 1,
USB_DRD_MODE = 2
} USB_ModeTypeDef;
/**
* @brief URB States definition
*/
typedef enum
{
URB_IDLE = 0,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
} USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
typedef enum
{
HC_IDLE = 0,
HC_XFRC,
HC_HALTED,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
} USB_OTG_HCStateTypeDef;
/**
* @brief USB OTG Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY_ */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
} USB_OTG_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type_ */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_OTG_EPTypeDef;
typedef struct
{
uint8_t dev_addr ; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_num; /*!< Endpoint number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_EP_Type_ */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t data_pid; /*!< Initial data PID.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
uint8_t toggle_in; /*!< IN transfer current toggle flag.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t toggle_out; /*!< OUT transfer current toggle flag
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
} USB_OTG_HCTypeDef;
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
} USB_EPTypeDef;
#endif /* defined (USB) */
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
#if defined (USB_OTG_FS)
/** @defgroup USB_OTG_CORE VERSION ID
* @{
*/
#define USB_OTG_CORE_ID_300A 0x4F54300AU
#define USB_OTG_CORE_ID_310A 0x4F54310AU
/**
* @}
*/
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
#define USBH_FS_SPEED 1U
/**
* @}
*/
/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
* @{
*/
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1U
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
*/
/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#define USBD_DEFAULT_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
* @{
*/
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1)
/**
* @}
*/
/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3U
/**
* @}
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 2U
#endif /* defined (USB) */
#if defined (USB_OTG_FS)
#define EP_ADDR_MSK 0xFU
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
#define EP_ADDR_MSK 0x7U
#endif /* defined (USB) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
* @{
*/
#if defined (USB_OTG_FS)
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
#endif /* defined (USB_OTG_FS) */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
#if defined (USB_OTG_FS)
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
#endif /* defined (USB_OTG_FS) */
#if defined (USB)
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
#endif /* defined (USB) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) || defined (USB_OTG_FS) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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LLDrivers/inc/stm32f1xx_ll_utils.h Normal file
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@ -0,0 +1,266 @@
/**
******************************************************************************
* @file stm32f1xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_LL_UTILS_H
#define __STM32F1xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F1xx_LL_UTILS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F1xx_LL_WWDG_H
#define STM32F1xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (WWDG)
/** @defgroup WWDG_LL WWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
* @{
*/
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
* then it cannot be disabled again except by a reset.
* This bit is set by software and only cleared by hardware after a reset.
* When WDGA = 1, the watchdog can generate a reset.
* @rmtoll CR WDGA LL_WWDG_Enable
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
}
/**
* @brief Checks if Window Watchdog is enabled
* @rmtoll CR WDGA LL_WWDG_IsEnabled
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
* @rmtoll CR T LL_WWDG_SetCounter
* @param WWDGx WWDG Instance
* @param Counter 0..0x7F (7 bit counter value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
{
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
}
/**
* @brief Return current Watchdog Counter Value (7 bits counter value)
* @rmtoll CR T LL_WWDG_GetCounter
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
* @brief Set the time base of the prescaler (WDGTB).
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
* is decremented every (4096 x 2expWDGTB) PCLK cycles
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
* @param WWDGx WWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
}
/**
* @brief Return current Watchdog Prescaler Value
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
* @param WWDGx WWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
* @note This window value defines when write in the WWDG_CR register
* to program Watchdog counter is allowed.
* Watchdog counter value update must occur only when the counter value
* is lower than the Watchdog window register value.
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
* (in the control register) is refreshed before the downcounter has reached
* the watchdog window register value.
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
* @rmtoll CFR W LL_WWDG_SetWindow
* @param WWDGx WWDG Instance
* @param Window 0x00..0x7F (7 bit Window value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
}
/**
* @brief Return current Watchdog Window Value (7 bits value)
* @rmtoll CFR W LL_WWDG_GetWindow
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
* @note This bit is set by hardware when the counter has reached the value 0x40.
* It must be cleared by software by writing 0.
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Early Wakeup Interrupt.
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
* This interrupt is only cleared by hardware after a reset
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
}
/**
* @brief Check if Early Wakeup Interrupt is enabled
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* WWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F1xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_adc.c
* @author MCD Application Team
* @brief ADC LL module driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_adc.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (ADC1) || defined (ADC2) || defined (ADC3)
/** @addtogroup ADC_LL ADC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup ADC_LL_Private_Macros
* @{
*/
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#if defined(ADC3)
#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
) \
: \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
) \
)
#else
#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
)
#else
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
#endif
#endif
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#if defined(ADC3)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
) \
: \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
) \
)
#else
#if defined (STM32F101xE) || defined (STM32F105xC) || defined (STM32F107xC)
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
)
#else
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
)
#endif
#endif
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
#if defined(ADC_MULTIMODE_SUPPORT)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_FAST) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL_SLOW) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM) \
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_LL_Exported_Functions
* @{
*/
/** @addtogroup ADC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize registers of all ADC instances belonging to
* the same ADC common instance to their default reset values.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
{
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1);
/* Release reset of ADC clock (core clock) */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
return SUCCESS;
}
/**
* @brief Initialize some features of ADC common parameters
* (all ADC instances belonging to the same ADC common instance)
* and multimode (for devices with several ADC instances available).
* @note The setting of ADC common parameters is conditioned to
* ADC instances state:
* All ADC instances belonging to the same ADC common instance
* must be disabled.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are initialized
* - ERROR: ADC common registers are not initialized
*/
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
#if defined(ADC_MULTIMODE_SUPPORT)
assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
#endif /* ADC_MULTIMODE_SUPPORT */
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
/* On this STM32 serie, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - common to several ADC */
/* (all ADC instances belonging to the same ADC common instance) */
/* - multimode (if several ADC instances available on the */
/* selected device) */
/* - Set ADC multimode configuration */
/* - Set ADC multimode DMA transfer */
/* - Set ADC multimode: delay between 2 sampling phases */
#if defined(ADC_MULTIMODE_SUPPORT)
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
{
MODIFY_REG(ADCxy_COMMON->CR1,
ADC_CR1_DUALMOD,
ADC_CommonInitStruct->Multimode
);
}
else
{
MODIFY_REG(ADCxy_COMMON->CR1,
ADC_CR1_DUALMOD,
LL_ADC_MULTI_INDEPENDENT
);
}
#endif
}
else
{
/* Initialization error: One or several ADC instances belonging to */
/* the same ADC common instance are not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
#if defined(ADC_MULTIMODE_SUPPORT)
/* Set fields of ADC multimode */
ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
#endif /* ADC_MULTIMODE_SUPPORT */
}
/**
* @brief De-initialize registers of the selected ADC instance
* to their default reset values.
* @note To reset all ADC instances quickly (perform a hard reset),
* use function @ref LL_ADC_CommonDeInit().
* @param ADCx ADC instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are de-initialized
* - ERROR: ADC registers are not de-initialized
*/
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
/* Disable ADC instance if not already disabled. */
if(LL_ADC_IsEnabled(ADCx) == 1U)
{
/* Set ADC group regular trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
}
/* Check whether ADC state is compliant with expected state */
/* (hardware requirements of bits state to reset registers below) */
if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
{
/* ========== Reset ADC registers ========== */
/* Reset register SR */
CLEAR_BIT(ADCx->SR,
( LL_ADC_FLAG_STRT
| LL_ADC_FLAG_JSTRT
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_AWD1 )
);
/* Reset register CR1 */
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
CLEAR_BIT(ADCx->CR1,
( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DUALMOD
| ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
| ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
| ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
| ADC_CR1_AWDCH )
);
#else
CLEAR_BIT(ADCx->CR1,
( ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM
| ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO
| ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE
| ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH )
);
#endif
/* Reset register CR2 */
CLEAR_BIT(ADCx->CR2,
( ADC_CR2_TSVREFE
| ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
| ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
| ADC_CR2_ALIGN | ADC_CR2_DMA
| ADC_CR2_RSTCAL | ADC_CR2_CAL
| ADC_CR2_CONT | ADC_CR2_ADON )
);
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
| ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
| ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
);
/* Reset register SMPR2 */
CLEAR_BIT(ADCx->SMPR2,
( ADC_SMPR2_SMP9
| ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
| ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
| ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
);
/* Reset register JOFR1 */
CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
/* Reset register JOFR2 */
CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
/* Reset register JOFR3 */
CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
/* Reset register JOFR4 */
CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
/* Reset register HTR */
SET_BIT(ADCx->HTR, ADC_HTR_HT);
/* Reset register LTR */
CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
/* Reset register SQR1 */
CLEAR_BIT(ADCx->SQR1,
( ADC_SQR1_L
| ADC_SQR1_SQ16
| ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
);
/* Reset register SQR2 */
CLEAR_BIT(ADCx->SQR2,
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
);
/* Reset register JSQR */
CLEAR_BIT(ADCx->JSQR,
( ADC_JSQR_JL
| ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
| ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
/* bits in access mode read only, no direct reset applicable */
}
return status;
}
/**
* @brief Initialize some features of ADC instance.
* @note These parameters have an impact on ADC scope: ADC instance.
* Affects both group regular and group injected (availability
* of ADC group injected depends on STM32 families).
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Instance .
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, some other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC instance */
/* - Set ADC conversion data alignment */
MODIFY_REG(ADCx->CR1,
ADC_CR1_SCAN
,
ADC_InitStruct->SequencersScanMode
);
MODIFY_REG(ADCx->CR2,
ADC_CR2_ALIGN
,
ADC_InitStruct->DataAlignment
);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
/* Enable scan mode to have a generic behavior with ADC of other */
/* STM32 families, without this setting available: */
/* ADC group regular sequencer and ADC group injected sequencer depend */
/* only of their own configuration. */
ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
}
/**
* @brief Initialize some features of ADC group regular.
* @note These parameters have an impact on ADC scope: ADC group regular.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "REG").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
#if defined(ADC3)
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
#else
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
#endif
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group regular */
/* - Set ADC group regular trigger source */
/* - Set ADC group regular sequencer length */
/* - Set ADC group regular sequencer discontinuous mode */
/* - Set ADC group regular continuous mode */
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| ADC_REG_InitStruct->SequencerDiscont
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| LL_ADC_REG_SEQ_DISCONT_DISABLE
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_EXTSEL
| ADC_CR2_CONT
| ADC_CR2_DMA
,
ADC_REG_InitStruct->TriggerSource
| ADC_REG_InitStruct->ContinuousMode
| ADC_REG_InitStruct->DMATransfer
);
/* Set ADC group regular sequencer length and scan direction */
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
}
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "INJ").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
#if defined(ADC3)
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
#else
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
#endif
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group injected */
/* - Set ADC group injected trigger source */
/* - Set ADC group injected sequencer length */
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
ADC_INJ_InitStruct->SequencerDiscont
| ADC_INJ_InitStruct->TrigAuto
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
LL_ADC_REG_SEQ_DISCONT_DISABLE
| ADC_INJ_InitStruct->TrigAuto
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_JEXTSEL
,
ADC_INJ_InitStruct->TriggerSource
);
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
/* Set ADC_INJ_InitStruct fields to default values */
/* Set fields of ADC group injected */
ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ADC1 || ADC2 || ADC3 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_crc.c
* @author MCD Application Team
* @brief CRC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_crc.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (CRC)
/** @addtogroup CRC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_LL_Exported_Functions
* @{
*/
/** @addtogroup CRC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize CRC registers (Registers restored to their default values).
* @param CRCx CRC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
if (CRCx == CRC)
{
/* Reset the CRC calculation unit */
LL_CRC_ResetCRCCalculationUnit(CRCx);
/* Reset IDR register */
LL_CRC_Write_IDR(CRCx, 0x00U);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (CRC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_dac.c
* @author MCD Application Team
* @brief DAC LL module driver
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_dac.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(DAC)
/** @addtogroup DAC_LL DAC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DAC_LL_Private_Macros
* @{
*/
#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \
( \
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|| ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM3_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM15_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \
( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
&& ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \
) \
||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
&& ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \
) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
|| ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_LL_Exported_Functions
* @{
*/
/** @addtogroup DAC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize registers of the selected DAC instance
* to their default reset values.
* @param DACx DAC instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DAC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
/* Force reset of DAC clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
/* Release reset of DAC clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
return SUCCESS;
}
/**
* @brief Initialize some features of DAC channel.
* @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel.
* Leaving it ready to be enabled and output:
* a level by calling one of
* @ref LL_DAC_ConvertData12RightAligned
* @ref LL_DAC_ConvertData12LeftAligned
* @ref LL_DAC_ConvertData8RightAligned
* or one of the supported autogenerated wave.
* @note This function allows configuration of:
* - Output mode
* - Trigger
* - Wave generation
* @note The setting of these parameters by function @ref LL_DAC_Init()
* is conditioned to DAC state:
* DAC channel must be disabled.
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DAC registers are initialized
* - ERROR: DAC registers are not initialized
*/
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
assert_param(IS_LL_DAC_CHANNEL(DAC_Channel));
assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
{
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration,
DAC_InitStruct->WaveAutoGenerationConfig));
}
/* Note: Hardware constraint (refer to description of this function) */
/* DAC instance must be disabled. */
if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
{
/* Configuration of DAC channel: */
/* - TriggerSource */
/* - WaveAutoGeneration */
/* - OutputBuffer */
/* - OutputMode */
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
{
MODIFY_REG(DACx->CR,
(DAC_CR_TSEL1
| DAC_CR_WAVE1
| DAC_CR_MAMP1
| DAC_CR_BOFF1
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
,
(DAC_InitStruct->TriggerSource
| DAC_InitStruct->WaveAutoGeneration
| DAC_InitStruct->WaveAutoGenerationConfig
| DAC_InitStruct->OutputBuffer
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
else
{
MODIFY_REG(DACx->CR,
(DAC_CR_TSEL1
| DAC_CR_WAVE1
| DAC_CR_BOFF1
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
,
(DAC_InitStruct->TriggerSource
| LL_DAC_WAVE_AUTO_GENERATION_NONE
| DAC_InitStruct->OutputBuffer
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
}
else
{
/* Initialization error: DAC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_DAC_InitTypeDef field to default value.
* @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
{
/* Set DAC_InitStruct fields to default values */
DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
/* Note: Parameter discarded if wave auto generation is disabled, */
/* set anyway to its default value. */
DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_dma.c
* @author MCD Application Team
* @brief DMA LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_dma.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
((__VALUE__) == LL_DMA_MODE_CIRCULAR))
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
#if defined (DMA2)
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5) || \
((CHANNEL) == LL_DMA_CHANNEL_6) || \
((CHANNEL) == LL_DMA_CHANNEL_7))) || \
(((INSTANCE) == DMA2) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5))))
#else
#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
(((CHANNEL) == LL_DMA_CHANNEL_1) || \
((CHANNEL) == LL_DMA_CHANNEL_2) || \
((CHANNEL) == LL_DMA_CHANNEL_3) || \
((CHANNEL) == LL_DMA_CHANNEL_4) || \
((CHANNEL) == LL_DMA_CHANNEL_5) || \
((CHANNEL) == LL_DMA_CHANNEL_6) || \
((CHANNEL) == LL_DMA_CHANNEL_7))))
#endif
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the DMA registers to their default reset values.
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
*/
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
{
DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
ErrorStatus status = SUCCESS;
/* Check the DMA Instance DMAx and Channel parameters*/
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
/* Disable the selected DMAx_Channely */
CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
/* Reset DMAx_Channely control register */
LL_DMA_WriteReg(tmp, CCR, 0U);
/* Reset DMAx_Channely remaining bytes register */
LL_DMA_WriteReg(tmp, CNDTR, 0U);
/* Reset DMAx_Channely peripheral address register */
LL_DMA_WriteReg(tmp, CPAR, 0U);
/* Reset DMAx_Channely memory address register */
LL_DMA_WriteReg(tmp, CMAR, 0U);
if (Channel == LL_DMA_CHANNEL_1)
{
/* Reset interrupt pending bits for DMAx Channel1 */
LL_DMA_ClearFlag_GI1(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_2)
{
/* Reset interrupt pending bits for DMAx Channel2 */
LL_DMA_ClearFlag_GI2(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_3)
{
/* Reset interrupt pending bits for DMAx Channel3 */
LL_DMA_ClearFlag_GI3(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_4)
{
/* Reset interrupt pending bits for DMAx Channel4 */
LL_DMA_ClearFlag_GI4(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_5)
{
/* Reset interrupt pending bits for DMAx Channel5 */
LL_DMA_ClearFlag_GI5(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_6)
{
/* Reset interrupt pending bits for DMAx Channel6 */
LL_DMA_ClearFlag_GI6(DMAx);
}
else if (Channel == LL_DMA_CHANNEL_7)
{
/* Reset interrupt pending bits for DMAx Channel7 */
LL_DMA_ClearFlag_GI7(DMAx);
}
else
{
status = ERROR;
}
return status;
}
/**
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
* @arg @ref __LL_DMA_GET_INSTANCE
* @arg @ref __LL_DMA_GET_CHANNEL
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Check the DMA Instance DMAx and Channel parameters*/
assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
/* Check the DMA parameters from DMA_InitStruct */
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
/*---------------------------- DMAx CCR Configuration ------------------------
* Configure DMAx_Channely: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
* - Mode: DMA_CCR_CIRC bit
* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
* - Priority: DMA_CCR_PL[1:0] bits
*/
LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
DMA_InitStruct->Priority);
/*-------------------------- DMAx CMAR Configuration -------------------------
* Configure the memory or destination base address with parameter :
* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
*/
LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
/*-------------------------- DMAx CPAR Configuration -------------------------
* Configure the peripheral or source base address with parameter :
* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
*/
LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
/*--------------------------- DMAx CNDTR Configuration -----------------------
* Configure the peripheral base address with parameter :
* - NbData: DMA_CNDTR_NDT[15:0] bits
*/
LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
return SUCCESS;
}
/**
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval None
*/
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_exti.c
* @author MCD Application Team
* @brief EXTI LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_exti.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup EXTI_LL_Private_Macros
* @{
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_LL_Exported_Functions
* @{
*/
/** @addtogroup EXTI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the EXTI registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are de-initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_DeInit(void)
{
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR, 0x00000000U);
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR, 0x00000000U);
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
/* Pending register clear */
LL_EXTI_WriteReg(PR, 0x000FFFFFU);
return SUCCESS;
}
/**
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
/* ENABLE LineCommand */
if (EXTI_InitStruct->LineCommand != DISABLE)
{
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
/* Configure EXTI Lines in range from 0 to 31 */
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
{
switch (EXTI_InitStruct->Mode)
{
case LL_EXTI_MODE_IT:
/* First Disable Event on provided Lines */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable IT on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_EVENT:
/* First Disable IT on provided Lines */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Event on provided Lines */
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_IT_EVENT:
/* Directly Enable IT & Event on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
{
case LL_EXTI_TRIGGER_RISING:
/* First Disable Falling Trigger on provided Lines */
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Rising Trigger on provided Lines */
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_FALLING:
/* First Disable Rising Trigger on provided Lines */
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Falling Trigger on provided Lines */
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_RISING_FALLING:
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
}
}
}
/* DISABLE LineCommand */
else
{
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
return status;
}
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval None
*/
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (EXTI) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_fsmc.c
* @author MCD Application Team
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Flexible Memory Controller (FSMC) peripheral memories:
* + Initialization/de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### FSMC peripheral features #####
==============================================================================
[..] The Flexible memory controller (FSMC) includes following memory controllers:
(+) The NOR/PSRAM memory controller
(+) The NAND/PC Card memory controller
[..] The FSMC functional block makes the interface with synchronous and asynchronous static
memories and 16-bit PC memory cards. Its main purposes are:
(+) to translate AHB transactions into the appropriate external device protocol
(+) to meet the access time requirements of the external memory devices
[..] All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique Chip Select. The FSMC performs
only one access at a time to an external device.
The main features of the FSMC controller are the following:
(+) Interface with static-memory mapped devices including:
(++) Static random access memory (SRAM)
(++) Read-only memory (ROM)
(++) NOR Flash memory/OneNAND Flash memory
(++) PSRAM (4 memory banks)
(++) 16-bit PC Card compatible devices
(++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
data
(+) Independent Chip Select control for each memory bank
(+) Independent configuration for each memory bank
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
#if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_PCCARD_MODULE_ENABLED )
/** @defgroup FSMC_LL FSMC Low Layer
* @brief FSMC driver modules
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
* @{
*/
/* ----------------------- FSMC registers bit mask --------------------------- */
#if defined FSMC_BANK1
/* --- BCR Register ---*/
/* BCR register clear mask */
/* --- BTR Register ---*/
/* BTR register clear mask */
#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
FSMC_BTRx_ACCMOD))
/* --- BWTR Register ---*/
/* BWTR register clear mask */
#if defined(FSMC_BWTRx_BUSTURN)
#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
FSMC_BWTRx_DATAST | FSMC_BWTRx_BUSTURN |\
FSMC_BWTRx_ACCMOD))
#else
#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD |\
FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD))
#endif /* FSMC_BWTRx_BUSTURN */
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/* --- PCR Register ---*/
/* PCR register clear mask */
#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \
FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \
FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \
FSMC_PCRx_TAR | FSMC_PCRx_ECCPS))
/* --- PMEM Register ---*/
/* PMEM register clear mask */
#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\
FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
/* --- PATT Register ---*/
/* PATT register clear mask */
#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\
FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/* --- PCR Register ---*/
/* PCR register clear mask */
#define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \
FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \
FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \
FSMC_PCR4_TAR | FSMC_PCR4_ECCPS))
/* --- PMEM Register ---*/
/* PMEM register clear mask */
#define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\
FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
/* --- PATT Register ---*/
/* PATT register clear mask */
#define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\
FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
/* --- PIO4 Register ---*/
/* PIO4 register clear mask */
#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
#endif /* FSMC_BANK4 */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
* @{
*/
#if defined FSMC_BANK1
/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions
* @brief NORSRAM Controller functions
*
@verbatim
==============================================================================
##### How to use NORSRAM device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
to run the NORSRAM external devices.
(+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
(+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
(+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
(+) FSMC NORSRAM bank extended timing configuration using the function
FSMC_NORSRAM_Extended_Timing_Init()
(+) FSMC NORSRAM bank enable/disable write operation using the functions
FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
@endverbatim
* @{
*/
/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the FSMC NORSRAM interface
(+) De-initialize the FSMC NORSRAM interface
(+) Configure the FSMC clock and associated GPIOs
@endverbatim
* @{
*/
/**
* @brief Initialize the FSMC_NORSRAM device according to the specified
* control parameters in the FSMC_NORSRAM_InitTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
assert_param(IS_FSMC_MUX(Init->DataAddressMux));
assert_param(IS_FSMC_MEMORY(Init->MemoryType));
assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
/* Disable NORSRAM Device */
__FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
/* Set NORSRAM device control parameters */
if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
{
flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
}
else
{
flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
}
MODIFY_REG(Device->BTCR[Init->NSBank],
(FSMC_BCRx_MBKEN |
FSMC_BCRx_MUXEN |
FSMC_BCRx_MTYP |
FSMC_BCRx_MWID |
FSMC_BCRx_FACCEN |
FSMC_BCRx_BURSTEN |
FSMC_BCRx_WAITPOL |
FSMC_BCRx_WRAPMOD |
FSMC_BCRx_WAITCFG |
FSMC_BCRx_WREN |
FSMC_BCRx_WAITEN |
FSMC_BCRx_EXTMOD |
FSMC_BCRx_ASYNCWAIT |
FSMC_BCRx_CBURSTRW |
0x00070000U), /* CPSIZE to be defined in CMSIS file */
(flashaccess |
Init->DataAddressMux |
Init->MemoryType |
Init->MemoryDataWidth |
Init->BurstAccessMode |
Init->WaitSignalPolarity |
Init->WrapMode |
Init->WaitSignalActive |
Init->WriteOperation |
Init->WaitSignal |
Init->ExtendedMode |
Init->AsynchronousWait |
Init->WriteBurst |
Init->PageSize));
return HAL_OK;
}
/**
* @brief DeInitialize the FSMC_NORSRAM peripheral
* @param Device Pointer to NORSRAM device instance
* @param ExDevice Pointer to NORSRAM extended mode device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Disable the FSMC_NORSRAM device */
__FSMC_NORSRAM_DISABLE(Device, Bank);
/* De-initialize the FSMC_NORSRAM device */
/* FSMC_NORSRAM_BANK1 */
if (Bank == FSMC_NORSRAM_BANK1)
{
Device->BTCR[Bank] = 0x000030DBU;
}
/* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
else
{
Device->BTCR[Bank] = 0x000030D2U;
}
Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
return HAL_OK;
}
/**
* @brief Initialize the FSMC_NORSRAM Timing according to the specified
* parameters in the FSMC_NORSRAM_TimingTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Timing Pointer to NORSRAM Timing structure
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set FSMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) |
((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) |
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) |
(Timing->AccessMode)));
return HAL_OK;
}
/**
* @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FSMC_NORSRAM_TimingTypeDef
* @param Device Pointer to NORSRAM device instance
* @param Timing Pointer to NORSRAM Timing structure
* @param Bank NORSRAM bank number
* @param ExtendedMode FSMC Extended Mode
* This parameter can be one of the following values:
* @arg FSMC_EXTENDED_MODE_DISABLE
* @arg FSMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
#else
assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Set NORSRAM device timing register for write configuration, if extended mode is used */
#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) |
Timing->AccessMode |
((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
#else
MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) |
((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) |
Timing->AccessMode |
(((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) |
(((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
}
else
{
Device->BWTR[Bank] = 0x0FFFFFFFU;
}
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
* @brief management functions
*
@verbatim
==============================================================================
##### FSMC_NORSRAM Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FSMC NORSRAM interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically FSMC_NORSRAM write operation.
* @param Device Pointer to NORSRAM device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Enable write operation */
SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
return HAL_OK;
}
/**
* @brief Disables dynamically FSMC_NORSRAM write operation.
* @param Device Pointer to NORSRAM device instance
* @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
assert_param(IS_FSMC_NORSRAM_BANK(Bank));
/* Disable write operation */
CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* FSMC_BANK1 */
#if defined(FSMC_BANK3)
/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions
* @brief NAND Controller functions
*
@verbatim
==============================================================================
##### How to use NAND device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FSMC NAND banks in order
to run the NAND external devices.
(+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
(+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
(+) FSMC NAND bank common space timing configuration using the function
FSMC_NAND_CommonSpace_Timing_Init()
(+) FSMC NAND bank attribute space timing configuration using the function
FSMC_NAND_AttributeSpace_Timing_Init()
(+) FSMC NAND bank enable/disable ECC correction feature using the functions
FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
(+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
@endverbatim
* @{
*/
/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the FSMC NAND interface
(+) De-initialize the FSMC NAND interface
(+) Configure the FSMC clock and associated GPIOs
@endverbatim
* @{
*/
/**
* @brief Initializes the FSMC_NAND device according to the specified
* control parameters in the FSMC_NAND_HandleTypeDef
* @param Device Pointer to NAND device instance
* @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
/* Set NAND device control parameters */
if (Init->NandBank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
FSMC_PCR_MEMORY_TYPE_NAND |
Init->MemoryDataWidth |
Init->EccComputation |
Init->ECCPageSize |
((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
FSMC_PCR_MEMORY_TYPE_NAND |
Init->MemoryDataWidth |
Init->EccComputation |
Init->ECCPageSize |
((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to NAND device instance
* @param Timing Pointer to NAND timing structure
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Set FSMC_NAND device timing parameters */
if (Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
}
return HAL_OK;
}
/**
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to NAND device instance
* @param Timing Pointer to NAND timing structure
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Set FSMC_NAND device timing parameters */
if (Bank == FSMC_NAND_BANK2)
{
/* NAND bank 2 registers configuration */
MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
}
else
{
/* NAND bank 3 registers configuration */
MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
}
return HAL_OK;
}
/**
* @brief DeInitializes the FSMC_NAND device
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Disable the NAND Bank */
__FSMC_NAND_DISABLE(Device, Bank);
/* De-initialize the NAND Bank */
if (Bank == FSMC_NAND_BANK2)
{
/* Set the FSMC_NAND_BANK2 registers to their reset values */
WRITE_REG(Device->PCR2, 0x00000018U);
WRITE_REG(Device->SR2, 0x00000040U);
WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
}
/* FSMC_Bank3_NAND */
else
{
/* Set the FSMC_NAND_BANK3 registers to their reset values */
WRITE_REG(Device->PCR3, 0x00000018U);
WRITE_REG(Device->SR3, 0x00000040U);
WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
}
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### FSMC_NAND Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the FSMC NAND interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Enable ECC feature */
if (Bank == FSMC_NAND_BANK2)
{
SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
}
else
{
SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
}
return HAL_OK;
}
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Disable ECC feature */
if (Bank == FSMC_NAND_BANK2)
{
CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
}
else
{
CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
}
return HAL_OK;
}
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
* @param Device Pointer to NAND device instance
* @param ECCval Pointer to ECC value
* @param Bank NAND bank number
* @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
{
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_FSMC_NAND_DEVICE(Device));
assert_param(IS_FSMC_NAND_BANK(Bank));
/* Get tick */
tickstart = HAL_GetTick();
/* Wait until FIFO is empty */
while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
return HAL_TIMEOUT;
}
}
}
if (Bank == FSMC_NAND_BANK2)
{
/* Get the ECCR2 register value */
*ECCval = (uint32_t)Device->ECCR2;
}
else
{
/* Get the ECCR3 register value */
*ECCval = (uint32_t)Device->ECCR3;
}
return HAL_OK;
}
/**
* @}
*/
#endif /* FSMC_BANK3 */
#if defined(FSMC_BANK4)
/** @addtogroup FSMC_LL_PCCARD
* @brief PCCARD Controller functions
*
@verbatim
==============================================================================
##### How to use PCCARD device driver #####
==============================================================================
[..]
This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
to run the PCCARD/compact flash external devices.
(+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
(+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
(+) FSMC PCCARD bank common space timing configuration using the function
FSMC_PCCARD_CommonSpace_Timing_Init()
(+) FSMC PCCARD bank attribute space timing configuration using the function
FSMC_PCCARD_AttributeSpace_Timing_Init()
(+) FSMC PCCARD bank IO space timing configuration using the function
FSMC_PCCARD_IOSpace_Timing_Init()
@endverbatim
* @{
*/
/** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and configure the FSMC PCCARD interface
(+) De-initialize the FSMC PCCARD interface
(+) Configure the FSMC clock and associated GPIOs
@endverbatim
* @{
*/
/**
* @brief Initializes the FSMC_PCCARD device according to the specified
* control parameters in the FSMC_PCCARD_HandleTypeDef
* @param Device Pointer to PCCARD device instance
* @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
/* Set FSMC_PCCARD device control parameters */
MODIFY_REG(Device->PCR4,
(FSMC_PCRx_PTYP |
FSMC_PCRx_PWAITEN |
FSMC_PCRx_PWID |
FSMC_PCRx_TCLR |
FSMC_PCRx_TAR),
(FSMC_PCR_MEMORY_TYPE_PCCARD |
Init->Waitfeature |
FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
(Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) |
(Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
(Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set PCCARD timing parameters */
MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,
(Timing->SetupTime |
((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) |
((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) |
((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
return HAL_OK;
}
/**
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
* @param Device Pointer to PCCARD device instance
* @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
/* Set FSMC_PCCARD device timing parameters */
MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,
(Timing->SetupTime |
(Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) |
(Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) |
(Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
return HAL_OK;
}
/**
* @brief DeInitializes the FSMC_PCCARD device
* @param Device Pointer to PCCARD device instance
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
{
/* Check the parameters */
assert_param(IS_FSMC_PCCARD_DEVICE(Device));
/* Disable the FSMC_PCCARD device */
__FSMC_PCCARD_DISABLE(Device);
/* De-initialize the FSMC_PCCARD device */
Device->PCR4 = 0x00000018U;
Device->SR4 = 0x00000040U;
Device->PMEM4 = 0xFCFCFCFCU;
Device->PATT4 = 0xFCFCFCFCU;
Device->PIO4 = 0xFCFCFCFCU;
return HAL_OK;
}
/**
* @}
*/
#endif /* FSMC_BANK4 */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

253
LLDrivers/src/stm32f1xx_ll_gpio.c Normal file
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@ -0,0 +1,253 @@
/**
******************************************************************************
* @file stm32f1xx_ll_gpio.c
* @author MCD Application Team
* @brief GPIO LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_gpio.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
/** @addtogroup GPIO_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
#define IS_LL_GPIO_PIN(__VALUE__) ((((__VALUE__) & LL_GPIO_PIN_ALL)!= 0u) &&\
(((__VALUE__) & (~LL_GPIO_PIN_ALL))== 0u))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
((__VALUE__) == LL_GPIO_PULL_UP))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_LL_Exported_Functions
* @{
*/
/** @addtogroup GPIO_LL_EF_Init
* @{
*/
/**
* @brief De-initialize GPIO registers (Registers restored to their default values).
* @param GPIOx GPIO Port
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Force and Release reset on clock of GPIOx Port */
if (GPIOx == GPIOA)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
}
else if (GPIOx == GPIOB)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
}
else if (GPIOx == GPIOC)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
}
else if (GPIOx == GPIOD)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
}
#if defined(GPIOE)
else if (GPIOx == GPIOE)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
}
#endif
#if defined(GPIOF)
else if (GPIOx == GPIOF)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
}
#endif
#if defined(GPIOG)
else if (GPIOx == GPIOG)
{
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
}
#endif
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
* - ERROR: Not applicable
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t pinmask;
uint32_t pinpos;
uint32_t currentpin;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinmask = ((GPIO_InitStruct->Pin) << GPIO_PIN_MASK_POS) >> GPIO_PIN_NB;
pinpos = POSITION_VAL(pinmask);
/* Configure the port pins */
while ((pinmask >> pinpos) != 0u)
{
/* skip if bit is not set */
if ((pinmask & (1u << pinpos)) != 0u)
{
/* Get current io position */
if (pinpos < GPIO_PIN_MASK_POS)
{
currentpin = (0x00000101uL << pinpos);
}
else
{
currentpin = ((0x00010001u << (pinpos - GPIO_PIN_MASK_POS)) | 0x04000000u);
}
/* Check Pin Mode and Pin Pull parameters */
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
/* Pull-up Pull-down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check speed and Output mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
}
}
pinpos++;
}
return (SUCCESS);
}
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_i2c.c
* @author MCD Application Team
* @brief I2C LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_i2c.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (I2C1) || defined (I2C2)
/** @defgroup I2C_LL I2C
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup I2C_LL_Private_Macros
* @{
*/
#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
((__VALUE__) == LL_I2C_NACK))
#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_LL_Exported_Functions
* @{
*/
/** @addtogroup I2C_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the I2C registers to their default reset values.
* @param I2Cx I2C Instance.
* @retval An ErrorStatus enumeration value:
* - SUCCESS I2C registers are de-initialized
* - ERROR I2C registers are not de-initialized
*/
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
if (I2Cx == I2C1)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
}
#if defined(I2C2)
else if (I2Cx == I2C2)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
}
#endif /* I2C2 */
else
{
status = ERROR;
}
return status;
}
/**
* @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
* @param I2Cx I2C Instance.
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS I2C registers are initialized
* - ERROR Not applicable
*/
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
{
LL_RCC_ClocksTypeDef rcc_clocks;
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
/* Check the I2C parameters from I2C_InitStruct */
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
/* Disable the selected I2Cx Peripheral */
LL_I2C_Disable(I2Cx);
/* Retrieve Clock frequencies */
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
/*---------------------------- I2Cx SCL Clock Speed Configuration ------------
* Configure the SCL speed :
* - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS,
* and I2C_CCR_CCR[11:0] bits
* - DutyCycle: I2C_CCR_DUTY[7:0] bits
*/
LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle);
/*---------------------------- I2Cx OAR1 Configuration -----------------------
* Disable, Configure and Enable I2Cx device own address 1 with parameters :
* - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits
* - OwnAddrSize: I2C_OAR1_ADDMODE bit
*/
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
/*---------------------------- I2Cx MODE Configuration -----------------------
* Configure I2Cx peripheral mode with parameter :
* - PeripheralMode: I2C_CR1_SMBUS, I2C_CR1_SMBTYPE and I2C_CR1_ENARP bits
*/
LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
/* Enable the selected I2Cx Peripheral */
LL_I2C_Enable(I2Cx);
/*---------------------------- I2Cx CR2 Configuration ------------------------
* Configure the ACKnowledge or Non ACKnowledge condition
* after the address receive match code or next received byte with parameter :
* - TypeAcknowledge: I2C_CR2_NACK bit
*/
LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
return SUCCESS;
}
/**
* @brief Set each @ref LL_I2C_InitTypeDef field to default value.
* @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
* @retval None
*/
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Set I2C_InitStruct fields to default values */
I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
I2C_InitStruct->ClockSpeed = 5000U;
I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2;
I2C_InitStruct->OwnAddress1 = 0U;
I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* I2C1 || I2C2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_pwr.c
* @author MCD Application Team
* @brief PWR LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_pwr.h"
#include "stm32f1xx_ll_bus.h"
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_LL_Exported_Functions
* @{
*/
/** @addtogroup PWR_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the PWR registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PWR registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_PWR_DeInit(void)
{
/* Force reset of PWR clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
/* Release reset of PWR clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
return SUCCESS;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_rcc.c
* @author MCD Application Team
* @brief RCC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCC_LL_Private_Macros
* @{
*/
#if defined(RCC_PLLI2S_SUPPORT)
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
|| ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(USB) || defined(USB_OTG_FS)
#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
#endif /* USB */
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
uint32_t RCC_GetSystemClockFreq(void);
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
#if defined(RCC_PLLI2S_SUPPORT)
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
#endif /* RCC_PLLI2S_SUPPORT */
#if defined(RCC_PLL2_SUPPORT)
uint32_t RCC_PLL2_GetFreqClockFreq(void);
#endif /* RCC_PLL2_SUPPORT */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_LL_Exported_Functions
* @{
*/
/** @addtogroup RCC_LL_EF_Init
* @{
*/
/**
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
* - HSE PLL, PLL2 & PLL3 are OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
* - Peripheral clocks
* - LSI, LSE and RTC clocks
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RCC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RCC_DeInit(void)
{
/* Set HSION bit */
LL_RCC_HSI_Enable();
/* Wait for HSI READY bit */
while (LL_RCC_HSI_IsReady() != 1U)
{}
/* Configure HSI as system clock source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
/* Wait till clock switch is ready */
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{}
/* Reset PLLON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
/* Wait for PLL READY bit to be reset */
while (LL_RCC_PLL_IsReady() != 0U)
{}
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
/* Reset HSEON, HSEBYP & CSSON bits */
CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
#if defined(RCC_CR_PLL2ON)
/* Reset PLL2ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
#endif /* RCC_CR_PLL2ON */
#if defined(RCC_CR_PLL3ON)
/* Reset PLL3ON bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
#endif /* RCC_CR_PLL3ON */
/* Set HSITRIM bits to the reset value */
LL_RCC_HSI_SetCalibTrimming(0x10U);
#if defined(RCC_CFGR2_PREDIV1)
/* Reset CFGR2 register */
LL_RCC_WriteReg(CFGR2, 0x00000000U);
#endif /* RCC_CFGR2_PREDIV1 */
/* Disable all interrupts */
LL_RCC_WriteReg(CIR, 0x00000000U);
/* Clear reset flags */
LL_RCC_ClearResetFlags();
return SUCCESS;
}
/**
* @}
*/
/** @addtogroup RCC_LL_EF_Get_Freq
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* and different peripheral clocks available on the device.
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
* @note If SYSCLK source is PLL, function returns values based on
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
* @note (**) HSI_VALUE is a defined constant but the real value may vary
* depending on the variations in voltage and temperature.
* @note (***) HSE_VALUE is a defined constant, user has to ensure that
* HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
* @note The result of this function could be incorrect when using fractional
* value for HSE crystal.
* @note This function can be used by the user application to compute the
* baud-rate for the communication peripherals or configure other parameters.
* @{
*/
/**
* @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
* @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
* must be called to update structure fields. Otherwise, any
* configuration based on this function will be incorrect.
* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
* @retval None
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
{
/* Get SYSCLK frequency */
RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
/* HCLK clock frequency */
RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
/* PCLK1 clock frequency */
RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
/* PCLK2 clock frequency */
RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
}
#if defined(RCC_CFGR2_I2S2SRC)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S2_CLKSOURCE
* @arg @ref LL_RCC_I2S3_CLKSOURCE
* @retval I2S clock frequency (in Hz)
*/
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
{
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
/* I2S1CLK clock frequency */
switch (LL_RCC_GetI2SClockSource(I2SxSource))
{
case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
i2s_frequency = RCC_GetSystemClockFreq();
break;
case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
default:
i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
break;
}
return i2s_frequency;
}
#endif /* RCC_CFGR2_I2S2SRC */
#if defined(USB) || defined(USB_OTG_FS)
/**
* @brief Return USBx clock frequency
* @param USBxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE
* @retval USB clock frequency (in Hz)
* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
*/
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
{
uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
/* USBCLK clock frequency */
switch (LL_RCC_GetUSBClockSource(USBxSource))
{
#if defined(RCC_CFGR_USBPRE)
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
}
break;
#endif /* RCC_CFGR_USBPRE */
#if defined(RCC_CFGR_OTGFSPRE)
/* USBCLK = PLLVCO/2
= (2 x PLLCLK) / 2
= PLLCLK */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady())
{
usb_frequency = RCC_PLL_GetFreqDomain_SYS();
}
break;
/* USBCLK = PLLVCO/3
= (2 x PLLCLK) / 3 */
case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
default:
if (LL_RCC_PLL_IsReady())
{
usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
}
break;
#endif /* RCC_CFGR_OTGFSPRE */
}
return usb_frequency;
}
#endif /* USB */
/**
* @brief Return ADCx clock frequency
* @param ADCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC_CLKSOURCE
* @retval ADC clock frequency (in Hz)
*/
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
{
uint32_t adc_prescaler = 0U;
uint32_t adc_frequency = 0U;
/* Check parameter */
assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
/* Get ADC prescaler */
adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
/* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
/ (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
return adc_frequency;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup RCC_LL_Private_Functions
* @{
*/
/**
* @brief Return SYSTEM clock frequency
* @retval SYSTEM clock frequency (in Hz)
*/
uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency = 0U;
/* Get SYSCLK source -------------------------------------------------------*/
switch (LL_RCC_GetSysClkSource())
{
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
frequency = HSI_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
frequency = HSE_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
frequency = RCC_PLL_GetFreqDomain_SYS();
break;
default:
frequency = HSI_VALUE;
break;
}
return frequency;
}
/**
* @brief Return HCLK clock frequency
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK clock frequency (in Hz)
*/
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
}
/**
* @brief Return PCLK1 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
}
/**
* @brief Return PCLK2 clock frequency
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
}
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq = 0U, pllsource = 0U;
/* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
/* Get PLL source */
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
pllinputfreq = HSI_VALUE / 2U;
break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#if defined(RCC_PLL2_SUPPORT)
case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
break;
#endif /* RCC_PLL2_SUPPORT */
default:
pllinputfreq = HSI_VALUE / 2U;
break;
}
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
}
#if defined(RCC_PLL2_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL2_GetFreqClockFreq(void)
{
return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/**
* @brief Return PLL clock frequency used for system domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
{
return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
}
#endif /* RCC_PLLI2S_SUPPORT */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_rtc.c
* @author MCD Application Team
* @brief RTC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rtc.h"
#include "stm32f1xx_ll_cortex.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined(RTC)
/** @addtogroup RTC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RTC_LL_Private_Constants
* @{
*/
/* Default values used for prescaler */
#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU
/* Values used for timeout */
#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RTC_LL_Private_Macros
* @{
*/
#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU)
#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
|| ((__VALUE__) == LL_RTC_FORMAT_BCD))
#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \
((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTC_LL_Exported_Functions
* @{
*/
/** @addtogroup RTC_LL_EF_Init
* @{
*/
/**
* @brief De-Initializes the RTC registers to their default reset values.
* @note This function doesn't reset the RTC Clock source and RTC Backup Data
* registers.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are de-initialized
* - ERROR: RTC registers are not de-initialized
*/
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
{
ErrorStatus status = ERROR;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
LL_RTC_WriteReg(RTCx, CNTL, 0x0000);
LL_RTC_WriteReg(RTCx, CNTH, 0x0000);
LL_RTC_WriteReg(RTCx, PRLH, 0x0000);
LL_RTC_WriteReg(RTCx, PRLL, 0x8000);
LL_RTC_WriteReg(RTCx, CRH, 0x0000);
LL_RTC_WriteReg(RTCx, CRL, 0x0020);
/* Reset Tamper and alternate functions configuration register */
LL_RTC_WriteReg(BKP, RTCCR, 0x00000000U);
LL_RTC_WriteReg(BKP, CR, 0x00000000U);
LL_RTC_WriteReg(BKP, CSR, 0x00000000U);
/* Exit Initialization Mode */
if (LL_RTC_ExitInitMode(RTCx) != ERROR)
{
/* Wait till the RTC RSF flag is set */
status = LL_RTC_WaitForSynchro(RTCx);
/* Clear RSF Flag */
LL_RTC_ClearFlag_RS(RTCx);
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
}
}
else
{
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
}
return status;
}
/**
* @brief Initializes the RTC registers according to the specified parameters
* in RTC_InitStruct.
* @param RTCx RTC Instance
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
* the configuration information for the RTC peripheral.
* @note The RTC Prescaler register is write protected and can be written in
* initialization mode only.
* @note the user should call LL_RTC_StructInit() or the structure of Prescaler
* need to be initialized before RTC init()
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are initialized
* - ERROR: RTC registers are not initialized
*/
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource));
/* Waiting for synchro */
if (LL_RTC_WaitForSynchro(RTCx) != ERROR)
{
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Clear Flag Bits */
LL_RTC_ClearFlag_ALR(RTCx);
LL_RTC_ClearFlag_OW(RTCx);
LL_RTC_ClearFlag_SEC(RTCx);
if (RTC_InitStruct->OutPutSource != LL_RTC_CALIB_OUTPUT_NONE)
{
/* Disable the selected Tamper Pin */
LL_RTC_TAMPER_Disable(BKP);
}
/* Set the signal which will be routed to RTC Tamper Pin */
LL_RTC_SetOutputSource(BKP, RTC_InitStruct->OutPutSource);
/* Configure Synchronous and Asynchronous prescaler factor */
LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
/* Exit Initialization Mode */
LL_RTC_ExitInitMode(RTCx);
status = SUCCESS;
}
}
return status;
}
/**
* @brief Set each @ref LL_RTC_InitTypeDef field to default value.
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
{
/* Set RTC_InitStruct fields to default values */
RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE;
}
/**
* @brief Set the RTC current time.
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
* the time configuration information for the RTC.
* @note The user should call LL_RTC_TIME_StructInit() or the structure
* of time need to be initialized before time init()
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC Time register is configured
* - ERROR: RTC Time register is not configured
*/
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
{
ErrorStatus status = ERROR;
uint32_t counter_time = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
}
else
{
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
}
/* Enter Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \
((uint32_t)RTC_TimeStruct->Minutes * 60U) + \
((uint32_t)RTC_TimeStruct->Seconds));
LL_RTC_TIME_Set(RTCx, counter_time);
}
else
{
counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))));
LL_RTC_TIME_Set(RTCx, counter_time);
}
status = SUCCESS;
}
/* Exit Initialization mode */
LL_RTC_ExitInitMode(RTCx);
return status;
}
/**
* @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
* @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
{
/* Time = 00h:00min:00sec */
RTC_TimeStruct->Hours = 0U;
RTC_TimeStruct->Minutes = 0U;
RTC_TimeStruct->Seconds = 0U;
}
/**
* @brief Set the RTC Alarm.
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
* contains the alarm configuration parameters.
* @note the user should call LL_RTC_ALARM_StructInit() or the structure
* of Alarm need to be initialized before Alarm init()
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ALARM registers are configured
* - ERROR: ALARM registers are not configured
*/
ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
ErrorStatus status = ERROR;
uint32_t counter_alarm = 0U;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
}
else
{
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
}
/* Enter Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \
((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \
((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds));
LL_RTC_ALARM_Set(RTCx, counter_alarm);
}
else
{
counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \
((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))));
LL_RTC_ALARM_Set(RTCx, counter_alarm);
}
status = SUCCESS;
}
/* Exit Initialization mode */
LL_RTC_ExitInitMode(RTCx);
return status;
}
/**
* @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec /
* Day = 1st day of the month/Mask = all fields are masked).
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
/* Alarm Time Settings : Time = 00h:00mn:00sec */
RTC_AlarmStruct->AlarmTime.Hours = 0U;
RTC_AlarmStruct->AlarmTime.Minutes = 0U;
RTC_AlarmStruct->AlarmTime.Seconds = 0U;
}
/**
* @brief Enters the RTC Initialization mode.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC is in Init mode
* - ERROR: RTC is not in Init mode
*/
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
{
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
ErrorStatus status = SUCCESS;
uint32_t tmp = 0U;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Wait till RTC is in INIT state and if Time out is reached exit */
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout --;
}
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
return status;
}
/**
* @brief Exit the RTC Initialization mode.
* @note When the initialization sequence is complete, the calendar restarts
* counting after 4 RTCCLK cycles.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC exited from in Init mode
* - ERROR: Not applicable
*/
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
{
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
ErrorStatus status = SUCCESS;
uint32_t tmp = 0U;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Disable initialization mode */
LL_RTC_EnableWriteProtection(RTCx);
/* Wait till RTC is in INIT state and if Time out is reached exit */
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout --;
}
tmp = LL_RTC_IsActiveFlag_RTOF(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
return status;
}
/**
* @brief Set the Time Counter
* @param RTCx RTC Instance
* @param TimeCounter this value can be from 0 to 0xFFFFFFFF
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC Counter register configured
* - ERROR: Not applicable
*/
ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter)
{
ErrorStatus status = ERROR;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Enter Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
LL_RTC_TIME_Set(RTCx, TimeCounter);
status = SUCCESS;
}
/* Exit Initialization mode */
LL_RTC_ExitInitMode(RTCx);
return status;
}
/**
* @brief Set Alarm Counter.
* @param RTCx RTC Instance
* @param AlarmCounter this value can be from 0 to 0xFFFFFFFF
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC exited from in Init mode
* - ERROR: Not applicable
*/
ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
{
ErrorStatus status = ERROR;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Enter Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
LL_RTC_ALARM_Set(RTCx, AlarmCounter);
status = SUCCESS;
}
/* Exit Initialization mode */
LL_RTC_ExitInitMode(RTCx);
return status;
}
/**
* @brief Waits until the RTC registers are synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are synchronised
* - ERROR: RTC registers are not synchronised
*/
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
{
__IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
ErrorStatus status = SUCCESS;
uint32_t tmp = 0U;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Clear RSF flag */
LL_RTC_ClearFlag_RS(RTCx);
/* Wait the registers to be synchronised */
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
while ((timeout != 0U) && (tmp != 0U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout--;
}
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RTC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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LLDrivers/src/stm32f1xx_ll_sdmmc.c Normal file
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/**
******************************************************************************
* @file stm32f1xx_ll_spi.c
* @author MCD Application Team
* @brief SPI LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_spi.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (SPI1) || defined (SPI2) || defined (SPI3)
/** @addtogroup SPI_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SPI_LL_Private_Constants SPI Private Constants
* @{
*/
/* SPI registers Masks */
#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
SPI_CR1_BIDIMODE)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_LL_Exported_Functions
* @{
*/
/** @addtogroup SPI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the SPI registers to their default reset values.
* @param SPIx SPI Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
#if defined(SPI1)
if (SPIx == SPI1)
{
/* Force reset of SPI clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
status = SUCCESS;
}
#endif /* SPI1 */
#if defined(SPI2)
if (SPIx == SPI2)
{
/* Force reset of SPI clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
status = SUCCESS;
}
#endif /* SPI2 */
#if defined(SPI3)
if (SPIx == SPI3)
{
/* Force reset of SPI clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
status = SUCCESS;
}
#endif /* SPI3 */
return status;
}
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
*/
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
{
ErrorStatus status = ERROR;
/* Check the SPI Instance SPIx*/
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
/* Check the SPI parameters from SPI_InitStruct*/
assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
{
/*---------------------------- SPIx CR1 Configuration ------------------------
* Configure SPIx CR1 with parameters:
* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
* - Master/Slave Mode: SPI_CR1_MSTR bit
* - DataWidth: SPI_CR1_DFF bit
* - ClockPolarity: SPI_CR1_CPOL bit
* - ClockPhase: SPI_CR1_CPHA bit
* - NSS management: SPI_CR1_SSM bit
* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
* - BitOrder: SPI_CR1_LSBFIRST bit
* - CRCCalculation: SPI_CR1_CRCEN bit
*/
MODIFY_REG(SPIx->CR1,
SPI_CR1_CLEAR_MASK,
SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
/*---------------------------- SPIx CR2 Configuration ------------------------
* Configure SPIx CR2 with parameters:
* - NSS management: SSOE bit
*/
MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
/*---------------------------- SPIx CRCPR Configuration ----------------------
* Configure SPIx CRCPR with parameters:
* - CRCPoly: CRCPOLY[15:0] bits
*/
if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
}
status = SUCCESS;
}
#if defined (SPI_I2S_SUPPORT)
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
#endif /* SPI_I2S_SUPPORT */
return status;
}
/**
* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
{
/* Set SPI_InitStruct fields to default values */
SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
SPI_InitStruct->CRCPoly = 7U;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#if defined(SPI_I2S_SUPPORT)
/** @addtogroup I2S_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2S_LL_Private_Constants I2S Private Constants
* @{
*/
/* I2S registers Masks */
#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
#define I2S_I2SPR_CLEAR_MASK 0x0002U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_LL_Private_Macros I2S Private Macros
* @{
*/
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_LL_Exported_Functions
* @{
*/
/** @addtogroup I2S_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the SPI/I2S registers to their default reset values.
* @param SPIx SPI Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
* SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are Initialized
* - ERROR: SPI registers are not Initialized
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
uint32_t i2sdiv = 2U;
uint32_t i2sodd = 0U;
uint32_t packetlength = 1U;
uint32_t tmp;
LL_RCC_ClocksTypeDef rcc_clocks;
uint32_t sourceclock;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
{
/*---------------------------- SPIx I2SCFGR Configuration --------------------
* Configure SPIx I2SCFGR with parameters:
* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
*/
/* Write to SPIx I2SCFGR */
MODIFY_REG(SPIx->I2SCFGR,
I2S_I2SCFGR_CLEAR_MASK,
I2S_InitStruct->Mode | I2S_InitStruct->Standard |
I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
SPI_I2SCFGR_I2SMOD);
/*---------------------------- SPIx I2SPR Configuration ----------------------
* Configure SPIx I2SPR with parameters:
* - MCLKOutput: SPI_I2SPR_MCKOE bit
* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
*/
/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
*/
if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
{
/* Check the frame length (For the Prescaler computing)
* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
*/
if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
{
/* Packet length is 32 bits */
packetlength = 2U;
}
/* I2S Clock source is System clock: Get System Clock frequency */
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
/* Get the source clock value: based on System Clock value */
sourceclock = rcc_clocks.SYSCLK_Frequency;
/* Compute the Real divider depending on the MCLK output state with a floating point */
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
{
/* MCLK output is enabled */
tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
/* Remove the floating point */
tmp = tmp / 10U;
/* Check the parity of the divider */
i2sodd = (tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
i2sdiv = ((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the default values */
i2sdiv = 2U;
i2sodd = 0U;
}
/* Write to SPIx I2SPR register the computed value */
WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
status = SUCCESS;
}
return status;
}
/**
* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
{
/*--------------- Reset I2S init structure parameters values -----------------*/
I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
}
/**
* @brief Set linear and parity prescaler.
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
* @param SPIx SPI Instance
* @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
* @param PrescalerParity This parameter can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
* @retval None
*/
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
{
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
/* Write to SPIx I2SPR */
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_usart.c
* @author MCD Application Team
* @brief USART LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
/** @addtogroup USART_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
*/
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
* divided by the smallest oversampling used on the USART (i.e. 8) */
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4500000U)
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_LL_Exported_Functions
* @{
*/
/** @addtogroup USART_LL_EF_Init
* @{
*/
/**
* @brief De-initialize USART registers (Registers restored to their default values).
* @param USARTx USART Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
if (USARTx == USART1)
{
/* Force reset of USART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
/* Release reset of USART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
}
else if (USARTx == USART2)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
}
#if defined(USART3)
else if (USARTx == USART3)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
}
#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
}
#endif /* UART4 */
#if defined(UART5)
else if (USARTx == UART5)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
}
#endif /* UART5 */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
LL_RCC_ClocksTypeDef rcc_clocks;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
#if defined(USART_CR1_OVER8)
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
#endif /* USART_OverSampling_Feature */
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR1 Configuration -----------------------
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
*/
#if defined(USART_CR1_OVER8)
MODIFY_REG(USARTx->CR1,
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
#else
MODIFY_REG(USARTx->CR1,
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
USART_CR1_TE | USART_CR1_RE),
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection));
#endif /* USART_OverSampling_Feature */
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Stop bits) with parameters:
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
*/
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
/*---------------------------- USART CR3 Configuration -----------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
/*---------------------------- USART BRR Configuration -----------------------
* Retrieve Clock frequency used for USART Peripheral
*/
LL_RCC_GetSystemClocksFreq(&rcc_clocks);
if (USARTx == USART1)
{
periphclk = rcc_clocks.PCLK2_Frequency;
}
else if (USARTx == USART2)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#if defined(USART3)
else if (USARTx == USART3)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* USART3 */
#if defined(UART4)
else if (USARTx == UART4)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* UART4 */
#if defined(UART5)
else if (USARTx == UART5)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
#endif /* UART5 */
else
{
/* Nothing to do, as error code is already assigned to ERROR value */
}
/* Configure the USART Baud Rate :
- valid baud rate value (different from 0) is required
- Peripheral clock as returned by RCC service, should be valid (different from 0).
*/
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
&& (USART_InitStruct->BaudRate != 0U))
{
status = SUCCESS;
#if defined(USART_CR1_OVER8)
LL_USART_SetBaudRate(USARTx,
periphclk,
USART_InitStruct->OverSampling,
USART_InitStruct->BaudRate);
#else
LL_USART_SetBaudRate(USARTx,
periphclk,
USART_InitStruct->BaudRate);
#endif /* USART_OverSampling_Feature */
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
return (status);
}
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
{
/* Set USART_InitStruct fields to default values */
USART_InitStruct->BaudRate = 9600U;
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
#if defined(USART_CR1_OVER8)
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
#endif /* USART_OverSampling_Feature */
}
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check USART Instance and Clock signal output parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR2 Configuration -----------------------*/
/* If Clock signal has to be output */
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
{
/* Deactivate Clock signal delivery :
* - Disable Clock Output: USART_CR2_CLKEN cleared
*/
LL_USART_DisableSCLKOutput(USARTx);
}
else
{
/* Ensure USART instance is USART capable */
assert_param(IS_USART_INSTANCE(USARTx));
/* Check clock related parameters */
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Clock signal related bits) with parameters:
* - Enable Clock Output: USART_CR2_CLKEN set
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
*/
MODIFY_REG(USARTx->CR2,
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
}
/* Else (USART not in Disabled state => return ERROR */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f1xx_ll_utils.c
* @author MCD Application Team
* @brief UTILS LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_system.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F1xx_LL_Driver
* @{
*/
/** @addtogroup UTILS_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
/* Defines used for PLL range */
#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
/* Defines used for HSE range */
#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
#if defined(FLASH_ACR_LATENCY)
#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
#else
/*!< No Latency Configuration in this device */
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Macros
* @{
*/
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
#if defined(RCC_CFGR_PLLMULL6_5)
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
#else
#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_3) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_4) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_5) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_6) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_7) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_8) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_9) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_10) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_11) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_12) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_13) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_14) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_15) \
|| ((__VALUE__) == LL_RCC_PLL_MUL_16))
#endif /* RCC_CFGR_PLLMULL6_5 */
#if defined(RCC_CFGR2_PREDIV1)
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
#else
#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UTILS_LL_Exported_Functions
* @{
*/
/** @addtogroup UTILS_LL_EF_DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
* @note When a RTOS is used, it is recommended to avoid changing the Systick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* on SysTick counter flag
* @note When a RTOS is used, it is recommended to avoid using blocking delay
* and use rather osDelay service.
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
/* Add this code to indicate that local variable is not used */
((void)tmp);
/* Add a period to guaranty minimum wait */
if (Delay < LL_MAX_DELAY)
{
Delay++;
}
while (Delay)
{
if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
{
Delay--;
}
}
}
/**
* @}
*/
/** @addtogroup UTILS_EF_SYSTEM
* @brief System Configuration functions
*
@verbatim
===============================================================================
##### System Configuration functions #####
===============================================================================
[..]
System, AHB and APB buses clocks configuration
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
@endverbatim
@internal
Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
(++) +-----------------------------------------------+
(++) | Latency | SYSCLK clock frequency (MHz) |
(++) |---------------|-------------------------------|
(++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
(++) |---------------|-------------------------------|
(++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
(++) |---------------|-------------------------------|
(++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
(++) +-----------------------------------------------+
@endinternal
* @{
*/
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
}
/**
* @brief This function configures system clock with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed 72MHz
* @note FLASH latency can be modified through this function.
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/* Check PREDIV value */
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
/* Force PREDIV value to 2 */
UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
/* Enable HSI if not enabled */
if (LL_RCC_HSI_IsReady() != 1U)
{
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1U)
{
/* Wait for HSI ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @brief This function configures system clock with HSE as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
* - PREDIV: Set to 2 for few devices
* - PLLMUL: The application software must set correctly the PLL multiplication factor to
* not exceed @ref UTILS_PLL_OUTPUT_MAX
* @note FLASH latency can be modified through this function.
* @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if (UTILS_PLL_IsBusy() == SUCCESS)
{
assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
/* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1U)
{
/* Check if need to enable HSE bypass feature or not */
if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
{
LL_RCC_HSE_EnableBypass();
}
else
{
LL_RCC_HSE_DisableBypass();
}
/* Enable HSE */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1U)
{
/* Wait for HSE ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @param Frequency SYSCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
#if defined(FLASH_ACR_LATENCY)
static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
{
ErrorStatus status = SUCCESS;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
/* Frequency cannot be equal to 0 */
if (Frequency == 0U)
{
status = ERROR;
}
else
{
if (Frequency > UTILS_LATENCY2_FREQ)
{
/* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if (Frequency > UTILS_LATENCY1_FREQ)
{
/* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
}
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (LL_FLASH_GetLatency() != latency)
{
status = ERROR;
}
}
return status;
}
#endif /* FLASH_ACR_LATENCY */
/**
* @brief Function to check that PLL can be modified
* @param PLL_InputFrequency PLL input frequency (in Hz)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
/* Check different PLL parameters according to RM */
#if defined (RCC_CFGR2_PREDIV1)
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
#else
pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
#endif /*RCC_CFGR2_PREDIV1SRC*/
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
}
/**
* @brief Function to check that PLL can be modified
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
ErrorStatus status = SUCCESS;
/* Check if PLL is busy*/
if (LL_RCC_PLL_IsReady() != 0U)
{
/* PLL configuration cannot be modified */
status = ERROR;
}
#if defined(RCC_PLL2_SUPPORT)
/* Check if PLL2 is busy*/
if (LL_RCC_PLL2_IsReady() != 0U)
{
/* PLL2 configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLL2_SUPPORT */
#if defined(RCC_PLLI2S_SUPPORT)
/* Check if PLLI2S is busy*/
if (LL_RCC_PLLI2S_IsReady() != 0U)
{
/* PLLI2S configuration cannot be modified */
status = ERROR;
}
#endif /* RCC_PLLI2S_SUPPORT */
return status;
}
/**
* @brief Function to enable PLL and switch system clock to PLL
* @param SYSCLK_Frequency SYSCLK frequency
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
#if defined(FLASH_ACR_LATENCY)
uint32_t sysclk_frequency_current = 0U;
#endif /* FLASH_ACR_LATENCY */
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
#if defined(FLASH_ACR_LATENCY)
/* Calculate current SYSCLK frequency */
sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
#endif /* FLASH_ACR_LATENCY */
/* Increasing the number of wait states because of higher CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current < SYSCLK_Frequency)
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update system clock configuration */
if (status == SUCCESS)
{
#if defined(RCC_PLL2_SUPPORT)
if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
{
/* Enable PLL2 */
LL_RCC_PLL2_Enable();
while (LL_RCC_PLL2_IsReady() != 1U)
{
/* Wait for PLL2 ready */
}
}
#endif /* RCC_PLL2_SUPPORT */
/* Enable PLL */
LL_RCC_PLL_Enable();
while (LL_RCC_PLL_IsReady() != 1U)
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
}
/* Decreasing the number of wait states because of lower CPU frequency */
#if defined (FLASH_ACR_LATENCY)
if (sysclk_frequency_current > SYSCLK_Frequency)
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(SYSCLK_Frequency);
}
#endif /* FLASH_ACR_LATENCY */
/* Update SystemCoreClock variable */
if (status == SUCCESS)
{
LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

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// <<< Use Configuration Wizard in Context Menu >>>
// <h> Debug MCU Configuration
// <o0.0> DBG_SLEEP
// <i> Debug Sleep Mode
// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
// <o0.1> DBG_STOP
// <i> Debug Stop Mode
// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.2> DBG_STANDBY
// <i> Debug Standby Mode
// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
// <o0.8> DBG_IWDG_STOP
// <i> Debug independent watchdog stopped when core is halted
// <i> 0: The watchdog counter clock continues even if the core is halted
// <i> 1: The watchdog counter clock is stopped when the core is halted
// <o0.9> DBG_WWDG_STOP
// <i> Debug window watchdog stopped when core is halted
// <i> 0: The window watchdog counter clock continues even if the core is halted
// <i> 1: The window watchdog counter clock is stopped when the core is halted
// <o0.10> DBG_TIM1_STOP
// <i> Timer 1 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.11> DBG_TIM2_STOP
// <i> Timer 2 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.12> DBG_TIM3_STOP
// <i> Timer 3 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.13> DBG_TIM4_STOP
// <i> Timer 4 counter stopped when core is halted
// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
// <o0.14> DBG_CAN1_STOP
// <i> Debug CAN1 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN1 receive registers are frozen
// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
// <i> I2C1 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
// <i> I2C2 SMBUS timeout mode stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: The SMBUS timeout is frozen
// <o0.17> DBG_TIM8_STOP
// <i> Timer 8 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.18> DBG_TIM5_STOP
// <i> Timer 5 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.19> DBG_TIM6_STOP
// <i> Timer 6 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.20> DBG_TIM7_STOP
// <i> Timer 7 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.21> DBG_CAN2_STOP
// <i> Debug CAN2 stopped when Core is halted
// <i> 0: Same behavior as in normal mode
// <i> 1: CAN2 receive registers are frozen
// <o0.25> DBG_TIM12_STOP
// <i> Timer 12 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.26> DBG_TIM13_STOP
// <i> Timer 13 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.27> DBG_TIM14_STOP
// <i> Timer 14 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.28> DBG_TIM9_STOP
// <i> Timer 9 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.29> DBG_TIM10_STOP
// <i> Timer 10 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// <o0.30> DBG_TIM11_STOP
// <i> Timer 11 counter stopped when core is halted
// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
// </h>
DbgMCU_CR = 0x00000007;
// <<< end of configuration section >>>

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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

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[EXTDLL]
Count=0

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MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.build_log.htm Normal file
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<html>
<body>
<pre>
<h1>µVision Build Log</h1>
<h2>Tool Versions:</h2>
IDE-Version: µVision V5.23.0.0
Copyright (C) 2017 ARM Ltd and ARM Germany GmbH. All rights reserved.
License Information: Thierry Thierry, INSA, LIC=----
Tool Versions:
Toolchain: MDK-Lite Version: 5.23
Toolchain Path: C:\Keil_v5\ARM\ARMCC\Bin
C Compiler: Armcc.exe V5.06 update 4 (build 422)
Assembler: Armasm.exe V5.06 update 4 (build 422)
Linker/Locator: ArmLink.exe V5.06 update 4 (build 422)
Library Manager: ArmAr.exe V5.06 update 4 (build 422)
Hex Converter: FromElf.exe V5.06 update 4 (build 422)
CPU DLL: SARMCM3.DLL V5.23
Dialog DLL: DARMSTM.DLL V1.68.0.0
Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V2.0.18.0
Dialog DLL: TARMSTM.DLL V1.66.0.0
<h2>Project:</h2>
D:\Thierry\2019_2020\Periph\PrepaPeriph\ProjetsKEIL\Nouveau dossier\DerLL\ProjKEIL_Chrono_TIM_IT_LL\MDK-ARM\Project.uvprojx
Project File Date: 09/20/2019
<h2>Output:</h2>
*** Using Compiler 'V5.06 update 4 (build 422)', folder: 'C:\Keil_v5\ARM\ARMCC\Bin'
Rebuild target 'Simulateur'
compiling Chrono.c...
compiling MyTimer.c...
compiling main.c...
compiling stm32f1xx_ll_rcc.c...
compiling stm32f1xx_ll_utils.c...
assembling startup_stm32f103xb.s...
compiling stm32f1xx_ll_tim.c...
compiling system_stm32f1xx.c...
linking...
Program Size: Code=1456 RO-data=268 RW-data=28 ZI-data=1028
"NUCLEO-F103RB\NUCLEO-F103RB.axf" - 0 Error(s), 0 Warning(s).
<h2>Software Packages used:</h2>
Package Vendor: ARM
http://www.keil.com/pack/ARM.CMSIS.5.0.1.pack
ARM::CMSIS:CORE:5.0.1
CMSIS (Cortex Microcontroller Software Interface Standard)
* Component: CORE Version: 5.0.1
<h2>Collection of Component include folders:</h2>
.\RTE\_Simulateur
C:\Keil_v5\ARM\PACK\ARM\CMSIS\5.0.1\CMSIS\Include
C:\Keil_v5\ARM\PACK\Keil\STM32F1xx_DFP\2.2.0\Device\Include
<h2>Collection of Component Files used:</h2>
* Component: ARM::CMSIS:CORE:5.0.1
Build Time Elapsed: 00:00:04
</pre>
</body>
</html>

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Component: ARM Compiler 5.06 update 4 (build 422) Tool: armlink [4d35d2]
==============================================================================
Section Cross References
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_Init1msTick) for LL_Init1msTick
main.o(i.SystemClock_Config) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
main.o(i.main) refers to main.o(i.SystemClock_Config) for SystemClock_Config
main.o(i.main) refers to chrono.o(i.Chrono_Conf) for Chrono_Conf
main.o(i.main) refers to chrono.o(i.Chrono_Start) for Chrono_Start
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_Conf) for MyTimer_Conf
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_IT_Conf) for MyTimer_IT_Conf
chrono.o(i.Chrono_Conf) refers to mytimer.o(i.MyTimer_IT_Enable) for MyTimer_IT_Enable
chrono.o(i.Chrono_Conf) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Conf) refers to chrono.o(i.Chrono_Task_10ms) for Chrono_Task_10ms
chrono.o(i.Chrono_Read) refers to chrono.o(.data) for Chrono_Time
chrono.o(i.Chrono_Reset) refers to mytimer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Reset) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Start) refers to mytimer.o(i.MyTimer_Start) for MyTimer_Start
chrono.o(i.Chrono_Start) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Stop) refers to mytimer.o(i.MyTimer_Stop) for MyTimer_Stop
chrono.o(i.Chrono_Stop) refers to chrono.o(.data) for Chrono_Timer
chrono.o(i.Chrono_Task_10ms) refers to chrono.o(.data) for Chrono_Time
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_APB1_GRP1_EnableClock) for LL_APB1_GRP1_EnableClock
mytimer.o(i.MyTimer_Conf) refers to stm32f1xx_ll_tim.o(i.LL_TIM_Init) for LL_TIM_Init
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_Conf) refers to mytimer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
mytimer.o(i.MyTimer_IT_Conf) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_IT_Conf) refers to mytimer.o(.data) for Ptr_ItFct_TIM1
mytimer.o(i.MyTimer_IT_Disable) refers to mytimer.o(i.LL_TIM_DisableIT_UPDATE) for LL_TIM_DisableIT_UPDATE
mytimer.o(i.MyTimer_Stop) refers to mytimer.o(i.LL_TIM_DisableCounter) for LL_TIM_DisableCounter
mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM1_UP_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM1
mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM2_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM2
mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM3_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM3
mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(i.LL_TIM_ClearFlag_UPDATE) for LL_TIM_ClearFlag_UPDATE
mytimer.o(i.TIM4_IRQHandler) refers to mytimer.o(.data) for Ptr_ItFct_TIM4
stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) for RCC_GetSystemClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) for RCC_GetHCLKClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) for RCC_GetPCLK1ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) for RCC_GetPCLK2ClockFreq
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq) refers to system_stm32f1xx.o(.constdata) for APBPrescTable
stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq) refers to stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS) for RCC_PLL_GetFreqDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady) for LL_RCC_HSE_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) for UTILS_PLL_IsBusy
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) for UTILS_GetPLLOutputFrequency
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady) for LL_RCC_HSI_IsReady
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS) for LL_RCC_PLL_ConfigDomain_SYS
stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI) refers to stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) for UTILS_EnablePLLAndSwitchSystem
stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency) for UTILS_SetFlashLatency
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock) for LL_SetSystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem) refers to system_stm32f1xx.o(.data) for SystemCoreClock
stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy) refers to stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady) for LL_RCC_PLL_IsReady
stm32f1xx_ll_tim.o(i.IC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.IC4Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset) for LL_APB1_GRP1_ForceReset
stm32f1xx_ll_tim.o(i.LL_TIM_DeInit) refers to stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset) for LL_APB1_GRP1_ReleaseReset
stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC1Config) for IC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC2Config) for IC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC3Config) for IC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init) refers to stm32f1xx_ll_tim.o(i.IC4Config) for IC4Config
stm32f1xx_ll_tim.o(i.LL_TIM_Init) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC1Config) for OC1Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC2Config) for OC2Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC3Config) for OC3Config
stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init) refers to stm32f1xx_ll_tim.o(i.OC4Config) for OC4Config
stm32f1xx_ll_tim.o(i.OC1Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC2Config) refers to stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2) for LL_TIM_OC_SetCompareCH2
stm32f1xx_ll_tim.o(i.OC3Config) refers to main.o(i.assert_failed) for assert_failed
stm32f1xx_ll_tim.o(i.OC4Config) refers to main.o(i.assert_failed) for assert_failed
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.data) for SystemCoreClock
system_stm32f1xx.o(i.SystemCoreClockUpdate) refers to system_stm32f1xx.o(.constdata) for AHBPrescTable
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(STACK) for __initial_sp
startup_stm32f103xb.o(RESET) refers to startup_stm32f103xb.o(.text) for Reset_Handler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM2_IRQHandler) for TIM2_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM3_IRQHandler) for TIM3_IRQHandler
startup_stm32f103xb.o(RESET) refers to mytimer.o(i.TIM4_IRQHandler) for TIM4_IRQHandler
startup_stm32f103xb.o(.text) refers to system_stm32f1xx.o(i.SystemInit) for SystemInit
startup_stm32f103xb.o(.text) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry10a.o(.ARM.Collect$$$$0000000D) for __rt_final_cpp
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry11a.o(.ARM.Collect$$$$0000000F) for __rt_final_exit
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry7b.o(.ARM.Collect$$$$00000008) for _main_clock
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry8b.o(.ARM.Collect$$$$0000000A) for _main_cpp_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry9a.o(.ARM.Collect$$$$0000000B) for _main_init
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry5.o(.ARM.Collect$$$$00000004) for _main_scatterload
entry.o(.ARM.Collect$$$$00000000) refers (Special) to entry2.o(.ARM.Collect$$$$00000001) for _main_stk
entry2.o(.ARM.Collect$$$$00000001) refers to entry2.o(.ARM.Collect$$$$00002712) for __lit__00000000
entry2.o(.ARM.Collect$$$$00002712) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to startup_stm32f103xb.o(STACK) for __initial_sp
entry2.o(__vectab_stack_and_reset_area) refers to entry.o(.ARM.Collect$$$$00000000) for __main
entry5.o(.ARM.Collect$$$$00000004) refers to init.o(.text) for __scatterload
entry9a.o(.ARM.Collect$$$$0000000B) refers to main.o(i.main) for main
entry9b.o(.ARM.Collect$$$$0000000C) refers to main.o(i.main) for main
init.o(.text) refers to entry5.o(.ARM.Collect$$$$00000004) for __main_after_scatterload
==============================================================================
Removing Unused input sections from the image.
Removing main.o(.rev16_text), (4 bytes).
Removing main.o(.revsh_text), (4 bytes).
Removing main.o(.rrx_text), (6 bytes).
Removing chrono.o(.rev16_text), (4 bytes).
Removing chrono.o(.revsh_text), (4 bytes).
Removing chrono.o(.rrx_text), (6 bytes).
Removing chrono.o(i.Chrono_Read), (8 bytes).
Removing chrono.o(i.Chrono_Reset), (32 bytes).
Removing chrono.o(i.Chrono_Stop), (16 bytes).
Removing mytimer.o(.rev16_text), (4 bytes).
Removing mytimer.o(.revsh_text), (4 bytes).
Removing mytimer.o(.rrx_text), (6 bytes).
Removing mytimer.o(i.MyTimer_IT_Disable), (12 bytes).
Removing mytimer.o(i.MyTimer_Stop), (12 bytes).
Removing mytimer.o(.constdata), (35 bytes).
Removing stm32f1xx_ll_rcc.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_rcc.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_DeInit), (152 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetADCClockFreq), (124 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetSystemClocksFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_GetUSBClockFreq), (120 bytes).
Removing stm32f1xx_ll_rcc.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetHCLKClockFreq), (32 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK1ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetPCLK2ClockFreq), (36 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_GetSystemClockFreq), (60 bytes).
Removing stm32f1xx_ll_rcc.o(i.RCC_PLL_GetFreqDomain_SYS), (88 bytes).
Removing stm32f1xx_ll_utils.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_utils.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSE), (260 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_PLL_ConfigSystemClock_HSI), (104 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSE_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_HSI_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_ConfigDomain_SYS), (28 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_RCC_PLL_IsReady), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.LL_mDelay), (40 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_EnablePLLAndSwitchSystem), (416 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_GetPLLOutputFrequency), (228 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_PLL_IsBusy), (16 bytes).
Removing stm32f1xx_ll_utils.o(i.UTILS_SetFlashLatency), (80 bytes).
Removing stm32f1xx_ll_tim.o(.rev16_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.revsh_text), (4 bytes).
Removing stm32f1xx_ll_tim.o(.rrx_text), (6 bytes).
Removing stm32f1xx_ll_tim.o(i.IC1Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC2Config), (376 bytes).
Removing stm32f1xx_ll_tim.o(i.IC3Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.IC4Config), (380 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ForceReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_APB1_GRP1_ReleaseReset), (16 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_Init), (312 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_BDTR_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_DeInit), (192 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_Init), (688 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_ENCODER_StructInit), (36 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_Init), (396 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_HALLSENSOR_StructInit), (12 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_IC_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_Init), (92 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_SetCompareCH2), (4 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_OC_StructInit), (20 bytes).
Removing stm32f1xx_ll_tim.o(i.LL_TIM_StructInit), (18 bytes).
Removing stm32f1xx_ll_tim.o(i.OC1Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC2Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC3Config), (404 bytes).
Removing stm32f1xx_ll_tim.o(i.OC4Config), (372 bytes).
Removing stm32f1xx_ll_tim.o(.constdata), (35 bytes).
Removing system_stm32f1xx.o(.rev16_text), (4 bytes).
Removing system_stm32f1xx.o(.revsh_text), (4 bytes).
Removing system_stm32f1xx.o(.rrx_text), (6 bytes).
Removing system_stm32f1xx.o(i.SystemCoreClockUpdate), (164 bytes).
Removing system_stm32f1xx.o(.constdata), (24 bytes).
Removing startup_stm32f103xb.o(HEAP), (512 bytes).
75 unused section(s) (total 7894 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../Src/main.c 0x00000000 Number 0 main.o ABSOLUTE
../Src/system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry5.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry9a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry8a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry10b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7b.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry7a.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry2.o ABSOLUTE
../clib/microlib/init/entry.s 0x00000000 Number 0 entry11b.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\LLDrivers\src\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\MyDrivers\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
..\Services\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
..\Src\main.c 0x00000000 Number 0 main.o ABSOLUTE
..\Src\system_stm32f1xx.c 0x00000000 Number 0 system_stm32f1xx.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_rcc.c 0x00000000 Number 0 stm32f1xx_ll_rcc.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_tim.c 0x00000000 Number 0 stm32f1xx_ll_tim.o ABSOLUTE
..\\LLDrivers\\src\\stm32f1xx_ll_utils.c 0x00000000 Number 0 stm32f1xx_ll_utils.o ABSOLUTE
..\\MyDrivers\\MyTimer.c 0x00000000 Number 0 mytimer.o ABSOLUTE
..\\Services\\Chrono.c 0x00000000 Number 0 chrono.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
handlers.s 0x00000000 Number 0 handlers.o ABSOLUTE
init.s 0x00000000 Number 0 init.o ABSOLUTE
startup_stm32f103xb.s 0x00000000 Number 0 startup_stm32f103xb.o ABSOLUTE
RESET 0x08000000 Section 236 startup_stm32f103xb.o(RESET)
.ARM.Collect$$$$00000000 0x080000ec Section 0 entry.o(.ARM.Collect$$$$00000000)
.ARM.Collect$$$$00000001 0x080000ec Section 4 entry2.o(.ARM.Collect$$$$00000001)
.ARM.Collect$$$$00000004 0x080000f0 Section 4 entry5.o(.ARM.Collect$$$$00000004)
.ARM.Collect$$$$00000008 0x080000f4 Section 0 entry7b.o(.ARM.Collect$$$$00000008)
.ARM.Collect$$$$0000000A 0x080000f4 Section 0 entry8b.o(.ARM.Collect$$$$0000000A)
.ARM.Collect$$$$0000000B 0x080000f4 Section 8 entry9a.o(.ARM.Collect$$$$0000000B)
.ARM.Collect$$$$0000000D 0x080000fc Section 0 entry10a.o(.ARM.Collect$$$$0000000D)
.ARM.Collect$$$$0000000F 0x080000fc Section 0 entry11a.o(.ARM.Collect$$$$0000000F)
.ARM.Collect$$$$00002712 0x080000fc Section 4 entry2.o(.ARM.Collect$$$$00002712)
__lit__00000000 0x080000fc Data 4 entry2.o(.ARM.Collect$$$$00002712)
.text 0x08000100 Section 36 startup_stm32f103xb.o(.text)
.text 0x08000124 Section 36 init.o(.text)
i.Chrono_Conf 0x08000148 Section 0 chrono.o(i.Chrono_Conf)
i.Chrono_Start 0x0800018c Section 0 chrono.o(i.Chrono_Start)
i.Chrono_Task_10ms 0x0800019c Section 0 chrono.o(i.Chrono_Task_10ms)
i.LL_APB1_GRP1_EnableClock 0x080001e4 Section 0 mytimer.o(i.LL_APB1_GRP1_EnableClock)
LL_APB1_GRP1_EnableClock 0x080001e5 Thumb Code 24 mytimer.o(i.LL_APB1_GRP1_EnableClock)
i.LL_Init1msTick 0x08000200 Section 0 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
i.LL_SetSystemCoreClock 0x0800021c Section 0 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
i.LL_TIM_ClearFlag_UPDATE 0x08000228 Section 0 mytimer.o(i.LL_TIM_ClearFlag_UPDATE)
LL_TIM_ClearFlag_UPDATE 0x08000229 Thumb Code 8 mytimer.o(i.LL_TIM_ClearFlag_UPDATE)
i.LL_TIM_DisableCounter 0x08000230 Section 0 mytimer.o(i.LL_TIM_DisableCounter)
LL_TIM_DisableCounter 0x08000231 Thumb Code 10 mytimer.o(i.LL_TIM_DisableCounter)
i.LL_TIM_DisableIT_UPDATE 0x0800023a Section 0 mytimer.o(i.LL_TIM_DisableIT_UPDATE)
LL_TIM_DisableIT_UPDATE 0x0800023b Thumb Code 10 mytimer.o(i.LL_TIM_DisableIT_UPDATE)
i.LL_TIM_Init 0x08000244 Section 0 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
i.MyTimer_Conf 0x08000358 Section 0 mytimer.o(i.MyTimer_Conf)
i.MyTimer_IT_Conf 0x080003dc Section 0 mytimer.o(i.MyTimer_IT_Conf)
i.MyTimer_IT_Enable 0x0800049c Section 0 mytimer.o(i.MyTimer_IT_Enable)
i.MyTimer_Start 0x080004aa Section 0 mytimer.o(i.MyTimer_Start)
i.SystemClock_Config 0x080004b8 Section 0 main.o(i.SystemClock_Config)
i.SystemInit 0x080005a8 Section 0 system_stm32f1xx.o(i.SystemInit)
i.TIM1_UP_IRQHandler 0x08000600 Section 0 mytimer.o(i.TIM1_UP_IRQHandler)
i.TIM2_IRQHandler 0x08000618 Section 0 mytimer.o(i.TIM2_IRQHandler)
i.TIM3_IRQHandler 0x08000630 Section 0 mytimer.o(i.TIM3_IRQHandler)
i.TIM4_IRQHandler 0x08000648 Section 0 mytimer.o(i.TIM4_IRQHandler)
i.__scatterload_copy 0x08000660 Section 14 handlers.o(i.__scatterload_copy)
i.__scatterload_null 0x0800066e Section 2 handlers.o(i.__scatterload_null)
i.__scatterload_zeroinit 0x08000670 Section 14 handlers.o(i.__scatterload_zeroinit)
i.assert_failed 0x0800067e Section 0 main.o(i.assert_failed)
i.main 0x08000684 Section 0 main.o(i.main)
.data 0x20000000 Section 8 chrono.o(.data)
Chrono_Time 0x20000000 Data 3 chrono.o(.data)
Chrono_Timer 0x20000004 Data 4 chrono.o(.data)
.data 0x20000008 Section 16 mytimer.o(.data)
.data 0x20000018 Section 4 system_stm32f1xx.o(.data)
STACK 0x20000020 Section 1024 startup_stm32f103xb.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv4$P$D$K$B$S$PE$A:L22UL41UL21$X:L11$S22US41US21$IEEE1$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$EBA8$MICROLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_use_no_argv 0x00000000 Number 0 main.o ABSOLUTE
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__decompress - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_microlib_exit - Undefined Weak Reference
__Vectors_Size 0x000000ec Number 0 startup_stm32f103xb.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_stm32f103xb.o(RESET)
__Vectors_End 0x080000ec Data 0 startup_stm32f103xb.o(RESET)
__main 0x080000ed Thumb Code 0 entry.o(.ARM.Collect$$$$00000000)
_main_stk 0x080000ed Thumb Code 0 entry2.o(.ARM.Collect$$$$00000001)
_main_scatterload 0x080000f1 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
__main_after_scatterload 0x080000f5 Thumb Code 0 entry5.o(.ARM.Collect$$$$00000004)
_main_clock 0x080000f5 Thumb Code 0 entry7b.o(.ARM.Collect$$$$00000008)
_main_cpp_init 0x080000f5 Thumb Code 0 entry8b.o(.ARM.Collect$$$$0000000A)
_main_init 0x080000f5 Thumb Code 0 entry9a.o(.ARM.Collect$$$$0000000B)
__rt_final_cpp 0x080000fd Thumb Code 0 entry10a.o(.ARM.Collect$$$$0000000D)
__rt_final_exit 0x080000fd Thumb Code 0 entry11a.o(.ARM.Collect$$$$0000000F)
Reset_Handler 0x08000101 Thumb Code 8 startup_stm32f103xb.o(.text)
NMI_Handler 0x08000109 Thumb Code 2 startup_stm32f103xb.o(.text)
HardFault_Handler 0x0800010b Thumb Code 2 startup_stm32f103xb.o(.text)
MemManage_Handler 0x0800010d Thumb Code 2 startup_stm32f103xb.o(.text)
BusFault_Handler 0x0800010f Thumb Code 2 startup_stm32f103xb.o(.text)
UsageFault_Handler 0x08000111 Thumb Code 2 startup_stm32f103xb.o(.text)
SVC_Handler 0x08000113 Thumb Code 2 startup_stm32f103xb.o(.text)
DebugMon_Handler 0x08000115 Thumb Code 2 startup_stm32f103xb.o(.text)
PendSV_Handler 0x08000117 Thumb Code 2 startup_stm32f103xb.o(.text)
SysTick_Handler 0x08000119 Thumb Code 2 startup_stm32f103xb.o(.text)
ADC1_2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_RX1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
CAN1_SCE_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel6_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
DMA1_Channel7_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI15_10_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI4_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
EXTI9_5_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C1_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_ER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
I2C2_EV_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
PVD_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RCC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_Alarm_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
RTC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
SPI2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TAMPER_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_BRK_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
TIM1_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART1_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART2_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USART3_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USBWakeUp_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_HP_CAN1_TX_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
USB_LP_CAN1_RX0_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
WWDG_IRQHandler 0x0800011b Thumb Code 0 startup_stm32f103xb.o(.text)
__scatterload 0x08000125 Thumb Code 28 init.o(.text)
__scatterload_rt2 0x08000125 Thumb Code 0 init.o(.text)
Chrono_Conf 0x08000149 Thumb Code 54 chrono.o(i.Chrono_Conf)
Chrono_Start 0x0800018d Thumb Code 12 chrono.o(i.Chrono_Start)
Chrono_Task_10ms 0x0800019d Thumb Code 68 chrono.o(i.Chrono_Task_10ms)
LL_Init1msTick 0x08000201 Thumb Code 28 stm32f1xx_ll_utils.o(i.LL_Init1msTick)
LL_SetSystemCoreClock 0x0800021d Thumb Code 6 stm32f1xx_ll_utils.o(i.LL_SetSystemCoreClock)
LL_TIM_Init 0x08000245 Thumb Code 228 stm32f1xx_ll_tim.o(i.LL_TIM_Init)
MyTimer_Conf 0x08000359 Thumb Code 118 mytimer.o(i.MyTimer_Conf)
MyTimer_IT_Conf 0x080003dd Thumb Code 158 mytimer.o(i.MyTimer_IT_Conf)
MyTimer_IT_Enable 0x0800049d Thumb Code 14 mytimer.o(i.MyTimer_IT_Enable)
MyTimer_Start 0x080004ab Thumb Code 14 mytimer.o(i.MyTimer_Start)
SystemClock_Config 0x080004b9 Thumb Code 226 main.o(i.SystemClock_Config)
SystemInit 0x080005a9 Thumb Code 70 system_stm32f1xx.o(i.SystemInit)
TIM1_UP_IRQHandler 0x08000601 Thumb Code 16 mytimer.o(i.TIM1_UP_IRQHandler)
TIM2_IRQHandler 0x08000619 Thumb Code 18 mytimer.o(i.TIM2_IRQHandler)
TIM3_IRQHandler 0x08000631 Thumb Code 16 mytimer.o(i.TIM3_IRQHandler)
TIM4_IRQHandler 0x08000649 Thumb Code 16 mytimer.o(i.TIM4_IRQHandler)
__scatterload_copy 0x08000661 Thumb Code 14 handlers.o(i.__scatterload_copy)
__scatterload_null 0x0800066f Thumb Code 2 handlers.o(i.__scatterload_null)
__scatterload_zeroinit 0x08000671 Thumb Code 14 handlers.o(i.__scatterload_zeroinit)
assert_failed 0x0800067f Thumb Code 4 main.o(i.assert_failed)
main 0x08000685 Thumb Code 18 main.o(i.main)
Region$$Table$$Base 0x0800069c Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x080006bc Number 0 anon$$obj.o(Region$$Table)
Ptr_ItFct_TIM1 0x20000008 Data 4 mytimer.o(.data)
Ptr_ItFct_TIM2 0x2000000c Data 4 mytimer.o(.data)
Ptr_ItFct_TIM3 0x20000010 Data 4 mytimer.o(.data)
Ptr_ItFct_TIM4 0x20000014 Data 4 mytimer.o(.data)
SystemCoreClock 0x20000018 Data 4 system_stm32f1xx.o(.data)
__initial_sp 0x20000420 Data 0 startup_stm32f103xb.o(STACK)
==============================================================================
Memory Map of the image
Image Entry point : 0x080000ed
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000006d8, Max: 0x00020000, ABSOLUTE)
Execution Region ER_IROM1 (Base: 0x08000000, Size: 0x000006bc, Max: 0x00020000, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x08000000 0x000000ec Data RO 624 RESET startup_stm32f103xb.o
0x080000ec 0x00000000 Code RO 629 * .ARM.Collect$$$$00000000 mc_w.l(entry.o)
0x080000ec 0x00000004 Code RO 632 .ARM.Collect$$$$00000001 mc_w.l(entry2.o)
0x080000f0 0x00000004 Code RO 635 .ARM.Collect$$$$00000004 mc_w.l(entry5.o)
0x080000f4 0x00000000 Code RO 637 .ARM.Collect$$$$00000008 mc_w.l(entry7b.o)
0x080000f4 0x00000000 Code RO 639 .ARM.Collect$$$$0000000A mc_w.l(entry8b.o)
0x080000f4 0x00000008 Code RO 640 .ARM.Collect$$$$0000000B mc_w.l(entry9a.o)
0x080000fc 0x00000000 Code RO 642 .ARM.Collect$$$$0000000D mc_w.l(entry10a.o)
0x080000fc 0x00000000 Code RO 644 .ARM.Collect$$$$0000000F mc_w.l(entry11a.o)
0x080000fc 0x00000004 Code RO 633 .ARM.Collect$$$$00002712 mc_w.l(entry2.o)
0x08000100 0x00000024 Code RO 625 .text startup_stm32f103xb.o
0x08000124 0x00000024 Code RO 646 .text mc_w.l(init.o)
0x08000148 0x00000044 Code RO 78 i.Chrono_Conf chrono.o
0x0800018c 0x00000010 Code RO 81 i.Chrono_Start chrono.o
0x0800019c 0x00000048 Code RO 83 i.Chrono_Task_10ms chrono.o
0x080001e4 0x0000001c Code RO 137 i.LL_APB1_GRP1_EnableClock mytimer.o
0x08000200 0x0000001c Code RO 332 i.LL_Init1msTick stm32f1xx_ll_utils.o
0x0800021c 0x0000000c Code RO 339 i.LL_SetSystemCoreClock stm32f1xx_ll_utils.o
0x08000228 0x00000008 Code RO 138 i.LL_TIM_ClearFlag_UPDATE mytimer.o
0x08000230 0x0000000a Code RO 139 i.LL_TIM_DisableCounter mytimer.o
0x0800023a 0x0000000a Code RO 140 i.LL_TIM_DisableIT_UPDATE mytimer.o
0x08000244 0x00000114 Code RO 444 i.LL_TIM_Init stm32f1xx_ll_tim.o
0x08000358 0x00000084 Code RO 141 i.MyTimer_Conf mytimer.o
0x080003dc 0x000000c0 Code RO 142 i.MyTimer_IT_Conf mytimer.o
0x0800049c 0x0000000e Code RO 144 i.MyTimer_IT_Enable mytimer.o
0x080004aa 0x0000000e Code RO 145 i.MyTimer_Start mytimer.o
0x080004b8 0x000000f0 Code RO 4 i.SystemClock_Config main.o
0x080005a8 0x00000058 Code RO 589 i.SystemInit system_stm32f1xx.o
0x08000600 0x00000018 Code RO 147 i.TIM1_UP_IRQHandler mytimer.o
0x08000618 0x00000018 Code RO 148 i.TIM2_IRQHandler mytimer.o
0x08000630 0x00000018 Code RO 149 i.TIM3_IRQHandler mytimer.o
0x08000648 0x00000018 Code RO 150 i.TIM4_IRQHandler mytimer.o
0x08000660 0x0000000e Code RO 650 i.__scatterload_copy mc_w.l(handlers.o)
0x0800066e 0x00000002 Code RO 651 i.__scatterload_null mc_w.l(handlers.o)
0x08000670 0x0000000e Code RO 652 i.__scatterload_zeroinit mc_w.l(handlers.o)
0x0800067e 0x00000004 Code RO 5 i.assert_failed main.o
0x08000682 0x00000002 PAD
0x08000684 0x00000018 Code RO 6 i.main main.o
0x0800069c 0x00000020 Data RO 648 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Base: 0x20000000, Size: 0x00000420, Max: 0x00005000, ABSOLUTE)
Base Addr Size Type Attr Idx E Section Name Object
0x20000000 0x00000008 Data RW 84 .data chrono.o
0x20000008 0x00000010 Data RW 152 .data mytimer.o
0x20000018 0x00000004 Data RW 591 .data system_stm32f1xx.o
0x2000001c 0x00000004 PAD
0x20000020 0x00000400 Zero RW 622 STACK startup_stm32f103xb.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
156 22 0 8 0 2192 chrono.o
268 20 0 0 0 357020 main.o
504 82 0 16 0 59517 mytimer.o
36 8 236 0 1024 820 startup_stm32f103xb.o
276 48 0 0 0 29110 stm32f1xx_ll_tim.o
40 6 0 0 0 2213 stm32f1xx_ll_utils.o
88 18 0 4 0 1287 system_stm32f1xx.o
----------------------------------------------------------------------
1370 204 268 28 1028 452159 Object Totals
0 0 32 0 0 0 (incl. Generated)
2 0 0 0 4 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
0 0 0 0 0 0 entry.o
0 0 0 0 0 0 entry10a.o
0 0 0 0 0 0 entry11a.o
8 4 0 0 0 0 entry2.o
4 0 0 0 0 0 entry5.o
0 0 0 0 0 0 entry7b.o
0 0 0 0 0 0 entry8b.o
8 4 0 0 0 0 entry9a.o
30 0 0 0 0 0 handlers.o
36 8 0 0 0 68 init.o
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
0 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
86 16 0 0 0 68 mc_w.l
----------------------------------------------------------------------
86 16 0 0 0 68 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
1456 220 268 28 1028 451339 Grand Totals
1456 220 268 28 1028 451339 ELF Image Totals
1456 220 268 28 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 1724 ( 1.68kB)
Total RW Size (RW Data + ZI Data) 1056 ( 1.03kB)
Total ROM Size (Code + RO Data + RW Data) 1752 ( 1.71kB)
==============================================================================

15
MDK-ARM/NUCLEO-F103RB/NUCLEO-F103RB.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00020000 { ; load region size_region
ER_IROM1 0x08000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00005000 { ; RW data
.ANY (+RW +ZI)
}
}

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MDK-ARM/NUCLEO-F103RB/chrono.crf Normal file
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MDK-ARM/NUCLEO-F103RB/main.crf Normal file
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MDK-ARM/NUCLEO-F103RB/mytimer.crf Normal file
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MDK-ARM/NUCLEO-F103RB/stm32f1xx_it.crf Normal file
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2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_adc.d Normal file
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nucleo-f103rb\stm32f1xx_ll_adc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c
nucleo-f103rb\stm32f1xx_ll_adc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_crc.d Normal file
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nucleo-f103rb\stm32f1xx_ll_crc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c
nucleo-f103rb\stm32f1xx_ll_crc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_crc.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dac.d Normal file
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nucleo-f103rb\stm32f1xx_ll_dac.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c
nucleo-f103rb\stm32f1xx_ll_dac.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dac.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_dma.d Normal file
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nucleo-f103rb\stm32f1xx_ll_dma.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
nucleo-f103rb\stm32f1xx_ll_dma.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_exti.d Normal file
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nucleo-f103rb\stm32f1xx_ll_exti.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
nucleo-f103rb\stm32f1xx_ll_exti.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_gpio.d Normal file
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nucleo-f103rb\stm32f1xx_ll_gpio.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
nucleo-f103rb\stm32f1xx_ll_gpio.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_i2c.d Normal file
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nucleo-f103rb\stm32f1xx_ll_i2c.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c
nucleo-f103rb\stm32f1xx_ll_i2c.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_i2c.h

2
MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_pwr.d Normal file
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nucleo-f103rb\stm32f1xx_ll_pwr.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
nucleo-f103rb\stm32f1xx_ll_pwr.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h

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MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_rcc.crf Normal file
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MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_rtc.d Normal file
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nucleo-f103rb\stm32f1xx_ll_rtc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c
nucleo-f103rb\stm32f1xx_ll_rtc.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rtc.h

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nucleo-f103rb\stm32f1xx_ll_spi.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
nucleo-f103rb\stm32f1xx_ll_spi.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h

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nucleo-f103rb\stm32f1xx_ll_usart.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c
nucleo-f103rb\stm32f1xx_ll_usart.o: ../../../../Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_usart.h

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MDK-ARM/NUCLEO-F103RB/stm32f1xx_ll_utils.crf Normal file
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MDK-ARM/NUCLEO-F103RB/system_stm32f1xx.crf Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>NUCLEO-F103RB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>8000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath></ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>0</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>1</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=100,127,658,622,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U-O142 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>47</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219058</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\47</Expression>
</Bp>
<Bp>
<Number>1</Number>
<Type>0</Type>
<LineNumber>44</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219052</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\44</Expression>
</Bp>
</Breakpoint>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>Main_Time</ItemText>
</Ww>
</WatchWindow1>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Target>
<TargetName>Simulateur</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>8000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath></ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>18</CpuCode>
<DebugOpt>
<uSim>1</uSim>
<uTrg>0</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>1</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<nTsel>5</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGDARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=100,127,658,622,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name>-T0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>(105=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM))</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ST-LINKIII-KEIL_SWO</Key>
<Name>-U-O142 -O2254 -S0 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103RB$Flash\STM32F10x_128.FLM)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint>
<Bp>
<Number>0</Number>
<Type>0</Type>
<LineNumber>46</LineNumber>
<EnabledFlag>1</EnabledFlag>
<Address>134219406</Address>
<ByteObject>0</ByteObject>
<HtxType>0</HtxType>
<ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject>
<BreakByAccess>0</BreakByAccess>
<BreakIfRCount>1</BreakIfRCount>
<Filename>../Src/main.c</Filename>
<ExecCommand></ExecCommand>
<Expression>\\NUCLEO_F103RB\../Src/main.c\46</Expression>
</Bp>
</Breakpoint>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<DebugDescription>
<Enable>1</Enable>
<EnableLog>0</EnableLog>
<Protocol>2</Protocol>
<DbgClock>10000000</DbgClock>
</DebugDescription>
</TargetOption>
</Target>
<Group>
<GroupName>User Application</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>../Src/main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>User Services</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\Services\Chrono.c</PathWithFileName>
<FilenameWithoutPath>Chrono.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>MyDrivers</GroupName>
<tvExp>1</tvExp>
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<cbSel>0</cbSel>
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</ProjectOpt>

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MDK-ARM/Project.uvprojx Normal file
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@ -0,0 +1,935 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>NUCLEO-F103RB</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<TargetOption>
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<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
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<Linker></Linker>
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<InfinionOptionDll></InfinionOptionDll>
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<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F103RB$SVD\STM32F103xx.svd</SFDFile>
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<BinPath></BinPath>
<IncludePath></IncludePath>
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<TargetStatus>
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<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>NUCLEO-F103RB\</OutputDirectory>
<OutputName>NUCLEO-F103RB</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
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<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
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<SVCSIdString></SVCSIdString>
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<CommonProperty>
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<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>0</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DARMSTM.DLL</SimDlgDll>
<SimDlgDllArguments>-pSTM32F103RB</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
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<DebugOption>
<OPTHX>
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<Utilities>
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<DriverSelection>4107</DriverSelection>
</Flash1>
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<Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
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</Utilities>
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<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
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<AdsLsxf>1</AdsLsxf>
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<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
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<Size>0x0</Size>
</Ocm3>
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</Ocm4>
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<StartAddress>0x0</StartAddress>
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</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x20000</Size>
</IROM>
<XRAM>
<Type>0</Type>
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</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
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</OCR_RVCT1>
<OCR_RVCT2>
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</OCR_RVCT9>
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</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
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<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
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<vShortWch>1</vShortWch>
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<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--C99</MiscControls>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U,USE_FULL_ASSERT</Define>
<Undefine></Undefine>
<IncludePath>..\Inc;..\LLDrivers\inc;..\Services;..\MyDrivers</IncludePath>
</VariousControls>
</Cads>
<Aads>
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<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
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<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
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<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
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<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>User Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>../Src/main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>User Services</GroupName>
<Files>
<File>
<FileName>Chrono.c</FileName>
<FileType>1</FileType>
<FilePath>..\Services\Chrono.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>MyDrivers</GroupName>
<Files>
<File>
<FileName>MyTimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\MyDrivers\MyTimer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers/STM32f1xx_LL_Driver</GroupName>
<Files>
<File>
<FileName>stm32f1xx_ll_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_rcc.c</FilePath>
</File>
<File>
<FileName>stm32f1xx_ll_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_utils.c</FilePath>
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<FileName>stm32f1xx_ll_tim.c</FileName>
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<Group>
<GroupName>Doc</GroupName>
<Files>
<File>
<FileName>readme.txt</FileName>
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<FilePath>../readme.txt</FilePath>
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<GroupName>Drivers/CMSIS</GroupName>
<Files>
<File>
<FileName>system_stm32f1xx.c</FileName>
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<FilePath>../Src/system_stm32f1xx.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Example/MDK-ARM</GroupName>
<Files>
<File>
<FileName>startup_stm32f103xb.s</FileName>
<FileType>2</FileType>
<FilePath>startup_stm32f103xb.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
<Target>
<TargetName>Simulateur</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>STM32F103RB</Device>
<Vendor>STMicroelectronics</Vendor>
<PackID>Keil.STM32F1xx_DFP.2.2.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000-0x20004FFF) IROM(0x8000000-0x801FFFF) CLOCK(8000000) CPUTYPE("Cortex-M3")</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll></FlashDriverDll>
<DeviceId></DeviceId>
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<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
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<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:STM32F103RB$SVD\STM32F103xx.svd</SFDFile>
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<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
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<DBRegisterFilePath></DBRegisterFilePath>
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<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>NUCLEO-F103RB\</OutputDirectory>
<OutputName>NUCLEO-F103RB</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath></ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
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<BeforeCompile>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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</BeforeCompile>
<BeforeMake>
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<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
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<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>0</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments></SimDllArguments>
<SimDlgDll>DARMSTM.DLL</SimDlgDll>
<SimDlgDllArguments>-pSTM32F103RB</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments></TargetDllArguments>
<TargetDlgDll>TARMSTM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pSTM32F103RB</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4107</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>STLink\ST-LINKIII-KEIL_SWO.dll</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M3"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x20000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x20000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x5000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--C99</MiscControls>
<Define>STM32F103xB,USE_FULL_LL_DRIVER,HSE_VALUE=8000000U,USE_FULL_ASSERT</Define>
<Undefine></Undefine>
<IncludePath>..\Inc;..\LLDrivers\inc;..\Services;..\MyDrivers</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>User Application</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>../Src/main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>User Services</GroupName>
<Files>
<File>
<FileName>Chrono.c</FileName>
<FileType>1</FileType>
<FilePath>..\Services\Chrono.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>MyDrivers</GroupName>
<Files>
<File>
<FileName>MyTimer.c</FileName>
<FileType>1</FileType>
<FilePath>..\MyDrivers\MyTimer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers/STM32f1xx_LL_Driver</GroupName>
<Files>
<File>
<FileName>stm32f1xx_ll_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_rcc.c</FilePath>
</File>
<File>
<FileName>stm32f1xx_ll_utils.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_utils.c</FilePath>
</File>
<File>
<FileName>stm32f1xx_ll_tim.c</FileName>
<FileType>1</FileType>
<FilePath>..\LLDrivers\src\stm32f1xx_ll_tim.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Doc</GroupName>
<Files>
<File>
<FileName>readme.txt</FileName>
<FileType>5</FileType>
<FilePath>../readme.txt</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Drivers/CMSIS</GroupName>
<Files>
<File>
<FileName>system_stm32f1xx.c</FileName>
<FileType>1</FileType>
<FilePath>../Src/system_stm32f1xx.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>Example/MDK-ARM</GroupName>
<Files>
<File>
<FileName>startup_stm32f103xb.s</FileName>
<FileType>2</FileType>
<FilePath>startup_stm32f103xb.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.3.0" condition="CMSIS Core">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.5.0"/>
<targetInfos>
<targetInfo name="NUCLEO-F103RB"/>
<targetInfo name="Simulateur"/>
</targetInfos>
</component>
</components>
<files/>
</RTE>
</Project>

20
MDK-ARM/RTE/_NUCLEO-F103RB/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'Project'
* Target: 'NUCLEO-F103RB'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

20
MDK-ARM/RTE/_Simulateur/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'Project'
* Target: 'Simulateur'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "stm32f10x.h"
#endif /* RTE_COMPONENTS_H */

307
MDK-ARM/startup_stm32f103xb.s Normal file
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;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f103xb.s
;* Author : MCD Application Team
;* Description : STM32F103xB Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/BSD-3-Clause
;*
;******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

182
MyDrivers/MyTimer.c Normal file
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// TOUT A FAIRE !! //
/*
indispensable pour pouvoir adresser les registres des périphériques.
Rem : OBLIGATION d'utiliser les définitions utiles contenues dans ce fichier (ex : TIM_CR1_CEN, RCC_APB1ENR_TIM2EN ...)
pour une meilleure lisibilité du code.
Pour les masques, utiliser également les définitions proposée
Rappel : pour mettre à 1 , reg = reg | Mask (ou Mask est le représente le ou les bits à positionner à 1)
pour mettre à 0 , reg = reg&~ Mask (ou Mask est le représente le ou les bits à positionner à 0)
*/
#include "MyTimer.h"
#include "stm32f1xx_ll_bus.h" // Pour l'activation des horloges
#include "stm32f1xx_ll_tim.h"
// variable pointeur de fonction permettant de mémoriser le callback à appeler depuis
// le handler d'IT
void (*Ptr_ItFct_TIM1)(void);
void (*Ptr_ItFct_TIM2)(void);
void (*Ptr_ItFct_TIM3)(void);
void (*Ptr_ItFct_TIM4)(void);
/**
* @brief Active l'horloge et règle l'ARR et le PSC du timer visé
* @note Fonction à lancer avant toute autre. Le timer n'est pas encore lancé (voir MyTimerStart)
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur à placer dans ARR
* int Psc : valeur à placer dans PSC
* @retval None
*/
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc)
{
LL_TIM_InitTypeDef My_LL_Tim_Init_Struct;
// Validation horloge locale
if (Timer==TIM1) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
else if (Timer==TIM2) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
else if (Timer==TIM3) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
else LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4);
// chargement structure Arr, Psc, Up Count
My_LL_Tim_Init_Struct.Autoreload=Arr;
My_LL_Tim_Init_Struct.Prescaler=Psc;
My_LL_Tim_Init_Struct.ClockDivision=LL_TIM_CLOCKDIVISION_DIV1;
My_LL_Tim_Init_Struct.CounterMode=LL_TIM_COUNTERMODE_UP;
My_LL_Tim_Init_Struct.RepetitionCounter=0;
LL_TIM_Init(Timer,&My_LL_Tim_Init_Struct);
// Blocage IT
LL_TIM_DisableIT_UPDATE(Timer);
// Blocage Timer
LL_TIM_DisableCounter(Timer);
}
/**
* @brief Démarre le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Start(TIM_TypeDef * Timer)
{
LL_TIM_EnableCounter(Timer);
}
/**
* @brief Arrêt le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Stop(TIM_TypeDef * Timer)
{
LL_TIM_DisableCounter(Timer);
}
/**
* @brief Configure le Timer considéré en interruption sur débordement.
* @note A ce stade, les interruptions ne sont pas validés (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction à lancer sur interruption
* int Prio : priorité associée à l'interruption
* @retval None
*/
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio)
{
// affectation de la fonction
if (Timer==TIM1) Ptr_ItFct_TIM1=IT_function;
else if (Timer==TIM2) Ptr_ItFct_TIM2=IT_function;
else if (Timer==TIM3) Ptr_ItFct_TIM3=IT_function;
else Ptr_ItFct_TIM4=IT_function;
// Blocage IT (il faudra la débloquer voir fct suivante)
LL_TIM_DisableIT_UPDATE(Timer);
// validation du canal NVIC
IRQn_Type TIM_irq;
if (Timer==TIM1) TIM_irq=TIM1_UP_IRQn;
else if (Timer==TIM2) TIM_irq=TIM2_IRQn;
else if (Timer==TIM3) TIM_irq=TIM3_IRQn;
else TIM_irq=TIM4_IRQn;
NVIC_SetPriority(TIM_irq, Prio);
NVIC_EnableIRQ(TIM_irq);
}
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Enable(TIM_TypeDef * Timer)
{
LL_TIM_EnableIT_UPDATE(Timer);
}
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Disable(TIM_TypeDef * Timer)
{
LL_TIM_DisableIT_UPDATE(Timer);
}
/*
============ LES INTERRUPTIONS =================================
*/
void TIM1_UP_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM1);
(*Ptr_ItFct_TIM1)();
}
void TIM2_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM2);
(*Ptr_ItFct_TIM2)();
}
void TIM3_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM3);
(*Ptr_ItFct_TIM3)();
}
void TIM4_IRQHandler(void)
{
// rabaisser le flag d'IT
LL_TIM_ClearFlag_UPDATE(TIM4);
(*Ptr_ItFct_TIM4)();
}

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// RIEN A MODIFIER //
#ifndef MY_TIMER_H
#define MY_TIMER_H
/*
Driver pour Timer 1 à 4 du STM32F103RB
*/
#include "stm32f103xb.h"
/**
* @brief Active l'horloge et règle l'ARR et le PSC du timer visé
* @note Fonction à lancer avant toute autre. Le timer n'est pas encore lancé (voir MyTimerStart)
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* int Arr : valeur à placer dans ARR
* int Psc : valeur à placer dans PSC
* @retval None
*/
void MyTimer_Conf(TIM_TypeDef * Timer,int Arr, int Psc);
/**
* @brief Démarre le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Start(TIM_TypeDef * Timer);
/**
* @brief Arrêt le timer considéré
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_Stop(TIM_TypeDef * Timer);
/**
* @brief Configure le Timer considéré en interruption sur débordement.
* @note A ce stade, les interruptions ne sont pas validés (voir MyTimer_IT_Enable )
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* void (*IT_function) (void) : nom (adresse) de la fonction à lancer sur interruption
* int Prio : priorité associée à l'interruption
* @retval None
*/
void MyTimer_IT_Conf(TIM_TypeDef * Timer, void (*IT_function) (void),int Prio);
/**
* @brief Autorise les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Enable(TIM_TypeDef * Timer);
/**
* @brief Interdit les interruptions
* @note
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void MyTimer_IT_Disable(TIM_TypeDef * Timer);
#endif

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// A COMPLETER
/*
Service permettant de chornométrer jusqu'à 59mn 59s 99 1/100
Utilise un timer au choix (TIMER1 à TIMER4).
Utilise la lib MyTimers.h /.c
*/
#include "Chrono.h"
#include "MyTimer.h"
// variable privée de type Time qui mémorise la durée mesurée
static Time Chrono_Time; // rem : static rend la visibilité de la variable Chrono_Time limitée à ce fichier
// variable privée qui mémorise pour le module le timer utilisé par le module
static TIM_TypeDef * Chrono_Timer=TIM1; // init par défaut au cas où l'utilisateur ne lance pas Chrono_Conf avant toute autre fct.
// déclaration callback appelé toute les 10ms
void Chrono_Task_10ms(void);
/**
* @brief Configure le chronomètre.
* @note A lancer avant toute autre fonction.
* @param Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Chrono_Conf(TIM_TypeDef * Timer)
{
// Reset Time
Chrono_Time.Hund=0;
Chrono_Time.Sec=0;
Chrono_Time.Min=0;
// Fixation du Timer
Chrono_Timer=Timer;
// Réglage Timer pour un débordement à 10ms
MyTimer_Conf(Chrono_Timer,999, 719);
// Réglage interruption du Timer avec callback : Chrono_Task_10ms()
MyTimer_IT_Conf(Chrono_Timer, Chrono_Task_10ms,3);
// Validation IT
MyTimer_IT_Enable(Chrono_Timer);
}
/**
* @brief Démarre le chronomètre.
* @note si la durée dépasse 59mn 59sec 99 Hund, elle est remise à zéro et repart
* @param Aucun
* @retval Aucun
*/
void Chrono_Start(void)
{
MyTimer_Start(Chrono_Timer);
}
/**
* @brief Arrête le chronomètre.
* @note
* @param Aucun
* @retval Aucun
*/
void Chrono_Stop(void)
{
MyTimer_Stop(Chrono_Timer);
}
/**
* @brief Remet le chronomètre à 0
* @note
* @param Aucun
* @retval Aucun
*/
void Chrono_Reset(void)
{
// Arrêt Chrono
MyTimer_Stop(Chrono_Timer);
// Reset Time
Chrono_Time.Hund=0;
Chrono_Time.Sec=0;
Chrono_Time.Min=0;
}
/**
* @brief Renvoie l'adresse de la variable Time privée gérée dans le module Chrono.c
* @note
* @param Aucun
* @retval adresse de la variable Time
*/
Time * Chrono_Read(void)
{
return &Chrono_Time;
}
/**
* @brief incrémente la variable privée Chron_Time modulo 60mn
* @note
* @param Aucun
* @retval Aucun
*/
void Chrono_Task_10ms(void)
{
Chrono_Time.Hund++;
if (Chrono_Time.Hund==100)
{
Chrono_Time.Sec++;
Chrono_Time.Hund=0;
}
if (Chrono_Time.Sec==60)
{
Chrono_Time.Min++;
Chrono_Time.Sec=0;
}
if (Chrono_Time.Min==60)
{
Chrono_Time.Hund=0;
}
}

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// RIEN A MODIFIER //
#ifndef CHRONO_H
#define CHRONO_H
/*
Service permettant de chornométrer jusqu'à 59mn 59s 99 1/100
Utilise un timer au choix (TIMER1 à TIMER4).
Utilise la lib MyTimers.h /.c
*/
#include "stm32f103xb.h"
/* =====================================================================================
Les fonctions qui gèrent les IO (ajout par rapport à l'activité 1)
=======================================================================================*/
#define PinStart LL_GPIO_PIN_8
#define PinStop LL_GPIO_PIN_6
// à compléter pour la pin reset du chronometre
#define PinLED LL_GPIO_PIN_10
#define GPIO_Pin GPIOC
#define GPIO_LED GPIOC
/**
* @brief polle les 3 entrées et gènère les actions à faire
* @note Fct à lancer en tâche de fond (non bloquante)
* @param None
* @retval None
*/
void Chrono_Background(void);
//=======================================================================================//
// Type de donnée utilisé dans le module
typedef struct {
char Hund;
char Sec;
char Min;
} Time;
/**
* @brief Configure le chronomètre.
* @note A lancer avant toute autre fonction.
* @param TIM_TypeDef Timer : indique le timer à utiliser par le chronomètre, TIM1, TIM2, TIM3 ou TIM4
* @retval None
*/
void Chrono_Conf(TIM_TypeDef * Timer);
/**
* @brief Démarre le chronomètre.
* @note si la durée dépasse 59mn 59sec 99 cent, elle est remise à zéro et repart
* @param Aucun
* @retval Aucun
*/
void Chrono_Start(void);
/**
* @brief Arrête le chronomètre.
* @note
* @param Aucun
* @retval Aucun
*/
void Chrono_Stop(void);
/**
* @brief Remet le chronomètre à 0
* @note
* @param Aucun
* @retval Aucun
*/
void Chrono_Reset(void);
/**
* @brief Renvoie l'adresse de la variable Time privée gérée dans le module Chrono.c
* @note
* @param Aucun
* @retval adresse de la variable Time
*/
Time * Chrono_Read(void);
#endif

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/**
******************************************************************************
* @file Templates_LL/Src/main.c
* @author MCD Application Team
* @brief Main program body through the LL API
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#include "stm32f1xx_ll_rcc.h" // utile dans la fonction SystemClock_Config
#include "stm32f1xx_ll_utils.h" // utile dans la fonction SystemClock_Config
#include "stm32f1xx_ll_system.h" // utile dans la fonction SystemClock_Config
#include "Chrono.h"
void SystemClock_Config(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/* Configure the system clock to 72 MHz */
SystemClock_Config();
/* Add your application code here */
// Configuration chronomètre
Chrono_Conf(TIM3);
// Lancement chronomètre
Chrono_Start();
/* Infinite loop */
while (1)
{
}
}
/**
* @brief System Clock Configuration
* The system Clock is configured as follow :
* System Clock source = PLL (HSE)
* SYSCLK(Hz) = 72000000
* HCLK(Hz) = 72000000
* AHB Prescaler = 1
* APB1 Prescaler = 2
* APB2 Prescaler = 1
* HSE Frequency(Hz) = 8000000
* PLLMUL = 9
* Flash Latency(WS) = 2
* @param None
* @retval None
*/
void SystemClock_Config(void)
{
/* Set FLASH latency */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
/* Enable HSE oscillator */
// ********* Commenter la ligne ci-dessous pour MCBSTM32 *****************
// ********* Conserver la ligne si Nucléo*********************************
LL_RCC_HSE_EnableBypass();
LL_RCC_HSE_Enable();
while(LL_RCC_HSE_IsReady() != 1)
{
};
/* Main PLL configuration and activation */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE_DIV_1, LL_RCC_PLL_MUL_9);
LL_RCC_PLL_Enable();
while(LL_RCC_PLL_IsReady() != 1)
{
};
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
};
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
/* Set systick to 1ms in using frequency set to 72MHz */
LL_Init1msTick(72000000); // utile lorsqu'on utilise la fonction LL_mDelay
/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
LL_SetSystemCoreClock(72000000);
}
/* ============== BOARD SPECIFIC CONFIGURATION CODE END ============== */
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d", file, line) */
/* Infinite loop */
while (1)
{
}
}
#endif
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* factors, AHB/APBx prescalers and Flash settings).
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f1xx_xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
* configure the system clock before to branch to main program.
*
* 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
* the product used), refer to "HSE_VALUE".
* When HSE is used as system clock source, directly or through PLL, and you
* are using different crystal you have to adapt the HSE value to your own
* configuration.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f1xx_system
* @{
*/
/** @addtogroup STM32F1xx_System_Private_Includes
* @{
*/
#include "stm32f1xx.h"
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/*!< Uncomment the following line if you need to use external SRAM */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/* #define DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/** @addtogroup STM32F1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemCoreClock variable.
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit (void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
#if !defined(STM32F105xC) && !defined(STM32F107xC)
RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif /* STM32F105xC */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
RCC->CFGR &= (uint32_t)0xFF80FFFF;
#if defined(STM32F105xC) || defined(STM32F107xC)
/* Reset PLL2ON and PLL3ON bits */
RCC->CR &= (uint32_t)0xEBFFFFFF;
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x00FF0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#elif defined(STM32F100xB) || defined(STM32F100xE)
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
/* Reset CFGR2 register */
RCC->CFGR2 = 0x00000000;
#else
/* Disable all interrupts and clear pending bits */
RCC->CIR = 0x009F0000;
#endif /* STM32F105xC */
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
#endif
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
* 8 MHz or 25 MHz, depending on the product used), user has to ensure
* that HSE_VALUE is same as the real frequency of the crystal used.
* Otherwise, this function may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
#if defined(STM32F105xC) || defined(STM32F107xC)
uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif /* STM32F105xC */
#if defined(STM32F100xB) || defined(STM32F100xE)
uint32_t prediv1factor = 0;
#endif /* STM32F100xB or STM32F100xE */
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
#if !defined(STM32F105xC) && !defined(STM32F107xC)
pllmull = ( pllmull >> 18) + 2;
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{
#if defined(STM32F100xB) || defined(STM32F100xE)
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
#else
/* HSE selected as PLL clock entry */
if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
{/* HSE oscillator clock divided by 2 */
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
}
else
{
SystemCoreClock = HSE_VALUE * pllmull;
}
#endif
}
#else
pllmull = pllmull >> 18;
if (pllmull != 0x0D)
{
pllmull += 2;
}
else
{ /* PLL multiplication factor = PLL input clock * 6.5 */
pllmull = 13 / 2;
}
if (pllsource == 0x00)
{
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
else
{/* PREDIV1 selected as PLL clock entry */
/* Get PREDIV1 clock source and division factor */
prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
if (prediv1source == 0)
{
/* HSE oscillator clock selected as PREDIV1 clock entry */
SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
}
else
{/* PLL2 clock selected as PREDIV1 clock entry */
/* Get PREDIV2 division factor and PLL2 multiplication factor */
prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
}
}
#endif /* STM32F105xC */
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
/**
* @brief Setup the external memory controller. Called in startup_stm32f1xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f1xx_xx.s/.c before jump to main.
* This function configures the external SRAM mounted on STM3210E-EVAL
* board (STM32 High density devices). This SRAM will be used as program
* data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
required, then adjust the Register Addresses */
/* Enable FSMC clock */
RCC->AHBENR = 0x00000114;
/* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
RCC->APB2ENR = 0x000001E0;
/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
/*---------------- SRAM Address lines configuration -------------------------*/
/*---------------- NOE and NWE configuration --------------------------------*/
/*---------------- NE3 configuration ----------------------------------------*/
/*---------------- NBL0, NBL1 configuration ---------------------------------*/
GPIOD->CRL = 0x44BB44BB;
GPIOD->CRH = 0xBBBBBBBB;
GPIOE->CRL = 0xB44444BB;
GPIOE->CRH = 0xBBBBBBBB;
GPIOF->CRL = 0x44BBBBBB;
GPIOF->CRH = 0xBBBB4444;
GPIOG->CRL = 0x44BBBBBB;
GPIOG->CRH = 0x44444B44;
/*---------------- FSMC Configuration ---------------------------------------*/
/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
FSMC_Bank1->BTCR[4] = 0x00001011;
FSMC_Bank1->BTCR[5] = 0x00000200;
}
#endif /* DATA_IN_ExtSRAM */
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/