Projet voilier 4IRA1 Arnaud Vergnet Marino Benassai Bastien Picco Yohan Simard
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  1. /**
  2. ******************************************************************************
  3. * @file stm32f103xb.h
  4. * @author MCD Application Team
  5. * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
  6. * This file contains all the peripheral register's definitions, bits
  7. * definitions and memory mapping for STM32F1xx devices.
  8. *
  9. * This file contains:
  10. * - Data structures and the address mapping for all peripherals
  11. * - Peripheral's registers declarations and bits definition
  12. * - Macros to access peripheral’s registers hardware
  13. *
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  18. * All rights reserved.</center></h2>
  19. *
  20. * This software component is licensed by ST under BSD 3-Clause license,
  21. * the "License"; You may not use this file except in compliance with the
  22. * License. You may obtain a copy of the License at:
  23. * opensource.org/licenses/BSD-3-Clause
  24. *
  25. ******************************************************************************
  26. */
  27. /** @addtogroup CMSIS
  28. * @{
  29. */
  30. /** @addtogroup stm32f103xb
  31. * @{
  32. */
  33. #ifndef __STM32F103xB_H
  34. #define __STM32F103xB_H
  35. #ifdef __cplusplus
  36. extern "C" {
  37. #endif
  38. /** @addtogroup Configuration_section_for_CMSIS
  39. * @{
  40. */
  41. /**
  42. * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
  43. */
  44. #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
  45. #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
  46. #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
  47. #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
  48. /**
  49. * @}
  50. */
  51. /** @addtogroup Peripheral_interrupt_number_definition
  52. * @{
  53. */
  54. /**
  55. * @brief STM32F10x Interrupt Number Definition, according to the selected device
  56. * in @ref Library_configuration_section
  57. */
  58. /*!< Interrupt Number Definition */
  59. typedef enum
  60. {
  61. /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
  62. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  63. HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
  64. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
  65. BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
  66. UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
  67. SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
  68. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
  69. PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
  70. SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
  71. /****** STM32 specific Interrupt Numbers *********************************************************/
  72. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  73. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
  74. TAMPER_IRQn = 2, /*!< Tamper Interrupt */
  75. RTC_IRQn = 3, /*!< RTC global Interrupt */
  76. FLASH_IRQn = 4, /*!< FLASH global Interrupt */
  77. RCC_IRQn = 5, /*!< RCC global Interrupt */
  78. EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
  79. EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
  80. EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
  81. EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
  82. EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
  83. DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
  84. DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
  85. DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
  86. DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
  87. DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
  88. DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
  89. DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
  90. ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
  91. USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
  92. USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
  93. CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
  94. CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
  95. EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
  96. TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
  97. TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
  98. TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
  99. TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
  100. TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
  101. TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
  102. TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
  103. I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
  104. I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
  105. I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
  106. I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
  107. SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
  108. SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
  109. USART1_IRQn = 37, /*!< USART1 global Interrupt */
  110. USART2_IRQn = 38, /*!< USART2 global Interrupt */
  111. USART3_IRQn = 39, /*!< USART3 global Interrupt */
  112. EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
  113. RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
  114. USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
  115. } IRQn_Type;
  116. /**
  117. * @}
  118. */
  119. #include "core_cm3.h"
  120. #include "system_stm32f1xx.h"
  121. #include <stdint.h>
  122. /** @addtogroup Peripheral_registers_structures
  123. * @{
  124. */
  125. /**
  126. * @brief Analog to Digital Converter
  127. */
  128. typedef struct
  129. {
  130. __IO uint32_t SR;
  131. __IO uint32_t CR1;
  132. __IO uint32_t CR2;
  133. __IO uint32_t SMPR1;
  134. __IO uint32_t SMPR2;
  135. __IO uint32_t JOFR1;
  136. __IO uint32_t JOFR2;
  137. __IO uint32_t JOFR3;
  138. __IO uint32_t JOFR4;
  139. __IO uint32_t HTR;
  140. __IO uint32_t LTR;
  141. __IO uint32_t SQR1;
  142. __IO uint32_t SQR2;
  143. __IO uint32_t SQR3;
  144. __IO uint32_t JSQR;
  145. __IO uint32_t JDR1;
  146. __IO uint32_t JDR2;
  147. __IO uint32_t JDR3;
  148. __IO uint32_t JDR4;
  149. __IO uint32_t DR;
  150. } ADC_TypeDef;
  151. typedef struct
  152. {
  153. __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
  154. __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
  155. __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
  156. uint32_t RESERVED[16];
  157. __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
  158. } ADC_Common_TypeDef;
  159. /**
  160. * @brief Backup Registers
  161. */
  162. typedef struct
  163. {
  164. uint32_t RESERVED0;
  165. __IO uint32_t DR1;
  166. __IO uint32_t DR2;
  167. __IO uint32_t DR3;
  168. __IO uint32_t DR4;
  169. __IO uint32_t DR5;
  170. __IO uint32_t DR6;
  171. __IO uint32_t DR7;
  172. __IO uint32_t DR8;
  173. __IO uint32_t DR9;
  174. __IO uint32_t DR10;
  175. __IO uint32_t RTCCR;
  176. __IO uint32_t CR;
  177. __IO uint32_t CSR;
  178. } BKP_TypeDef;
  179. /**
  180. * @brief Controller Area Network TxMailBox
  181. */
  182. typedef struct
  183. {
  184. __IO uint32_t TIR;
  185. __IO uint32_t TDTR;
  186. __IO uint32_t TDLR;
  187. __IO uint32_t TDHR;
  188. } CAN_TxMailBox_TypeDef;
  189. /**
  190. * @brief Controller Area Network FIFOMailBox
  191. */
  192. typedef struct
  193. {
  194. __IO uint32_t RIR;
  195. __IO uint32_t RDTR;
  196. __IO uint32_t RDLR;
  197. __IO uint32_t RDHR;
  198. } CAN_FIFOMailBox_TypeDef;
  199. /**
  200. * @brief Controller Area Network FilterRegister
  201. */
  202. typedef struct
  203. {
  204. __IO uint32_t FR1;
  205. __IO uint32_t FR2;
  206. } CAN_FilterRegister_TypeDef;
  207. /**
  208. * @brief Controller Area Network
  209. */
  210. typedef struct
  211. {
  212. __IO uint32_t MCR;
  213. __IO uint32_t MSR;
  214. __IO uint32_t TSR;
  215. __IO uint32_t RF0R;
  216. __IO uint32_t RF1R;
  217. __IO uint32_t IER;
  218. __IO uint32_t ESR;
  219. __IO uint32_t BTR;
  220. uint32_t RESERVED0[88];
  221. CAN_TxMailBox_TypeDef sTxMailBox[3];
  222. CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
  223. uint32_t RESERVED1[12];
  224. __IO uint32_t FMR;
  225. __IO uint32_t FM1R;
  226. uint32_t RESERVED2;
  227. __IO uint32_t FS1R;
  228. uint32_t RESERVED3;
  229. __IO uint32_t FFA1R;
  230. uint32_t RESERVED4;
  231. __IO uint32_t FA1R;
  232. uint32_t RESERVED5[8];
  233. CAN_FilterRegister_TypeDef sFilterRegister[14];
  234. } CAN_TypeDef;
  235. /**
  236. * @brief CRC calculation unit
  237. */
  238. typedef struct
  239. {
  240. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  241. __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  242. uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
  243. uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
  244. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  245. } CRC_TypeDef;
  246. /**
  247. * @brief Debug MCU
  248. */
  249. typedef struct
  250. {
  251. __IO uint32_t IDCODE;
  252. __IO uint32_t CR;
  253. }DBGMCU_TypeDef;
  254. /**
  255. * @brief DMA Controller
  256. */
  257. typedef struct
  258. {
  259. __IO uint32_t CCR;
  260. __IO uint32_t CNDTR;
  261. __IO uint32_t CPAR;
  262. __IO uint32_t CMAR;
  263. } DMA_Channel_TypeDef;
  264. typedef struct
  265. {
  266. __IO uint32_t ISR;
  267. __IO uint32_t IFCR;
  268. } DMA_TypeDef;
  269. /**
  270. * @brief External Interrupt/Event Controller
  271. */
  272. typedef struct
  273. {
  274. __IO uint32_t IMR;
  275. __IO uint32_t EMR;
  276. __IO uint32_t RTSR;
  277. __IO uint32_t FTSR;
  278. __IO uint32_t SWIER;
  279. __IO uint32_t PR;
  280. } EXTI_TypeDef;
  281. /**
  282. * @brief FLASH Registers
  283. */
  284. typedef struct
  285. {
  286. __IO uint32_t ACR;
  287. __IO uint32_t KEYR;
  288. __IO uint32_t OPTKEYR;
  289. __IO uint32_t SR;
  290. __IO uint32_t CR;
  291. __IO uint32_t AR;
  292. __IO uint32_t RESERVED;
  293. __IO uint32_t OBR;
  294. __IO uint32_t WRPR;
  295. } FLASH_TypeDef;
  296. /**
  297. * @brief Option Bytes Registers
  298. */
  299. typedef struct
  300. {
  301. __IO uint16_t RDP;
  302. __IO uint16_t USER;
  303. __IO uint16_t Data0;
  304. __IO uint16_t Data1;
  305. __IO uint16_t WRP0;
  306. __IO uint16_t WRP1;
  307. __IO uint16_t WRP2;
  308. __IO uint16_t WRP3;
  309. } OB_TypeDef;
  310. /**
  311. * @brief General Purpose I/O
  312. */
  313. typedef struct
  314. {
  315. __IO uint32_t CRL;
  316. __IO uint32_t CRH;
  317. __IO uint32_t IDR;
  318. __IO uint32_t ODR;
  319. __IO uint32_t BSRR;
  320. __IO uint32_t BRR;
  321. __IO uint32_t LCKR;
  322. } GPIO_TypeDef;
  323. /**
  324. * @brief Alternate Function I/O
  325. */
  326. typedef struct
  327. {
  328. __IO uint32_t EVCR;
  329. __IO uint32_t MAPR;
  330. __IO uint32_t EXTICR[4];
  331. uint32_t RESERVED0;
  332. __IO uint32_t MAPR2;
  333. } AFIO_TypeDef;
  334. /**
  335. * @brief Inter Integrated Circuit Interface
  336. */
  337. typedef struct
  338. {
  339. __IO uint32_t CR1;
  340. __IO uint32_t CR2;
  341. __IO uint32_t OAR1;
  342. __IO uint32_t OAR2;
  343. __IO uint32_t DR;
  344. __IO uint32_t SR1;
  345. __IO uint32_t SR2;
  346. __IO uint32_t CCR;
  347. __IO uint32_t TRISE;
  348. } I2C_TypeDef;
  349. /**
  350. * @brief Independent WATCHDOG
  351. */
  352. typedef struct
  353. {
  354. __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
  355. __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
  356. __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
  357. __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
  358. } IWDG_TypeDef;
  359. /**
  360. * @brief Power Control
  361. */
  362. typedef struct
  363. {
  364. __IO uint32_t CR;
  365. __IO uint32_t CSR;
  366. } PWR_TypeDef;
  367. /**
  368. * @brief Reset and Clock Control
  369. */
  370. typedef struct
  371. {
  372. __IO uint32_t CR;
  373. __IO uint32_t CFGR;
  374. __IO uint32_t CIR;
  375. __IO uint32_t APB2RSTR;
  376. __IO uint32_t APB1RSTR;
  377. __IO uint32_t AHBENR;
  378. __IO uint32_t APB2ENR;
  379. __IO uint32_t APB1ENR;
  380. __IO uint32_t BDCR;
  381. __IO uint32_t CSR;
  382. } RCC_TypeDef;
  383. /**
  384. * @brief Real-Time Clock
  385. */
  386. typedef struct
  387. {
  388. __IO uint32_t CRH;
  389. __IO uint32_t CRL;
  390. __IO uint32_t PRLH;
  391. __IO uint32_t PRLL;
  392. __IO uint32_t DIVH;
  393. __IO uint32_t DIVL;
  394. __IO uint32_t CNTH;
  395. __IO uint32_t CNTL;
  396. __IO uint32_t ALRH;
  397. __IO uint32_t ALRL;
  398. } RTC_TypeDef;
  399. /**
  400. * @brief Serial Peripheral Interface
  401. */
  402. typedef struct
  403. {
  404. __IO uint32_t CR1;
  405. __IO uint32_t CR2;
  406. __IO uint32_t SR;
  407. __IO uint32_t DR;
  408. __IO uint32_t CRCPR;
  409. __IO uint32_t RXCRCR;
  410. __IO uint32_t TXCRCR;
  411. __IO uint32_t I2SCFGR;
  412. } SPI_TypeDef;
  413. /**
  414. * @brief TIM Timers
  415. */
  416. typedef struct
  417. {
  418. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  419. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  420. __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
  421. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  422. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  423. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  424. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  425. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  426. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  427. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  428. __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
  429. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  430. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  431. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  432. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  433. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  434. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  435. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  436. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  437. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
  438. __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
  439. }TIM_TypeDef;
  440. /**
  441. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  442. */
  443. typedef struct
  444. {
  445. __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
  446. __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
  447. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
  448. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
  449. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
  450. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
  451. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
  452. } USART_TypeDef;
  453. /**
  454. * @brief Universal Serial Bus Full Speed Device
  455. */
  456. typedef struct
  457. {
  458. __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
  459. __IO uint16_t RESERVED0; /*!< Reserved */
  460. __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
  461. __IO uint16_t RESERVED1; /*!< Reserved */
  462. __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
  463. __IO uint16_t RESERVED2; /*!< Reserved */
  464. __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
  465. __IO uint16_t RESERVED3; /*!< Reserved */
  466. __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
  467. __IO uint16_t RESERVED4; /*!< Reserved */
  468. __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
  469. __IO uint16_t RESERVED5; /*!< Reserved */
  470. __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
  471. __IO uint16_t RESERVED6; /*!< Reserved */
  472. __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
  473. __IO uint16_t RESERVED7[17]; /*!< Reserved */
  474. __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
  475. __IO uint16_t RESERVED8; /*!< Reserved */
  476. __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
  477. __IO uint16_t RESERVED9; /*!< Reserved */
  478. __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
  479. __IO uint16_t RESERVEDA; /*!< Reserved */
  480. __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
  481. __IO uint16_t RESERVEDB; /*!< Reserved */
  482. __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
  483. __IO uint16_t RESERVEDC; /*!< Reserved */
  484. } USB_TypeDef;
  485. /**
  486. * @brief Window WATCHDOG
  487. */
  488. typedef struct
  489. {
  490. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  491. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  492. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  493. } WWDG_TypeDef;
  494. /**
  495. * @}
  496. */
  497. /** @addtogroup Peripheral_memory_map
  498. * @{
  499. */
  500. #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */
  501. #define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */
  502. #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */
  503. #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
  504. #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */
  505. #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
  506. /*!< Peripheral memory map */
  507. #define APB1PERIPH_BASE PERIPH_BASE
  508. #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
  509. #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  510. #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
  511. #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
  512. #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
  513. #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
  514. #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
  515. #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
  516. #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
  517. #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
  518. #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
  519. #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
  520. #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
  521. #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
  522. #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
  523. #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
  524. #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
  525. #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
  526. #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
  527. #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
  528. #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
  529. #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
  530. #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
  531. #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
  532. #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
  533. #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
  534. #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
  535. #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
  536. #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
  537. #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
  538. #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
  539. #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
  540. #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
  541. #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
  542. #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
  543. #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
  544. #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
  545. #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
  546. #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
  547. #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */
  548. #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */
  549. #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */
  550. #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */
  551. /* USB device FS */
  552. #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
  553. #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
  554. /**
  555. * @}
  556. */
  557. /** @addtogroup Peripheral_declaration
  558. * @{
  559. */
  560. #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
  561. #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
  562. #define TIM4 ((TIM_TypeDef *)TIM4_BASE)
  563. #define RTC ((RTC_TypeDef *)RTC_BASE)
  564. #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
  565. #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
  566. #define SPI2 ((SPI_TypeDef *)SPI2_BASE)
  567. #define USART2 ((USART_TypeDef *)USART2_BASE)
  568. #define USART3 ((USART_TypeDef *)USART3_BASE)
  569. #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
  570. #define I2C2 ((I2C_TypeDef *)I2C2_BASE)
  571. #define USB ((USB_TypeDef *)USB_BASE)
  572. #define CAN1 ((CAN_TypeDef *)CAN1_BASE)
  573. #define BKP ((BKP_TypeDef *)BKP_BASE)
  574. #define PWR ((PWR_TypeDef *)PWR_BASE)
  575. #define AFIO ((AFIO_TypeDef *)AFIO_BASE)
  576. #define EXTI ((EXTI_TypeDef *)EXTI_BASE)
  577. #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
  578. #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
  579. #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
  580. #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
  581. #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
  582. #define ADC1 ((ADC_TypeDef *)ADC1_BASE)
  583. #define ADC2 ((ADC_TypeDef *)ADC2_BASE)
  584. #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
  585. #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
  586. #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
  587. #define USART1 ((USART_TypeDef *)USART1_BASE)
  588. #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
  589. #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
  590. #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
  591. #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
  592. #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
  593. #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
  594. #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
  595. #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
  596. #define RCC ((RCC_TypeDef *)RCC_BASE)
  597. #define CRC ((CRC_TypeDef *)CRC_BASE)
  598. #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
  599. #define OB ((OB_TypeDef *)OB_BASE)
  600. #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
  601. /**
  602. * @}
  603. */
  604. /** @addtogroup Exported_constants
  605. * @{
  606. */
  607. /** @addtogroup Peripheral_Registers_Bits_Definition
  608. * @{
  609. */
  610. /******************************************************************************/
  611. /* Peripheral Registers_Bits_Definition */
  612. /******************************************************************************/
  613. /******************************************************************************/
  614. /* */
  615. /* CRC calculation unit (CRC) */
  616. /* */
  617. /******************************************************************************/
  618. /******************* Bit definition for CRC_DR register *********************/
  619. #define CRC_DR_DR_Pos (0U)
  620. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  621. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  622. /******************* Bit definition for CRC_IDR register ********************/
  623. #define CRC_IDR_IDR_Pos (0U)
  624. #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
  625. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
  626. /******************** Bit definition for CRC_CR register ********************/
  627. #define CRC_CR_RESET_Pos (0U)
  628. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  629. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
  630. /******************************************************************************/
  631. /* */
  632. /* Power Control */
  633. /* */
  634. /******************************************************************************/
  635. /******************** Bit definition for PWR_CR register ********************/
  636. #define PWR_CR_LPDS_Pos (0U)
  637. #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
  638. #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
  639. #define PWR_CR_PDDS_Pos (1U)
  640. #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
  641. #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
  642. #define PWR_CR_CWUF_Pos (2U)
  643. #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
  644. #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
  645. #define PWR_CR_CSBF_Pos (3U)
  646. #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
  647. #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
  648. #define PWR_CR_PVDE_Pos (4U)
  649. #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
  650. #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
  651. #define PWR_CR_PLS_Pos (5U)
  652. #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
  653. #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
  654. #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
  655. #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
  656. #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
  657. /*!< PVD level configuration */
  658. #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
  659. #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
  660. #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
  661. #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
  662. #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
  663. #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
  664. #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
  665. #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
  666. /* Legacy defines */
  667. #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
  668. #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
  669. #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
  670. #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
  671. #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
  672. #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
  673. #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
  674. #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
  675. #define PWR_CR_DBP_Pos (8U)
  676. #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
  677. #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
  678. /******************* Bit definition for PWR_CSR register ********************/
  679. #define PWR_CSR_WUF_Pos (0U)
  680. #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
  681. #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
  682. #define PWR_CSR_SBF_Pos (1U)
  683. #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
  684. #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
  685. #define PWR_CSR_PVDO_Pos (2U)
  686. #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
  687. #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
  688. #define PWR_CSR_EWUP_Pos (8U)
  689. #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
  690. #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
  691. /******************************************************************************/
  692. /* */
  693. /* Backup registers */
  694. /* */
  695. /******************************************************************************/
  696. /******************* Bit definition for BKP_DR1 register ********************/
  697. #define BKP_DR1_D_Pos (0U)
  698. #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
  699. #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
  700. /******************* Bit definition for BKP_DR2 register ********************/
  701. #define BKP_DR2_D_Pos (0U)
  702. #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
  703. #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
  704. /******************* Bit definition for BKP_DR3 register ********************/
  705. #define BKP_DR3_D_Pos (0U)
  706. #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
  707. #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
  708. /******************* Bit definition for BKP_DR4 register ********************/
  709. #define BKP_DR4_D_Pos (0U)
  710. #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
  711. #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
  712. /******************* Bit definition for BKP_DR5 register ********************/
  713. #define BKP_DR5_D_Pos (0U)
  714. #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
  715. #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
  716. /******************* Bit definition for BKP_DR6 register ********************/
  717. #define BKP_DR6_D_Pos (0U)
  718. #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
  719. #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
  720. /******************* Bit definition for BKP_DR7 register ********************/
  721. #define BKP_DR7_D_Pos (0U)
  722. #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
  723. #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
  724. /******************* Bit definition for BKP_DR8 register ********************/
  725. #define BKP_DR8_D_Pos (0U)
  726. #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
  727. #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
  728. /******************* Bit definition for BKP_DR9 register ********************/
  729. #define BKP_DR9_D_Pos (0U)
  730. #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
  731. #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
  732. /******************* Bit definition for BKP_DR10 register *******************/
  733. #define BKP_DR10_D_Pos (0U)
  734. #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
  735. #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
  736. #define RTC_BKP_NUMBER 10
  737. /****************** Bit definition for BKP_RTCCR register *******************/
  738. #define BKP_RTCCR_CAL_Pos (0U)
  739. #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
  740. #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
  741. #define BKP_RTCCR_CCO_Pos (7U)
  742. #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
  743. #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
  744. #define BKP_RTCCR_ASOE_Pos (8U)
  745. #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
  746. #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
  747. #define BKP_RTCCR_ASOS_Pos (9U)
  748. #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
  749. #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
  750. /******************** Bit definition for BKP_CR register ********************/
  751. #define BKP_CR_TPE_Pos (0U)
  752. #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */
  753. #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
  754. #define BKP_CR_TPAL_Pos (1U)
  755. #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
  756. #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
  757. /******************* Bit definition for BKP_CSR register ********************/
  758. #define BKP_CSR_CTE_Pos (0U)
  759. #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
  760. #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
  761. #define BKP_CSR_CTI_Pos (1U)
  762. #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
  763. #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
  764. #define BKP_CSR_TPIE_Pos (2U)
  765. #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
  766. #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
  767. #define BKP_CSR_TEF_Pos (8U)
  768. #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
  769. #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
  770. #define BKP_CSR_TIF_Pos (9U)
  771. #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
  772. #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
  773. /******************************************************************************/
  774. /* */
  775. /* Reset and Clock Control */
  776. /* */
  777. /******************************************************************************/
  778. /******************** Bit definition for RCC_CR register ********************/
  779. #define RCC_CR_HSION_Pos (0U)
  780. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
  781. #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
  782. #define RCC_CR_HSIRDY_Pos (1U)
  783. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
  784. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
  785. #define RCC_CR_HSITRIM_Pos (3U)
  786. #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
  787. #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
  788. #define RCC_CR_HSICAL_Pos (8U)
  789. #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
  790. #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
  791. #define RCC_CR_HSEON_Pos (16U)
  792. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  793. #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
  794. #define RCC_CR_HSERDY_Pos (17U)
  795. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  796. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
  797. #define RCC_CR_HSEBYP_Pos (18U)
  798. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  799. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
  800. #define RCC_CR_CSSON_Pos (19U)
  801. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  802. #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
  803. #define RCC_CR_PLLON_Pos (24U)
  804. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  805. #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
  806. #define RCC_CR_PLLRDY_Pos (25U)
  807. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  808. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
  809. /******************* Bit definition for RCC_CFGR register *******************/
  810. /*!< SW configuration */
  811. #define RCC_CFGR_SW_Pos (0U)
  812. #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
  813. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
  814. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  815. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  816. #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
  817. #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
  818. #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
  819. /*!< SWS configuration */
  820. #define RCC_CFGR_SWS_Pos (2U)
  821. #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
  822. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
  823. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
  824. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  825. #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
  826. #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
  827. #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
  828. /*!< HPRE configuration */
  829. #define RCC_CFGR_HPRE_Pos (4U)
  830. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
  831. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  832. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
  833. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
  834. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
  835. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
  836. #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
  837. #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
  838. #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
  839. #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
  840. #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
  841. #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
  842. #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
  843. #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
  844. #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
  845. /*!< PPRE1 configuration */
  846. #define RCC_CFGR_PPRE1_Pos (8U)
  847. #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
  848. #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
  849. #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
  850. #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
  851. #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
  852. #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
  853. #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
  854. #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
  855. #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
  856. #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
  857. /*!< PPRE2 configuration */
  858. #define RCC_CFGR_PPRE2_Pos (11U)
  859. #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
  860. #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
  861. #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
  862. #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
  863. #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
  864. #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
  865. #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
  866. #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
  867. #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
  868. #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
  869. /*!< ADCPPRE configuration */
  870. #define RCC_CFGR_ADCPRE_Pos (14U)
  871. #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
  872. #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
  873. #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
  874. #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
  875. #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
  876. #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
  877. #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
  878. #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
  879. #define RCC_CFGR_PLLSRC_Pos (16U)
  880. #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
  881. #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
  882. #define RCC_CFGR_PLLXTPRE_Pos (17U)
  883. #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
  884. #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
  885. /*!< PLLMUL configuration */
  886. #define RCC_CFGR_PLLMULL_Pos (18U)
  887. #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
  888. #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
  889. #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
  890. #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
  891. #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
  892. #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
  893. #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
  894. #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
  895. #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
  896. #define RCC_CFGR_PLLMULL3_Pos (18U)
  897. #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
  898. #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
  899. #define RCC_CFGR_PLLMULL4_Pos (19U)
  900. #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
  901. #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
  902. #define RCC_CFGR_PLLMULL5_Pos (18U)
  903. #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
  904. #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
  905. #define RCC_CFGR_PLLMULL6_Pos (20U)
  906. #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
  907. #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
  908. #define RCC_CFGR_PLLMULL7_Pos (18U)
  909. #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
  910. #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
  911. #define RCC_CFGR_PLLMULL8_Pos (19U)
  912. #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
  913. #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
  914. #define RCC_CFGR_PLLMULL9_Pos (18U)
  915. #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
  916. #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
  917. #define RCC_CFGR_PLLMULL10_Pos (21U)
  918. #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
  919. #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
  920. #define RCC_CFGR_PLLMULL11_Pos (18U)
  921. #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
  922. #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
  923. #define RCC_CFGR_PLLMULL12_Pos (19U)
  924. #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
  925. #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
  926. #define RCC_CFGR_PLLMULL13_Pos (18U)
  927. #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
  928. #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
  929. #define RCC_CFGR_PLLMULL14_Pos (20U)
  930. #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
  931. #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
  932. #define RCC_CFGR_PLLMULL15_Pos (18U)
  933. #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
  934. #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
  935. #define RCC_CFGR_PLLMULL16_Pos (19U)
  936. #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
  937. #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
  938. #define RCC_CFGR_USBPRE_Pos (22U)
  939. #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
  940. #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
  941. /*!< MCO configuration */
  942. #define RCC_CFGR_MCO_Pos (24U)
  943. #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
  944. #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
  945. #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
  946. #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
  947. #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
  948. #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
  949. #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
  950. #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
  951. #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
  952. #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
  953. /* Reference defines */
  954. #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
  955. #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
  956. #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
  957. #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
  958. #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
  959. #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
  960. #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
  961. #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
  962. #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
  963. /*!<****************** Bit definition for RCC_CIR register ********************/
  964. #define RCC_CIR_LSIRDYF_Pos (0U)
  965. #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
  966. #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
  967. #define RCC_CIR_LSERDYF_Pos (1U)
  968. #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
  969. #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
  970. #define RCC_CIR_HSIRDYF_Pos (2U)
  971. #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
  972. #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
  973. #define RCC_CIR_HSERDYF_Pos (3U)
  974. #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
  975. #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
  976. #define RCC_CIR_PLLRDYF_Pos (4U)
  977. #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
  978. #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
  979. #define RCC_CIR_CSSF_Pos (7U)
  980. #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
  981. #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
  982. #define RCC_CIR_LSIRDYIE_Pos (8U)
  983. #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
  984. #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
  985. #define RCC_CIR_LSERDYIE_Pos (9U)
  986. #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
  987. #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
  988. #define RCC_CIR_HSIRDYIE_Pos (10U)
  989. #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
  990. #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
  991. #define RCC_CIR_HSERDYIE_Pos (11U)
  992. #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
  993. #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
  994. #define RCC_CIR_PLLRDYIE_Pos (12U)
  995. #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
  996. #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
  997. #define RCC_CIR_LSIRDYC_Pos (16U)
  998. #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
  999. #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
  1000. #define RCC_CIR_LSERDYC_Pos (17U)
  1001. #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
  1002. #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
  1003. #define RCC_CIR_HSIRDYC_Pos (18U)
  1004. #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
  1005. #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
  1006. #define RCC_CIR_HSERDYC_Pos (19U)
  1007. #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
  1008. #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
  1009. #define RCC_CIR_PLLRDYC_Pos (20U)
  1010. #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
  1011. #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
  1012. #define RCC_CIR_CSSC_Pos (23U)
  1013. #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
  1014. #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
  1015. /***************** Bit definition for RCC_APB2RSTR register *****************/
  1016. #define RCC_APB2RSTR_AFIORST_Pos (0U)
  1017. #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
  1018. #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
  1019. #define RCC_APB2RSTR_IOPARST_Pos (2U)
  1020. #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
  1021. #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
  1022. #define RCC_APB2RSTR_IOPBRST_Pos (3U)
  1023. #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
  1024. #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
  1025. #define RCC_APB2RSTR_IOPCRST_Pos (4U)
  1026. #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
  1027. #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
  1028. #define RCC_APB2RSTR_IOPDRST_Pos (5U)
  1029. #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
  1030. #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
  1031. #define RCC_APB2RSTR_ADC1RST_Pos (9U)
  1032. #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
  1033. #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
  1034. #define RCC_APB2RSTR_ADC2RST_Pos (10U)
  1035. #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
  1036. #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
  1037. #define RCC_APB2RSTR_TIM1RST_Pos (11U)
  1038. #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
  1039. #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
  1040. #define RCC_APB2RSTR_SPI1RST_Pos (12U)
  1041. #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
  1042. #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
  1043. #define RCC_APB2RSTR_USART1RST_Pos (14U)
  1044. #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
  1045. #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
  1046. #define RCC_APB2RSTR_IOPERST_Pos (6U)
  1047. #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
  1048. #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
  1049. /***************** Bit definition for RCC_APB1RSTR register *****************/
  1050. #define RCC_APB1RSTR_TIM2RST_Pos (0U)
  1051. #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
  1052. #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
  1053. #define RCC_APB1RSTR_TIM3RST_Pos (1U)
  1054. #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
  1055. #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
  1056. #define RCC_APB1RSTR_WWDGRST_Pos (11U)
  1057. #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
  1058. #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
  1059. #define RCC_APB1RSTR_USART2RST_Pos (17U)
  1060. #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
  1061. #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
  1062. #define RCC_APB1RSTR_I2C1RST_Pos (21U)
  1063. #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
  1064. #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
  1065. #define RCC_APB1RSTR_CAN1RST_Pos (25U)
  1066. #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
  1067. #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
  1068. #define RCC_APB1RSTR_BKPRST_Pos (27U)
  1069. #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
  1070. #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
  1071. #define RCC_APB1RSTR_PWRRST_Pos (28U)
  1072. #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
  1073. #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
  1074. #define RCC_APB1RSTR_TIM4RST_Pos (2U)
  1075. #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
  1076. #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
  1077. #define RCC_APB1RSTR_SPI2RST_Pos (14U)
  1078. #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
  1079. #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
  1080. #define RCC_APB1RSTR_USART3RST_Pos (18U)
  1081. #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
  1082. #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
  1083. #define RCC_APB1RSTR_I2C2RST_Pos (22U)
  1084. #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
  1085. #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
  1086. #define RCC_APB1RSTR_USBRST_Pos (23U)
  1087. #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
  1088. #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
  1089. /****************** Bit definition for RCC_AHBENR register ******************/
  1090. #define RCC_AHBENR_DMA1EN_Pos (0U)
  1091. #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
  1092. #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
  1093. #define RCC_AHBENR_SRAMEN_Pos (2U)
  1094. #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
  1095. #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
  1096. #define RCC_AHBENR_FLITFEN_Pos (4U)
  1097. #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
  1098. #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
  1099. #define RCC_AHBENR_CRCEN_Pos (6U)
  1100. #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
  1101. #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
  1102. /****************** Bit definition for RCC_APB2ENR register *****************/
  1103. #define RCC_APB2ENR_AFIOEN_Pos (0U)
  1104. #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
  1105. #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
  1106. #define RCC_APB2ENR_IOPAEN_Pos (2U)
  1107. #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
  1108. #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
  1109. #define RCC_APB2ENR_IOPBEN_Pos (3U)
  1110. #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
  1111. #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
  1112. #define RCC_APB2ENR_IOPCEN_Pos (4U)
  1113. #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
  1114. #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
  1115. #define RCC_APB2ENR_IOPDEN_Pos (5U)
  1116. #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
  1117. #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
  1118. #define RCC_APB2ENR_ADC1EN_Pos (9U)
  1119. #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
  1120. #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
  1121. #define RCC_APB2ENR_ADC2EN_Pos (10U)
  1122. #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
  1123. #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
  1124. #define RCC_APB2ENR_TIM1EN_Pos (11U)
  1125. #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
  1126. #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
  1127. #define RCC_APB2ENR_SPI1EN_Pos (12U)
  1128. #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
  1129. #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
  1130. #define RCC_APB2ENR_USART1EN_Pos (14U)
  1131. #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
  1132. #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
  1133. #define RCC_APB2ENR_IOPEEN_Pos (6U)
  1134. #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
  1135. #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
  1136. /***************** Bit definition for RCC_APB1ENR register ******************/
  1137. #define RCC_APB1ENR_TIM2EN_Pos (0U)
  1138. #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
  1139. #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
  1140. #define RCC_APB1ENR_TIM3EN_Pos (1U)
  1141. #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
  1142. #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
  1143. #define RCC_APB1ENR_WWDGEN_Pos (11U)
  1144. #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
  1145. #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
  1146. #define RCC_APB1ENR_USART2EN_Pos (17U)
  1147. #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
  1148. #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
  1149. #define RCC_APB1ENR_I2C1EN_Pos (21U)
  1150. #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
  1151. #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
  1152. #define RCC_APB1ENR_CAN1EN_Pos (25U)
  1153. #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
  1154. #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
  1155. #define RCC_APB1ENR_BKPEN_Pos (27U)
  1156. #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
  1157. #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
  1158. #define RCC_APB1ENR_PWREN_Pos (28U)
  1159. #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
  1160. #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
  1161. #define RCC_APB1ENR_TIM4EN_Pos (2U)
  1162. #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
  1163. #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
  1164. #define RCC_APB1ENR_SPI2EN_Pos (14U)
  1165. #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
  1166. #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
  1167. #define RCC_APB1ENR_USART3EN_Pos (18U)
  1168. #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
  1169. #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
  1170. #define RCC_APB1ENR_I2C2EN_Pos (22U)
  1171. #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
  1172. #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
  1173. #define RCC_APB1ENR_USBEN_Pos (23U)
  1174. #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
  1175. #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
  1176. /******************* Bit definition for RCC_BDCR register *******************/
  1177. #define RCC_BDCR_LSEON_Pos (0U)
  1178. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  1179. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
  1180. #define RCC_BDCR_LSERDY_Pos (1U)
  1181. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  1182. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
  1183. #define RCC_BDCR_LSEBYP_Pos (2U)
  1184. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  1185. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
  1186. #define RCC_BDCR_RTCSEL_Pos (8U)
  1187. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  1188. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
  1189. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  1190. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  1191. /*!< RTC congiguration */
  1192. #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
  1193. #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
  1194. #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
  1195. #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
  1196. #define RCC_BDCR_RTCEN_Pos (15U)
  1197. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  1198. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
  1199. #define RCC_BDCR_BDRST_Pos (16U)
  1200. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  1201. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
  1202. /******************* Bit definition for RCC_CSR register ********************/
  1203. #define RCC_CSR_LSION_Pos (0U)
  1204. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  1205. #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
  1206. #define RCC_CSR_LSIRDY_Pos (1U)
  1207. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  1208. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
  1209. #define RCC_CSR_RMVF_Pos (24U)
  1210. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
  1211. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
  1212. #define RCC_CSR_PINRSTF_Pos (26U)
  1213. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  1214. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
  1215. #define RCC_CSR_PORRSTF_Pos (27U)
  1216. #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
  1217. #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
  1218. #define RCC_CSR_SFTRSTF_Pos (28U)
  1219. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  1220. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
  1221. #define RCC_CSR_IWDGRSTF_Pos (29U)
  1222. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  1223. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
  1224. #define RCC_CSR_WWDGRSTF_Pos (30U)
  1225. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  1226. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
  1227. #define RCC_CSR_LPWRRSTF_Pos (31U)
  1228. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  1229. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
  1230. /******************************************************************************/
  1231. /* */
  1232. /* General Purpose and Alternate Function I/O */
  1233. /* */
  1234. /******************************************************************************/
  1235. /******************* Bit definition for GPIO_CRL register *******************/
  1236. #define GPIO_CRL_MODE_Pos (0U)
  1237. #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
  1238. #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
  1239. #define GPIO_CRL_MODE0_Pos (0U)
  1240. #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
  1241. #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
  1242. #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
  1243. #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
  1244. #define GPIO_CRL_MODE1_Pos (4U)
  1245. #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
  1246. #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
  1247. #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
  1248. #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
  1249. #define GPIO_CRL_MODE2_Pos (8U)
  1250. #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
  1251. #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
  1252. #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
  1253. #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
  1254. #define GPIO_CRL_MODE3_Pos (12U)
  1255. #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
  1256. #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
  1257. #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
  1258. #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
  1259. #define GPIO_CRL_MODE4_Pos (16U)
  1260. #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
  1261. #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
  1262. #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
  1263. #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
  1264. #define GPIO_CRL_MODE5_Pos (20U)
  1265. #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
  1266. #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
  1267. #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
  1268. #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
  1269. #define GPIO_CRL_MODE6_Pos (24U)
  1270. #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
  1271. #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
  1272. #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
  1273. #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
  1274. #define GPIO_CRL_MODE7_Pos (28U)
  1275. #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
  1276. #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
  1277. #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
  1278. #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
  1279. #define GPIO_CRL_CNF_Pos (2U)
  1280. #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
  1281. #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
  1282. #define GPIO_CRL_CNF0_Pos (2U)
  1283. #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
  1284. #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
  1285. #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
  1286. #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
  1287. #define GPIO_CRL_CNF1_Pos (6U)
  1288. #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
  1289. #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
  1290. #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
  1291. #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
  1292. #define GPIO_CRL_CNF2_Pos (10U)
  1293. #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
  1294. #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
  1295. #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
  1296. #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
  1297. #define GPIO_CRL_CNF3_Pos (14U)
  1298. #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
  1299. #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
  1300. #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
  1301. #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
  1302. #define GPIO_CRL_CNF4_Pos (18U)
  1303. #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
  1304. #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
  1305. #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
  1306. #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
  1307. #define GPIO_CRL_CNF5_Pos (22U)
  1308. #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
  1309. #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
  1310. #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
  1311. #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
  1312. #define GPIO_CRL_CNF6_Pos (26U)
  1313. #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
  1314. #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
  1315. #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
  1316. #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
  1317. #define GPIO_CRL_CNF7_Pos (30U)
  1318. #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
  1319. #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
  1320. #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
  1321. #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
  1322. /******************* Bit definition for GPIO_CRH register *******************/
  1323. #define GPIO_CRH_MODE_Pos (0U)
  1324. #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
  1325. #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
  1326. #define GPIO_CRH_MODE8_Pos (0U)
  1327. #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
  1328. #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
  1329. #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
  1330. #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
  1331. #define GPIO_CRH_MODE9_Pos (4U)
  1332. #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
  1333. #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
  1334. #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
  1335. #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
  1336. #define GPIO_CRH_MODE10_Pos (8U)
  1337. #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
  1338. #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
  1339. #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
  1340. #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
  1341. #define GPIO_CRH_MODE11_Pos (12U)
  1342. #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
  1343. #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
  1344. #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
  1345. #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
  1346. #define GPIO_CRH_MODE12_Pos (16U)
  1347. #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
  1348. #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
  1349. #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
  1350. #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
  1351. #define GPIO_CRH_MODE13_Pos (20U)
  1352. #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
  1353. #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
  1354. #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
  1355. #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
  1356. #define GPIO_CRH_MODE14_Pos (24U)
  1357. #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
  1358. #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
  1359. #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
  1360. #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
  1361. #define GPIO_CRH_MODE15_Pos (28U)
  1362. #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
  1363. #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
  1364. #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
  1365. #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
  1366. #define GPIO_CRH_CNF_Pos (2U)
  1367. #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
  1368. #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
  1369. #define GPIO_CRH_CNF8_Pos (2U)
  1370. #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
  1371. #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
  1372. #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
  1373. #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
  1374. #define GPIO_CRH_CNF9_Pos (6U)
  1375. #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
  1376. #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
  1377. #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
  1378. #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
  1379. #define GPIO_CRH_CNF10_Pos (10U)
  1380. #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
  1381. #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
  1382. #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
  1383. #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
  1384. #define GPIO_CRH_CNF11_Pos (14U)
  1385. #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
  1386. #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
  1387. #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
  1388. #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
  1389. #define GPIO_CRH_CNF12_Pos (18U)
  1390. #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
  1391. #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
  1392. #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
  1393. #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
  1394. #define GPIO_CRH_CNF13_Pos (22U)
  1395. #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
  1396. #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
  1397. #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
  1398. #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
  1399. #define GPIO_CRH_CNF14_Pos (26U)
  1400. #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
  1401. #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
  1402. #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
  1403. #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
  1404. #define GPIO_CRH_CNF15_Pos (30U)
  1405. #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
  1406. #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
  1407. #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
  1408. #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
  1409. /*!<****************** Bit definition for GPIO_IDR register *******************/
  1410. #define GPIO_IDR_IDR0_Pos (0U)
  1411. #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
  1412. #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
  1413. #define GPIO_IDR_IDR1_Pos (1U)
  1414. #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
  1415. #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
  1416. #define GPIO_IDR_IDR2_Pos (2U)
  1417. #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
  1418. #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
  1419. #define GPIO_IDR_IDR3_Pos (3U)
  1420. #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
  1421. #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
  1422. #define GPIO_IDR_IDR4_Pos (4U)
  1423. #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
  1424. #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
  1425. #define GPIO_IDR_IDR5_Pos (5U)
  1426. #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
  1427. #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
  1428. #define GPIO_IDR_IDR6_Pos (6U)
  1429. #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
  1430. #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
  1431. #define GPIO_IDR_IDR7_Pos (7U)
  1432. #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
  1433. #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
  1434. #define GPIO_IDR_IDR8_Pos (8U)
  1435. #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
  1436. #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
  1437. #define GPIO_IDR_IDR9_Pos (9U)
  1438. #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
  1439. #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
  1440. #define GPIO_IDR_IDR10_Pos (10U)
  1441. #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
  1442. #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
  1443. #define GPIO_IDR_IDR11_Pos (11U)
  1444. #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
  1445. #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
  1446. #define GPIO_IDR_IDR12_Pos (12U)
  1447. #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
  1448. #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
  1449. #define GPIO_IDR_IDR13_Pos (13U)
  1450. #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
  1451. #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
  1452. #define GPIO_IDR_IDR14_Pos (14U)
  1453. #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
  1454. #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
  1455. #define GPIO_IDR_IDR15_Pos (15U)
  1456. #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
  1457. #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
  1458. /******************* Bit definition for GPIO_ODR register *******************/
  1459. #define GPIO_ODR_ODR0_Pos (0U)
  1460. #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
  1461. #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
  1462. #define GPIO_ODR_ODR1_Pos (1U)
  1463. #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
  1464. #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
  1465. #define GPIO_ODR_ODR2_Pos (2U)
  1466. #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
  1467. #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
  1468. #define GPIO_ODR_ODR3_Pos (3U)
  1469. #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
  1470. #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
  1471. #define GPIO_ODR_ODR4_Pos (4U)
  1472. #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
  1473. #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
  1474. #define GPIO_ODR_ODR5_Pos (5U)
  1475. #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
  1476. #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
  1477. #define GPIO_ODR_ODR6_Pos (6U)
  1478. #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
  1479. #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
  1480. #define GPIO_ODR_ODR7_Pos (7U)
  1481. #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
  1482. #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
  1483. #define GPIO_ODR_ODR8_Pos (8U)
  1484. #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
  1485. #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
  1486. #define GPIO_ODR_ODR9_Pos (9U)
  1487. #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
  1488. #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
  1489. #define GPIO_ODR_ODR10_Pos (10U)
  1490. #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
  1491. #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
  1492. #define GPIO_ODR_ODR11_Pos (11U)
  1493. #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
  1494. #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
  1495. #define GPIO_ODR_ODR12_Pos (12U)
  1496. #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
  1497. #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
  1498. #define GPIO_ODR_ODR13_Pos (13U)
  1499. #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
  1500. #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
  1501. #define GPIO_ODR_ODR14_Pos (14U)
  1502. #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
  1503. #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
  1504. #define GPIO_ODR_ODR15_Pos (15U)
  1505. #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
  1506. #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
  1507. /****************** Bit definition for GPIO_BSRR register *******************/
  1508. #define GPIO_BSRR_BS0_Pos (0U)
  1509. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  1510. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
  1511. #define GPIO_BSRR_BS1_Pos (1U)
  1512. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  1513. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
  1514. #define GPIO_BSRR_BS2_Pos (2U)
  1515. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  1516. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
  1517. #define GPIO_BSRR_BS3_Pos (3U)
  1518. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  1519. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
  1520. #define GPIO_BSRR_BS4_Pos (4U)
  1521. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  1522. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
  1523. #define GPIO_BSRR_BS5_Pos (5U)
  1524. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  1525. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
  1526. #define GPIO_BSRR_BS6_Pos (6U)
  1527. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  1528. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
  1529. #define GPIO_BSRR_BS7_Pos (7U)
  1530. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  1531. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
  1532. #define GPIO_BSRR_BS8_Pos (8U)
  1533. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  1534. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
  1535. #define GPIO_BSRR_BS9_Pos (9U)
  1536. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  1537. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
  1538. #define GPIO_BSRR_BS10_Pos (10U)
  1539. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  1540. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
  1541. #define GPIO_BSRR_BS11_Pos (11U)
  1542. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  1543. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
  1544. #define GPIO_BSRR_BS12_Pos (12U)
  1545. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  1546. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
  1547. #define GPIO_BSRR_BS13_Pos (13U)
  1548. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  1549. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
  1550. #define GPIO_BSRR_BS14_Pos (14U)
  1551. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  1552. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
  1553. #define GPIO_BSRR_BS15_Pos (15U)
  1554. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  1555. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
  1556. #define GPIO_BSRR_BR0_Pos (16U)
  1557. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  1558. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
  1559. #define GPIO_BSRR_BR1_Pos (17U)
  1560. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  1561. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
  1562. #define GPIO_BSRR_BR2_Pos (18U)
  1563. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  1564. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
  1565. #define GPIO_BSRR_BR3_Pos (19U)
  1566. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  1567. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
  1568. #define GPIO_BSRR_BR4_Pos (20U)
  1569. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  1570. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
  1571. #define GPIO_BSRR_BR5_Pos (21U)
  1572. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  1573. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
  1574. #define GPIO_BSRR_BR6_Pos (22U)
  1575. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  1576. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
  1577. #define GPIO_BSRR_BR7_Pos (23U)
  1578. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  1579. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
  1580. #define GPIO_BSRR_BR8_Pos (24U)
  1581. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  1582. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
  1583. #define GPIO_BSRR_BR9_Pos (25U)
  1584. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  1585. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
  1586. #define GPIO_BSRR_BR10_Pos (26U)
  1587. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  1588. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
  1589. #define GPIO_BSRR_BR11_Pos (27U)
  1590. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  1591. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
  1592. #define GPIO_BSRR_BR12_Pos (28U)
  1593. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  1594. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
  1595. #define GPIO_BSRR_BR13_Pos (29U)
  1596. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  1597. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
  1598. #define GPIO_BSRR_BR14_Pos (30U)
  1599. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  1600. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
  1601. #define GPIO_BSRR_BR15_Pos (31U)
  1602. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  1603. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
  1604. /******************* Bit definition for GPIO_BRR register *******************/
  1605. #define GPIO_BRR_BR0_Pos (0U)
  1606. #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
  1607. #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
  1608. #define GPIO_BRR_BR1_Pos (1U)
  1609. #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
  1610. #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
  1611. #define GPIO_BRR_BR2_Pos (2U)
  1612. #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
  1613. #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
  1614. #define GPIO_BRR_BR3_Pos (3U)
  1615. #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
  1616. #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
  1617. #define GPIO_BRR_BR4_Pos (4U)
  1618. #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
  1619. #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
  1620. #define GPIO_BRR_BR5_Pos (5U)
  1621. #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
  1622. #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
  1623. #define GPIO_BRR_BR6_Pos (6U)
  1624. #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
  1625. #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
  1626. #define GPIO_BRR_BR7_Pos (7U)
  1627. #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
  1628. #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
  1629. #define GPIO_BRR_BR8_Pos (8U)
  1630. #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
  1631. #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
  1632. #define GPIO_BRR_BR9_Pos (9U)
  1633. #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
  1634. #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
  1635. #define GPIO_BRR_BR10_Pos (10U)
  1636. #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
  1637. #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
  1638. #define GPIO_BRR_BR11_Pos (11U)
  1639. #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
  1640. #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
  1641. #define GPIO_BRR_BR12_Pos (12U)
  1642. #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
  1643. #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
  1644. #define GPIO_BRR_BR13_Pos (13U)
  1645. #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
  1646. #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
  1647. #define GPIO_BRR_BR14_Pos (14U)
  1648. #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
  1649. #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
  1650. #define GPIO_BRR_BR15_Pos (15U)
  1651. #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
  1652. #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
  1653. /****************** Bit definition for GPIO_LCKR register *******************/
  1654. #define GPIO_LCKR_LCK0_Pos (0U)
  1655. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  1656. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
  1657. #define GPIO_LCKR_LCK1_Pos (1U)
  1658. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  1659. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
  1660. #define GPIO_LCKR_LCK2_Pos (2U)
  1661. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  1662. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
  1663. #define GPIO_LCKR_LCK3_Pos (3U)
  1664. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  1665. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
  1666. #define GPIO_LCKR_LCK4_Pos (4U)
  1667. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  1668. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
  1669. #define GPIO_LCKR_LCK5_Pos (5U)
  1670. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  1671. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
  1672. #define GPIO_LCKR_LCK6_Pos (6U)
  1673. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  1674. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
  1675. #define GPIO_LCKR_LCK7_Pos (7U)
  1676. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  1677. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
  1678. #define GPIO_LCKR_LCK8_Pos (8U)
  1679. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  1680. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
  1681. #define GPIO_LCKR_LCK9_Pos (9U)
  1682. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  1683. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
  1684. #define GPIO_LCKR_LCK10_Pos (10U)
  1685. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  1686. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
  1687. #define GPIO_LCKR_LCK11_Pos (11U)
  1688. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  1689. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
  1690. #define GPIO_LCKR_LCK12_Pos (12U)
  1691. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  1692. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
  1693. #define GPIO_LCKR_LCK13_Pos (13U)
  1694. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  1695. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
  1696. #define GPIO_LCKR_LCK14_Pos (14U)
  1697. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  1698. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
  1699. #define GPIO_LCKR_LCK15_Pos (15U)
  1700. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  1701. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
  1702. #define GPIO_LCKR_LCKK_Pos (16U)
  1703. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  1704. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
  1705. /*----------------------------------------------------------------------------*/
  1706. /****************** Bit definition for AFIO_EVCR register *******************/
  1707. #define AFIO_EVCR_PIN_Pos (0U)
  1708. #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
  1709. #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
  1710. #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
  1711. #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
  1712. #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
  1713. #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
  1714. /*!< PIN configuration */
  1715. #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
  1716. #define AFIO_EVCR_PIN_PX1_Pos (0U)
  1717. #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
  1718. #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
  1719. #define AFIO_EVCR_PIN_PX2_Pos (1U)
  1720. #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
  1721. #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
  1722. #define AFIO_EVCR_PIN_PX3_Pos (0U)
  1723. #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
  1724. #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
  1725. #define AFIO_EVCR_PIN_PX4_Pos (2U)
  1726. #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
  1727. #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
  1728. #define AFIO_EVCR_PIN_PX5_Pos (0U)
  1729. #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
  1730. #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
  1731. #define AFIO_EVCR_PIN_PX6_Pos (1U)
  1732. #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
  1733. #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
  1734. #define AFIO_EVCR_PIN_PX7_Pos (0U)
  1735. #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
  1736. #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
  1737. #define AFIO_EVCR_PIN_PX8_Pos (3U)
  1738. #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
  1739. #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
  1740. #define AFIO_EVCR_PIN_PX9_Pos (0U)
  1741. #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
  1742. #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
  1743. #define AFIO_EVCR_PIN_PX10_Pos (1U)
  1744. #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
  1745. #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
  1746. #define AFIO_EVCR_PIN_PX11_Pos (0U)
  1747. #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
  1748. #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
  1749. #define AFIO_EVCR_PIN_PX12_Pos (2U)
  1750. #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
  1751. #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
  1752. #define AFIO_EVCR_PIN_PX13_Pos (0U)
  1753. #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
  1754. #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
  1755. #define AFIO_EVCR_PIN_PX14_Pos (1U)
  1756. #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
  1757. #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
  1758. #define AFIO_EVCR_PIN_PX15_Pos (0U)
  1759. #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
  1760. #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
  1761. #define AFIO_EVCR_PORT_Pos (4U)
  1762. #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
  1763. #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
  1764. #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
  1765. #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
  1766. #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
  1767. /*!< PORT configuration */
  1768. #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
  1769. #define AFIO_EVCR_PORT_PB_Pos (4U)
  1770. #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
  1771. #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
  1772. #define AFIO_EVCR_PORT_PC_Pos (5U)
  1773. #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
  1774. #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
  1775. #define AFIO_EVCR_PORT_PD_Pos (4U)
  1776. #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
  1777. #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
  1778. #define AFIO_EVCR_PORT_PE_Pos (6U)
  1779. #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
  1780. #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
  1781. #define AFIO_EVCR_EVOE_Pos (7U)
  1782. #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
  1783. #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
  1784. /****************** Bit definition for AFIO_MAPR register *******************/
  1785. #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
  1786. #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
  1787. #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
  1788. #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
  1789. #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
  1790. #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
  1791. #define AFIO_MAPR_USART1_REMAP_Pos (2U)
  1792. #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
  1793. #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
  1794. #define AFIO_MAPR_USART2_REMAP_Pos (3U)
  1795. #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
  1796. #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
  1797. #define AFIO_MAPR_USART3_REMAP_Pos (4U)
  1798. #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
  1799. #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
  1800. #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
  1801. #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
  1802. /* USART3_REMAP configuration */
  1803. #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
  1804. #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
  1805. #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
  1806. #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
  1807. #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
  1808. #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
  1809. #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
  1810. #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
  1811. #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
  1812. #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
  1813. #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
  1814. #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
  1815. /*!< TIM1_REMAP configuration */
  1816. #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
  1817. #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
  1818. #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
  1819. #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
  1820. #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
  1821. #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
  1822. #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
  1823. #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
  1824. #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
  1825. #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
  1826. #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
  1827. #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
  1828. /*!< TIM2_REMAP configuration */
  1829. #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
  1830. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
  1831. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
  1832. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
  1833. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
  1834. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
  1835. #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
  1836. #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
  1837. #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
  1838. #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
  1839. #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
  1840. #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
  1841. #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
  1842. #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
  1843. #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
  1844. /*!< TIM3_REMAP configuration */
  1845. #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
  1846. #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
  1847. #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
  1848. #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
  1849. #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
  1850. #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
  1851. #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
  1852. #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
  1853. #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
  1854. #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
  1855. #define AFIO_MAPR_CAN_REMAP_Pos (13U)
  1856. #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
  1857. #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
  1858. #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
  1859. #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
  1860. /*!< CAN_REMAP configuration */
  1861. #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
  1862. #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
  1863. #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
  1864. #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
  1865. #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
  1866. #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
  1867. #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
  1868. #define AFIO_MAPR_PD01_REMAP_Pos (15U)
  1869. #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
  1870. #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
  1871. /*!< SWJ_CFG configuration */
  1872. #define AFIO_MAPR_SWJ_CFG_Pos (24U)
  1873. #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
  1874. #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
  1875. #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
  1876. #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
  1877. #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
  1878. #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
  1879. #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
  1880. #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
  1881. #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
  1882. #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
  1883. #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
  1884. #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
  1885. #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
  1886. #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
  1887. #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
  1888. /***************** Bit definition for AFIO_EXTICR1 register *****************/
  1889. #define AFIO_EXTICR1_EXTI0_Pos (0U)
  1890. #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
  1891. #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
  1892. #define AFIO_EXTICR1_EXTI1_Pos (4U)
  1893. #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
  1894. #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
  1895. #define AFIO_EXTICR1_EXTI2_Pos (8U)
  1896. #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
  1897. #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
  1898. #define AFIO_EXTICR1_EXTI3_Pos (12U)
  1899. #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
  1900. #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
  1901. /*!< EXTI0 configuration */
  1902. #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
  1903. #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
  1904. #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
  1905. #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
  1906. #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
  1907. #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
  1908. #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
  1909. #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
  1910. #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
  1911. #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
  1912. #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
  1913. #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
  1914. #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
  1915. #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
  1916. #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
  1917. #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
  1918. #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
  1919. #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
  1920. #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
  1921. /*!< EXTI1 configuration */
  1922. #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
  1923. #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
  1924. #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
  1925. #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
  1926. #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
  1927. #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
  1928. #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
  1929. #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
  1930. #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
  1931. #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
  1932. #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
  1933. #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
  1934. #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
  1935. #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
  1936. #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
  1937. #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
  1938. #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
  1939. #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
  1940. #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
  1941. /*!< EXTI2 configuration */
  1942. #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
  1943. #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
  1944. #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
  1945. #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
  1946. #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
  1947. #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
  1948. #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
  1949. #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
  1950. #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
  1951. #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
  1952. #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
  1953. #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
  1954. #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
  1955. #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
  1956. #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
  1957. #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
  1958. #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
  1959. #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
  1960. #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
  1961. /*!< EXTI3 configuration */
  1962. #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
  1963. #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
  1964. #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
  1965. #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
  1966. #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
  1967. #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
  1968. #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
  1969. #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
  1970. #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
  1971. #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
  1972. #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
  1973. #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
  1974. #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
  1975. #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
  1976. #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
  1977. #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
  1978. #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
  1979. #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
  1980. #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
  1981. /***************** Bit definition for AFIO_EXTICR2 register *****************/
  1982. #define AFIO_EXTICR2_EXTI4_Pos (0U)
  1983. #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
  1984. #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
  1985. #define AFIO_EXTICR2_EXTI5_Pos (4U)
  1986. #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
  1987. #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
  1988. #define AFIO_EXTICR2_EXTI6_Pos (8U)
  1989. #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
  1990. #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
  1991. #define AFIO_EXTICR2_EXTI7_Pos (12U)
  1992. #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
  1993. #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
  1994. /*!< EXTI4 configuration */
  1995. #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
  1996. #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
  1997. #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
  1998. #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
  1999. #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
  2000. #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
  2001. #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
  2002. #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
  2003. #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
  2004. #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
  2005. #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
  2006. #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
  2007. #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
  2008. #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
  2009. #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
  2010. #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
  2011. #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
  2012. #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
  2013. #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
  2014. /* EXTI5 configuration */
  2015. #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
  2016. #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
  2017. #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
  2018. #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
  2019. #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
  2020. #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
  2021. #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
  2022. #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
  2023. #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
  2024. #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
  2025. #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
  2026. #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
  2027. #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
  2028. #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
  2029. #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
  2030. #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
  2031. #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
  2032. #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
  2033. #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
  2034. /*!< EXTI6 configuration */
  2035. #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
  2036. #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
  2037. #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
  2038. #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
  2039. #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
  2040. #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
  2041. #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
  2042. #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
  2043. #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
  2044. #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
  2045. #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
  2046. #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
  2047. #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
  2048. #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
  2049. #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
  2050. #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
  2051. #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
  2052. #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
  2053. #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
  2054. /*!< EXTI7 configuration */
  2055. #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
  2056. #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
  2057. #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
  2058. #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
  2059. #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
  2060. #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
  2061. #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
  2062. #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
  2063. #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
  2064. #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
  2065. #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
  2066. #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
  2067. #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
  2068. #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
  2069. #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
  2070. #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
  2071. #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
  2072. #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
  2073. #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
  2074. /***************** Bit definition for AFIO_EXTICR3 register *****************/
  2075. #define AFIO_EXTICR3_EXTI8_Pos (0U)
  2076. #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
  2077. #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
  2078. #define AFIO_EXTICR3_EXTI9_Pos (4U)
  2079. #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
  2080. #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
  2081. #define AFIO_EXTICR3_EXTI10_Pos (8U)
  2082. #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
  2083. #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
  2084. #define AFIO_EXTICR3_EXTI11_Pos (12U)
  2085. #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
  2086. #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
  2087. /*!< EXTI8 configuration */
  2088. #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
  2089. #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
  2090. #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
  2091. #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
  2092. #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
  2093. #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
  2094. #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
  2095. #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
  2096. #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
  2097. #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
  2098. #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
  2099. #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
  2100. #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
  2101. #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
  2102. #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
  2103. #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
  2104. #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
  2105. #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
  2106. #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
  2107. /*!< EXTI9 configuration */
  2108. #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
  2109. #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
  2110. #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
  2111. #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
  2112. #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
  2113. #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
  2114. #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
  2115. #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
  2116. #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
  2117. #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
  2118. #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
  2119. #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
  2120. #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
  2121. #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
  2122. #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
  2123. #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
  2124. #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
  2125. #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
  2126. #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
  2127. /*!< EXTI10 configuration */
  2128. #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
  2129. #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
  2130. #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
  2131. #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
  2132. #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
  2133. #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
  2134. #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
  2135. #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
  2136. #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
  2137. #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
  2138. #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
  2139. #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
  2140. #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
  2141. #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
  2142. #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
  2143. #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
  2144. #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
  2145. #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
  2146. #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
  2147. /*!< EXTI11 configuration */
  2148. #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
  2149. #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
  2150. #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
  2151. #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
  2152. #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
  2153. #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
  2154. #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
  2155. #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
  2156. #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
  2157. #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
  2158. #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
  2159. #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
  2160. #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
  2161. #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
  2162. #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
  2163. #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
  2164. #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
  2165. #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
  2166. #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
  2167. /***************** Bit definition for AFIO_EXTICR4 register *****************/
  2168. #define AFIO_EXTICR4_EXTI12_Pos (0U)
  2169. #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
  2170. #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
  2171. #define AFIO_EXTICR4_EXTI13_Pos (4U)
  2172. #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
  2173. #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
  2174. #define AFIO_EXTICR4_EXTI14_Pos (8U)
  2175. #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
  2176. #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
  2177. #define AFIO_EXTICR4_EXTI15_Pos (12U)
  2178. #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
  2179. #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
  2180. /* EXTI12 configuration */
  2181. #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
  2182. #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
  2183. #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
  2184. #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
  2185. #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
  2186. #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
  2187. #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
  2188. #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
  2189. #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
  2190. #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
  2191. #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
  2192. #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
  2193. #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
  2194. #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
  2195. #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
  2196. #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
  2197. #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
  2198. #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
  2199. #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
  2200. /* EXTI13 configuration */
  2201. #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
  2202. #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
  2203. #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
  2204. #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
  2205. #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
  2206. #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
  2207. #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
  2208. #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
  2209. #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
  2210. #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
  2211. #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
  2212. #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
  2213. #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
  2214. #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
  2215. #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
  2216. #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
  2217. #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
  2218. #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
  2219. #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
  2220. /*!< EXTI14 configuration */
  2221. #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
  2222. #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
  2223. #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
  2224. #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
  2225. #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
  2226. #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
  2227. #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
  2228. #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
  2229. #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
  2230. #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
  2231. #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
  2232. #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
  2233. #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
  2234. #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
  2235. #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
  2236. #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
  2237. #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
  2238. #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
  2239. #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
  2240. /*!< EXTI15 configuration */
  2241. #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
  2242. #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
  2243. #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
  2244. #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
  2245. #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
  2246. #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
  2247. #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
  2248. #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
  2249. #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
  2250. #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
  2251. #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
  2252. #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
  2253. #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
  2254. #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
  2255. #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
  2256. #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
  2257. #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
  2258. #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
  2259. #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
  2260. /****************** Bit definition for AFIO_MAPR2 register ******************/
  2261. /******************************************************************************/
  2262. /* */
  2263. /* External Interrupt/Event Controller */
  2264. /* */
  2265. /******************************************************************************/
  2266. /******************* Bit definition for EXTI_IMR register *******************/
  2267. #define EXTI_IMR_MR0_Pos (0U)
  2268. #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
  2269. #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
  2270. #define EXTI_IMR_MR1_Pos (1U)
  2271. #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
  2272. #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
  2273. #define EXTI_IMR_MR2_Pos (2U)
  2274. #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
  2275. #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
  2276. #define EXTI_IMR_MR3_Pos (3U)
  2277. #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
  2278. #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
  2279. #define EXTI_IMR_MR4_Pos (4U)
  2280. #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
  2281. #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
  2282. #define EXTI_IMR_MR5_Pos (5U)
  2283. #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
  2284. #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
  2285. #define EXTI_IMR_MR6_Pos (6U)
  2286. #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
  2287. #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
  2288. #define EXTI_IMR_MR7_Pos (7U)
  2289. #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
  2290. #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
  2291. #define EXTI_IMR_MR8_Pos (8U)
  2292. #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
  2293. #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
  2294. #define EXTI_IMR_MR9_Pos (9U)
  2295. #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
  2296. #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
  2297. #define EXTI_IMR_MR10_Pos (10U)
  2298. #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
  2299. #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
  2300. #define EXTI_IMR_MR11_Pos (11U)
  2301. #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
  2302. #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
  2303. #define EXTI_IMR_MR12_Pos (12U)
  2304. #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
  2305. #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
  2306. #define EXTI_IMR_MR13_Pos (13U)
  2307. #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
  2308. #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
  2309. #define EXTI_IMR_MR14_Pos (14U)
  2310. #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
  2311. #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
  2312. #define EXTI_IMR_MR15_Pos (15U)
  2313. #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
  2314. #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
  2315. #define EXTI_IMR_MR16_Pos (16U)
  2316. #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
  2317. #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
  2318. #define EXTI_IMR_MR17_Pos (17U)
  2319. #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
  2320. #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
  2321. #define EXTI_IMR_MR18_Pos (18U)
  2322. #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
  2323. #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
  2324. /* References Defines */
  2325. #define EXTI_IMR_IM0 EXTI_IMR_MR0
  2326. #define EXTI_IMR_IM1 EXTI_IMR_MR1
  2327. #define EXTI_IMR_IM2 EXTI_IMR_MR2
  2328. #define EXTI_IMR_IM3 EXTI_IMR_MR3
  2329. #define EXTI_IMR_IM4 EXTI_IMR_MR4
  2330. #define EXTI_IMR_IM5 EXTI_IMR_MR5
  2331. #define EXTI_IMR_IM6 EXTI_IMR_MR6
  2332. #define EXTI_IMR_IM7 EXTI_IMR_MR7
  2333. #define EXTI_IMR_IM8 EXTI_IMR_MR8
  2334. #define EXTI_IMR_IM9 EXTI_IMR_MR9
  2335. #define EXTI_IMR_IM10 EXTI_IMR_MR10
  2336. #define EXTI_IMR_IM11 EXTI_IMR_MR11
  2337. #define EXTI_IMR_IM12 EXTI_IMR_MR12
  2338. #define EXTI_IMR_IM13 EXTI_IMR_MR13
  2339. #define EXTI_IMR_IM14 EXTI_IMR_MR14
  2340. #define EXTI_IMR_IM15 EXTI_IMR_MR15
  2341. #define EXTI_IMR_IM16 EXTI_IMR_MR16
  2342. #define EXTI_IMR_IM17 EXTI_IMR_MR17
  2343. #define EXTI_IMR_IM18 EXTI_IMR_MR18
  2344. #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
  2345. /******************* Bit definition for EXTI_EMR register *******************/
  2346. #define EXTI_EMR_MR0_Pos (0U)
  2347. #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
  2348. #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
  2349. #define EXTI_EMR_MR1_Pos (1U)
  2350. #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
  2351. #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
  2352. #define EXTI_EMR_MR2_Pos (2U)
  2353. #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
  2354. #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
  2355. #define EXTI_EMR_MR3_Pos (3U)
  2356. #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
  2357. #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
  2358. #define EXTI_EMR_MR4_Pos (4U)
  2359. #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
  2360. #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
  2361. #define EXTI_EMR_MR5_Pos (5U)
  2362. #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
  2363. #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
  2364. #define EXTI_EMR_MR6_Pos (6U)
  2365. #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
  2366. #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
  2367. #define EXTI_EMR_MR7_Pos (7U)
  2368. #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
  2369. #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
  2370. #define EXTI_EMR_MR8_Pos (8U)
  2371. #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
  2372. #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
  2373. #define EXTI_EMR_MR9_Pos (9U)
  2374. #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
  2375. #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
  2376. #define EXTI_EMR_MR10_Pos (10U)
  2377. #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
  2378. #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
  2379. #define EXTI_EMR_MR11_Pos (11U)
  2380. #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
  2381. #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
  2382. #define EXTI_EMR_MR12_Pos (12U)
  2383. #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
  2384. #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
  2385. #define EXTI_EMR_MR13_Pos (13U)
  2386. #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
  2387. #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
  2388. #define EXTI_EMR_MR14_Pos (14U)
  2389. #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
  2390. #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
  2391. #define EXTI_EMR_MR15_Pos (15U)
  2392. #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
  2393. #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
  2394. #define EXTI_EMR_MR16_Pos (16U)
  2395. #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
  2396. #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
  2397. #define EXTI_EMR_MR17_Pos (17U)
  2398. #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
  2399. #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
  2400. #define EXTI_EMR_MR18_Pos (18U)
  2401. #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
  2402. #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
  2403. /* References Defines */
  2404. #define EXTI_EMR_EM0 EXTI_EMR_MR0
  2405. #define EXTI_EMR_EM1 EXTI_EMR_MR1
  2406. #define EXTI_EMR_EM2 EXTI_EMR_MR2
  2407. #define EXTI_EMR_EM3 EXTI_EMR_MR3
  2408. #define EXTI_EMR_EM4 EXTI_EMR_MR4
  2409. #define EXTI_EMR_EM5 EXTI_EMR_MR5
  2410. #define EXTI_EMR_EM6 EXTI_EMR_MR6
  2411. #define EXTI_EMR_EM7 EXTI_EMR_MR7
  2412. #define EXTI_EMR_EM8 EXTI_EMR_MR8
  2413. #define EXTI_EMR_EM9 EXTI_EMR_MR9
  2414. #define EXTI_EMR_EM10 EXTI_EMR_MR10
  2415. #define EXTI_EMR_EM11 EXTI_EMR_MR11
  2416. #define EXTI_EMR_EM12 EXTI_EMR_MR12
  2417. #define EXTI_EMR_EM13 EXTI_EMR_MR13
  2418. #define EXTI_EMR_EM14 EXTI_EMR_MR14
  2419. #define EXTI_EMR_EM15 EXTI_EMR_MR15
  2420. #define EXTI_EMR_EM16 EXTI_EMR_MR16
  2421. #define EXTI_EMR_EM17 EXTI_EMR_MR17
  2422. #define EXTI_EMR_EM18 EXTI_EMR_MR18
  2423. /****************** Bit definition for EXTI_RTSR register *******************/
  2424. #define EXTI_RTSR_TR0_Pos (0U)
  2425. #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
  2426. #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
  2427. #define EXTI_RTSR_TR1_Pos (1U)
  2428. #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
  2429. #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
  2430. #define EXTI_RTSR_TR2_Pos (2U)
  2431. #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
  2432. #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
  2433. #define EXTI_RTSR_TR3_Pos (3U)
  2434. #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
  2435. #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
  2436. #define EXTI_RTSR_TR4_Pos (4U)
  2437. #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
  2438. #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
  2439. #define EXTI_RTSR_TR5_Pos (5U)
  2440. #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
  2441. #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
  2442. #define EXTI_RTSR_TR6_Pos (6U)
  2443. #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
  2444. #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
  2445. #define EXTI_RTSR_TR7_Pos (7U)
  2446. #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
  2447. #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
  2448. #define EXTI_RTSR_TR8_Pos (8U)
  2449. #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
  2450. #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
  2451. #define EXTI_RTSR_TR9_Pos (9U)
  2452. #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
  2453. #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
  2454. #define EXTI_RTSR_TR10_Pos (10U)
  2455. #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
  2456. #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
  2457. #define EXTI_RTSR_TR11_Pos (11U)
  2458. #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
  2459. #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
  2460. #define EXTI_RTSR_TR12_Pos (12U)
  2461. #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
  2462. #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
  2463. #define EXTI_RTSR_TR13_Pos (13U)
  2464. #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
  2465. #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
  2466. #define EXTI_RTSR_TR14_Pos (14U)
  2467. #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
  2468. #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
  2469. #define EXTI_RTSR_TR15_Pos (15U)
  2470. #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
  2471. #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
  2472. #define EXTI_RTSR_TR16_Pos (16U)
  2473. #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
  2474. #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
  2475. #define EXTI_RTSR_TR17_Pos (17U)
  2476. #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
  2477. #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
  2478. #define EXTI_RTSR_TR18_Pos (18U)
  2479. #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
  2480. #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
  2481. /* References Defines */
  2482. #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
  2483. #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
  2484. #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
  2485. #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
  2486. #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
  2487. #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
  2488. #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
  2489. #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
  2490. #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
  2491. #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
  2492. #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
  2493. #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
  2494. #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
  2495. #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
  2496. #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
  2497. #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
  2498. #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
  2499. #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
  2500. #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
  2501. /****************** Bit definition for EXTI_FTSR register *******************/
  2502. #define EXTI_FTSR_TR0_Pos (0U)
  2503. #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
  2504. #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
  2505. #define EXTI_FTSR_TR1_Pos (1U)
  2506. #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
  2507. #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
  2508. #define EXTI_FTSR_TR2_Pos (2U)
  2509. #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
  2510. #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
  2511. #define EXTI_FTSR_TR3_Pos (3U)
  2512. #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
  2513. #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
  2514. #define EXTI_FTSR_TR4_Pos (4U)
  2515. #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
  2516. #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
  2517. #define EXTI_FTSR_TR5_Pos (5U)
  2518. #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
  2519. #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
  2520. #define EXTI_FTSR_TR6_Pos (6U)
  2521. #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
  2522. #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
  2523. #define EXTI_FTSR_TR7_Pos (7U)
  2524. #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
  2525. #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
  2526. #define EXTI_FTSR_TR8_Pos (8U)
  2527. #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
  2528. #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
  2529. #define EXTI_FTSR_TR9_Pos (9U)
  2530. #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
  2531. #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
  2532. #define EXTI_FTSR_TR10_Pos (10U)
  2533. #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
  2534. #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
  2535. #define EXTI_FTSR_TR11_Pos (11U)
  2536. #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
  2537. #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
  2538. #define EXTI_FTSR_TR12_Pos (12U)
  2539. #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
  2540. #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
  2541. #define EXTI_FTSR_TR13_Pos (13U)
  2542. #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
  2543. #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
  2544. #define EXTI_FTSR_TR14_Pos (14U)
  2545. #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
  2546. #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
  2547. #define EXTI_FTSR_TR15_Pos (15U)
  2548. #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
  2549. #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
  2550. #define EXTI_FTSR_TR16_Pos (16U)
  2551. #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
  2552. #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
  2553. #define EXTI_FTSR_TR17_Pos (17U)
  2554. #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
  2555. #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
  2556. #define EXTI_FTSR_TR18_Pos (18U)
  2557. #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
  2558. #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
  2559. /* References Defines */
  2560. #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
  2561. #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
  2562. #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
  2563. #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
  2564. #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
  2565. #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
  2566. #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
  2567. #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
  2568. #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
  2569. #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
  2570. #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
  2571. #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
  2572. #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
  2573. #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
  2574. #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
  2575. #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
  2576. #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
  2577. #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
  2578. #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
  2579. /****************** Bit definition for EXTI_SWIER register ******************/
  2580. #define EXTI_SWIER_SWIER0_Pos (0U)
  2581. #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
  2582. #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
  2583. #define EXTI_SWIER_SWIER1_Pos (1U)
  2584. #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
  2585. #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
  2586. #define EXTI_SWIER_SWIER2_Pos (2U)
  2587. #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
  2588. #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
  2589. #define EXTI_SWIER_SWIER3_Pos (3U)
  2590. #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
  2591. #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
  2592. #define EXTI_SWIER_SWIER4_Pos (4U)
  2593. #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
  2594. #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
  2595. #define EXTI_SWIER_SWIER5_Pos (5U)
  2596. #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
  2597. #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
  2598. #define EXTI_SWIER_SWIER6_Pos (6U)
  2599. #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
  2600. #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
  2601. #define EXTI_SWIER_SWIER7_Pos (7U)
  2602. #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
  2603. #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
  2604. #define EXTI_SWIER_SWIER8_Pos (8U)
  2605. #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
  2606. #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
  2607. #define EXTI_SWIER_SWIER9_Pos (9U)
  2608. #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
  2609. #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
  2610. #define EXTI_SWIER_SWIER10_Pos (10U)
  2611. #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
  2612. #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
  2613. #define EXTI_SWIER_SWIER11_Pos (11U)
  2614. #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
  2615. #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
  2616. #define EXTI_SWIER_SWIER12_Pos (12U)
  2617. #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
  2618. #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
  2619. #define EXTI_SWIER_SWIER13_Pos (13U)
  2620. #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
  2621. #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
  2622. #define EXTI_SWIER_SWIER14_Pos (14U)
  2623. #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
  2624. #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
  2625. #define EXTI_SWIER_SWIER15_Pos (15U)
  2626. #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
  2627. #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
  2628. #define EXTI_SWIER_SWIER16_Pos (16U)
  2629. #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
  2630. #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
  2631. #define EXTI_SWIER_SWIER17_Pos (17U)
  2632. #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
  2633. #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
  2634. #define EXTI_SWIER_SWIER18_Pos (18U)
  2635. #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
  2636. #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
  2637. /* References Defines */
  2638. #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
  2639. #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
  2640. #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
  2641. #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
  2642. #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
  2643. #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
  2644. #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
  2645. #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
  2646. #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
  2647. #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
  2648. #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
  2649. #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
  2650. #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
  2651. #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
  2652. #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
  2653. #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
  2654. #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
  2655. #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
  2656. #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
  2657. /******************* Bit definition for EXTI_PR register ********************/
  2658. #define EXTI_PR_PR0_Pos (0U)
  2659. #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
  2660. #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
  2661. #define EXTI_PR_PR1_Pos (1U)
  2662. #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
  2663. #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
  2664. #define EXTI_PR_PR2_Pos (2U)
  2665. #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
  2666. #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
  2667. #define EXTI_PR_PR3_Pos (3U)
  2668. #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
  2669. #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
  2670. #define EXTI_PR_PR4_Pos (4U)
  2671. #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
  2672. #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
  2673. #define EXTI_PR_PR5_Pos (5U)
  2674. #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
  2675. #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
  2676. #define EXTI_PR_PR6_Pos (6U)
  2677. #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
  2678. #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
  2679. #define EXTI_PR_PR7_Pos (7U)
  2680. #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
  2681. #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
  2682. #define EXTI_PR_PR8_Pos (8U)
  2683. #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
  2684. #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
  2685. #define EXTI_PR_PR9_Pos (9U)
  2686. #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
  2687. #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
  2688. #define EXTI_PR_PR10_Pos (10U)
  2689. #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
  2690. #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
  2691. #define EXTI_PR_PR11_Pos (11U)
  2692. #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
  2693. #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
  2694. #define EXTI_PR_PR12_Pos (12U)
  2695. #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
  2696. #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
  2697. #define EXTI_PR_PR13_Pos (13U)
  2698. #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
  2699. #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
  2700. #define EXTI_PR_PR14_Pos (14U)
  2701. #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
  2702. #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
  2703. #define EXTI_PR_PR15_Pos (15U)
  2704. #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
  2705. #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
  2706. #define EXTI_PR_PR16_Pos (16U)
  2707. #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
  2708. #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
  2709. #define EXTI_PR_PR17_Pos (17U)
  2710. #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
  2711. #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
  2712. #define EXTI_PR_PR18_Pos (18U)
  2713. #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
  2714. #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
  2715. /* References Defines */
  2716. #define EXTI_PR_PIF0 EXTI_PR_PR0
  2717. #define EXTI_PR_PIF1 EXTI_PR_PR1
  2718. #define EXTI_PR_PIF2 EXTI_PR_PR2
  2719. #define EXTI_PR_PIF3 EXTI_PR_PR3
  2720. #define EXTI_PR_PIF4 EXTI_PR_PR4
  2721. #define EXTI_PR_PIF5 EXTI_PR_PR5
  2722. #define EXTI_PR_PIF6 EXTI_PR_PR6
  2723. #define EXTI_PR_PIF7 EXTI_PR_PR7
  2724. #define EXTI_PR_PIF8 EXTI_PR_PR8
  2725. #define EXTI_PR_PIF9 EXTI_PR_PR9
  2726. #define EXTI_PR_PIF10 EXTI_PR_PR10
  2727. #define EXTI_PR_PIF11 EXTI_PR_PR11
  2728. #define EXTI_PR_PIF12 EXTI_PR_PR12
  2729. #define EXTI_PR_PIF13 EXTI_PR_PR13
  2730. #define EXTI_PR_PIF14 EXTI_PR_PR14
  2731. #define EXTI_PR_PIF15 EXTI_PR_PR15
  2732. #define EXTI_PR_PIF16 EXTI_PR_PR16
  2733. #define EXTI_PR_PIF17 EXTI_PR_PR17
  2734. #define EXTI_PR_PIF18 EXTI_PR_PR18
  2735. /******************************************************************************/
  2736. /* */
  2737. /* DMA Controller */
  2738. /* */
  2739. /******************************************************************************/
  2740. /******************* Bit definition for DMA_ISR register ********************/
  2741. #define DMA_ISR_GIF1_Pos (0U)
  2742. #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
  2743. #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
  2744. #define DMA_ISR_TCIF1_Pos (1U)
  2745. #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
  2746. #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
  2747. #define DMA_ISR_HTIF1_Pos (2U)
  2748. #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
  2749. #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
  2750. #define DMA_ISR_TEIF1_Pos (3U)
  2751. #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
  2752. #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
  2753. #define DMA_ISR_GIF2_Pos (4U)
  2754. #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
  2755. #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
  2756. #define DMA_ISR_TCIF2_Pos (5U)
  2757. #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
  2758. #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
  2759. #define DMA_ISR_HTIF2_Pos (6U)
  2760. #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
  2761. #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
  2762. #define DMA_ISR_TEIF2_Pos (7U)
  2763. #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
  2764. #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
  2765. #define DMA_ISR_GIF3_Pos (8U)
  2766. #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
  2767. #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
  2768. #define DMA_ISR_TCIF3_Pos (9U)
  2769. #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
  2770. #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
  2771. #define DMA_ISR_HTIF3_Pos (10U)
  2772. #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
  2773. #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
  2774. #define DMA_ISR_TEIF3_Pos (11U)
  2775. #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
  2776. #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
  2777. #define DMA_ISR_GIF4_Pos (12U)
  2778. #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
  2779. #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
  2780. #define DMA_ISR_TCIF4_Pos (13U)
  2781. #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
  2782. #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
  2783. #define DMA_ISR_HTIF4_Pos (14U)
  2784. #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
  2785. #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
  2786. #define DMA_ISR_TEIF4_Pos (15U)
  2787. #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
  2788. #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
  2789. #define DMA_ISR_GIF5_Pos (16U)
  2790. #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
  2791. #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
  2792. #define DMA_ISR_TCIF5_Pos (17U)
  2793. #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
  2794. #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
  2795. #define DMA_ISR_HTIF5_Pos (18U)
  2796. #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
  2797. #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
  2798. #define DMA_ISR_TEIF5_Pos (19U)
  2799. #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
  2800. #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
  2801. #define DMA_ISR_GIF6_Pos (20U)
  2802. #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
  2803. #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
  2804. #define DMA_ISR_TCIF6_Pos (21U)
  2805. #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
  2806. #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
  2807. #define DMA_ISR_HTIF6_Pos (22U)
  2808. #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
  2809. #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
  2810. #define DMA_ISR_TEIF6_Pos (23U)
  2811. #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
  2812. #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
  2813. #define DMA_ISR_GIF7_Pos (24U)
  2814. #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
  2815. #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
  2816. #define DMA_ISR_TCIF7_Pos (25U)
  2817. #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
  2818. #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
  2819. #define DMA_ISR_HTIF7_Pos (26U)
  2820. #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
  2821. #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
  2822. #define DMA_ISR_TEIF7_Pos (27U)
  2823. #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
  2824. #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
  2825. /******************* Bit definition for DMA_IFCR register *******************/
  2826. #define DMA_IFCR_CGIF1_Pos (0U)
  2827. #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
  2828. #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
  2829. #define DMA_IFCR_CTCIF1_Pos (1U)
  2830. #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
  2831. #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
  2832. #define DMA_IFCR_CHTIF1_Pos (2U)
  2833. #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
  2834. #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
  2835. #define DMA_IFCR_CTEIF1_Pos (3U)
  2836. #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
  2837. #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
  2838. #define DMA_IFCR_CGIF2_Pos (4U)
  2839. #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
  2840. #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
  2841. #define DMA_IFCR_CTCIF2_Pos (5U)
  2842. #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
  2843. #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
  2844. #define DMA_IFCR_CHTIF2_Pos (6U)
  2845. #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
  2846. #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
  2847. #define DMA_IFCR_CTEIF2_Pos (7U)
  2848. #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
  2849. #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
  2850. #define DMA_IFCR_CGIF3_Pos (8U)
  2851. #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
  2852. #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
  2853. #define DMA_IFCR_CTCIF3_Pos (9U)
  2854. #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
  2855. #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
  2856. #define DMA_IFCR_CHTIF3_Pos (10U)
  2857. #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
  2858. #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
  2859. #define DMA_IFCR_CTEIF3_Pos (11U)
  2860. #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
  2861. #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
  2862. #define DMA_IFCR_CGIF4_Pos (12U)
  2863. #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
  2864. #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
  2865. #define DMA_IFCR_CTCIF4_Pos (13U)
  2866. #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
  2867. #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
  2868. #define DMA_IFCR_CHTIF4_Pos (14U)
  2869. #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
  2870. #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
  2871. #define DMA_IFCR_CTEIF4_Pos (15U)
  2872. #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
  2873. #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
  2874. #define DMA_IFCR_CGIF5_Pos (16U)
  2875. #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
  2876. #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
  2877. #define DMA_IFCR_CTCIF5_Pos (17U)
  2878. #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
  2879. #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
  2880. #define DMA_IFCR_CHTIF5_Pos (18U)
  2881. #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
  2882. #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
  2883. #define DMA_IFCR_CTEIF5_Pos (19U)
  2884. #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
  2885. #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
  2886. #define DMA_IFCR_CGIF6_Pos (20U)
  2887. #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
  2888. #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
  2889. #define DMA_IFCR_CTCIF6_Pos (21U)
  2890. #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
  2891. #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
  2892. #define DMA_IFCR_CHTIF6_Pos (22U)
  2893. #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
  2894. #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
  2895. #define DMA_IFCR_CTEIF6_Pos (23U)
  2896. #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
  2897. #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
  2898. #define DMA_IFCR_CGIF7_Pos (24U)
  2899. #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
  2900. #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
  2901. #define DMA_IFCR_CTCIF7_Pos (25U)
  2902. #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
  2903. #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
  2904. #define DMA_IFCR_CHTIF7_Pos (26U)
  2905. #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
  2906. #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
  2907. #define DMA_IFCR_CTEIF7_Pos (27U)
  2908. #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
  2909. #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
  2910. /******************* Bit definition for DMA_CCR register *******************/
  2911. #define DMA_CCR_EN_Pos (0U)
  2912. #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
  2913. #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
  2914. #define DMA_CCR_TCIE_Pos (1U)
  2915. #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
  2916. #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
  2917. #define DMA_CCR_HTIE_Pos (2U)
  2918. #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
  2919. #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
  2920. #define DMA_CCR_TEIE_Pos (3U)
  2921. #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
  2922. #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
  2923. #define DMA_CCR_DIR_Pos (4U)
  2924. #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
  2925. #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
  2926. #define DMA_CCR_CIRC_Pos (5U)
  2927. #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
  2928. #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
  2929. #define DMA_CCR_PINC_Pos (6U)
  2930. #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
  2931. #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
  2932. #define DMA_CCR_MINC_Pos (7U)
  2933. #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
  2934. #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
  2935. #define DMA_CCR_PSIZE_Pos (8U)
  2936. #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
  2937. #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
  2938. #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
  2939. #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
  2940. #define DMA_CCR_MSIZE_Pos (10U)
  2941. #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
  2942. #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
  2943. #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
  2944. #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
  2945. #define DMA_CCR_PL_Pos (12U)
  2946. #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
  2947. #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
  2948. #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
  2949. #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
  2950. #define DMA_CCR_MEM2MEM_Pos (14U)
  2951. #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
  2952. #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
  2953. /****************** Bit definition for DMA_CNDTR register ******************/
  2954. #define DMA_CNDTR_NDT_Pos (0U)
  2955. #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
  2956. #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
  2957. /****************** Bit definition for DMA_CPAR register *******************/
  2958. #define DMA_CPAR_PA_Pos (0U)
  2959. #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
  2960. #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
  2961. /****************** Bit definition for DMA_CMAR register *******************/
  2962. #define DMA_CMAR_MA_Pos (0U)
  2963. #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
  2964. #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
  2965. /******************************************************************************/
  2966. /* */
  2967. /* Analog to Digital Converter (ADC) */
  2968. /* */
  2969. /******************************************************************************/
  2970. /*
  2971. * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
  2972. */
  2973. #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
  2974. /******************** Bit definition for ADC_SR register ********************/
  2975. #define ADC_SR_AWD_Pos (0U)
  2976. #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
  2977. #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
  2978. #define ADC_SR_EOS_Pos (1U)
  2979. #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */
  2980. #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
  2981. #define ADC_SR_JEOS_Pos (2U)
  2982. #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
  2983. #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
  2984. #define ADC_SR_JSTRT_Pos (3U)
  2985. #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
  2986. #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
  2987. #define ADC_SR_STRT_Pos (4U)
  2988. #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
  2989. #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
  2990. /* Legacy defines */
  2991. #define ADC_SR_EOC (ADC_SR_EOS)
  2992. #define ADC_SR_JEOC (ADC_SR_JEOS)
  2993. /******************* Bit definition for ADC_CR1 register ********************/
  2994. #define ADC_CR1_AWDCH_Pos (0U)
  2995. #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
  2996. #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
  2997. #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
  2998. #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
  2999. #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
  3000. #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
  3001. #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
  3002. #define ADC_CR1_EOSIE_Pos (5U)
  3003. #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
  3004. #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
  3005. #define ADC_CR1_AWDIE_Pos (6U)
  3006. #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
  3007. #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
  3008. #define ADC_CR1_JEOSIE_Pos (7U)
  3009. #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
  3010. #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
  3011. #define ADC_CR1_SCAN_Pos (8U)
  3012. #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
  3013. #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
  3014. #define ADC_CR1_AWDSGL_Pos (9U)
  3015. #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
  3016. #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
  3017. #define ADC_CR1_JAUTO_Pos (10U)
  3018. #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
  3019. #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
  3020. #define ADC_CR1_DISCEN_Pos (11U)
  3021. #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
  3022. #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
  3023. #define ADC_CR1_JDISCEN_Pos (12U)
  3024. #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
  3025. #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
  3026. #define ADC_CR1_DISCNUM_Pos (13U)
  3027. #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
  3028. #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
  3029. #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
  3030. #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
  3031. #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
  3032. #define ADC_CR1_DUALMOD_Pos (16U)
  3033. #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
  3034. #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
  3035. #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
  3036. #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
  3037. #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
  3038. #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
  3039. #define ADC_CR1_JAWDEN_Pos (22U)
  3040. #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
  3041. #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
  3042. #define ADC_CR1_AWDEN_Pos (23U)
  3043. #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
  3044. #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
  3045. /* Legacy defines */
  3046. #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
  3047. #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
  3048. /******************* Bit definition for ADC_CR2 register ********************/
  3049. #define ADC_CR2_ADON_Pos (0U)
  3050. #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
  3051. #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
  3052. #define ADC_CR2_CONT_Pos (1U)
  3053. #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
  3054. #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
  3055. #define ADC_CR2_CAL_Pos (2U)
  3056. #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
  3057. #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
  3058. #define ADC_CR2_RSTCAL_Pos (3U)
  3059. #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
  3060. #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
  3061. #define ADC_CR2_DMA_Pos (8U)
  3062. #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
  3063. #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
  3064. #define ADC_CR2_ALIGN_Pos (11U)
  3065. #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
  3066. #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
  3067. #define ADC_CR2_JEXTSEL_Pos (12U)
  3068. #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
  3069. #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
  3070. #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
  3071. #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
  3072. #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
  3073. #define ADC_CR2_JEXTTRIG_Pos (15U)
  3074. #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
  3075. #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
  3076. #define ADC_CR2_EXTSEL_Pos (17U)
  3077. #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
  3078. #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
  3079. #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
  3080. #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
  3081. #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
  3082. #define ADC_CR2_EXTTRIG_Pos (20U)
  3083. #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
  3084. #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
  3085. #define ADC_CR2_JSWSTART_Pos (21U)
  3086. #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
  3087. #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
  3088. #define ADC_CR2_SWSTART_Pos (22U)
  3089. #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
  3090. #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
  3091. #define ADC_CR2_TSVREFE_Pos (23U)
  3092. #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
  3093. #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
  3094. /****************** Bit definition for ADC_SMPR1 register *******************/
  3095. #define ADC_SMPR1_SMP10_Pos (0U)
  3096. #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
  3097. #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
  3098. #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
  3099. #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
  3100. #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
  3101. #define ADC_SMPR1_SMP11_Pos (3U)
  3102. #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
  3103. #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
  3104. #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
  3105. #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
  3106. #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
  3107. #define ADC_SMPR1_SMP12_Pos (6U)
  3108. #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
  3109. #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
  3110. #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
  3111. #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
  3112. #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
  3113. #define ADC_SMPR1_SMP13_Pos (9U)
  3114. #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
  3115. #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
  3116. #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
  3117. #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
  3118. #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
  3119. #define ADC_SMPR1_SMP14_Pos (12U)
  3120. #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
  3121. #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
  3122. #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
  3123. #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
  3124. #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
  3125. #define ADC_SMPR1_SMP15_Pos (15U)
  3126. #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
  3127. #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
  3128. #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
  3129. #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
  3130. #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
  3131. #define ADC_SMPR1_SMP16_Pos (18U)
  3132. #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
  3133. #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
  3134. #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
  3135. #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
  3136. #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
  3137. #define ADC_SMPR1_SMP17_Pos (21U)
  3138. #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
  3139. #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
  3140. #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
  3141. #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
  3142. #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
  3143. /****************** Bit definition for ADC_SMPR2 register *******************/
  3144. #define ADC_SMPR2_SMP0_Pos (0U)
  3145. #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
  3146. #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
  3147. #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
  3148. #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
  3149. #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
  3150. #define ADC_SMPR2_SMP1_Pos (3U)
  3151. #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
  3152. #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
  3153. #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
  3154. #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
  3155. #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
  3156. #define ADC_SMPR2_SMP2_Pos (6U)
  3157. #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
  3158. #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
  3159. #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
  3160. #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
  3161. #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
  3162. #define ADC_SMPR2_SMP3_Pos (9U)
  3163. #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
  3164. #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
  3165. #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
  3166. #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
  3167. #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
  3168. #define ADC_SMPR2_SMP4_Pos (12U)
  3169. #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
  3170. #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
  3171. #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
  3172. #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
  3173. #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
  3174. #define ADC_SMPR2_SMP5_Pos (15U)
  3175. #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
  3176. #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
  3177. #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
  3178. #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
  3179. #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
  3180. #define ADC_SMPR2_SMP6_Pos (18U)
  3181. #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
  3182. #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
  3183. #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
  3184. #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
  3185. #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
  3186. #define ADC_SMPR2_SMP7_Pos (21U)
  3187. #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
  3188. #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
  3189. #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
  3190. #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
  3191. #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
  3192. #define ADC_SMPR2_SMP8_Pos (24U)
  3193. #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
  3194. #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
  3195. #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
  3196. #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
  3197. #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
  3198. #define ADC_SMPR2_SMP9_Pos (27U)
  3199. #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
  3200. #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
  3201. #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
  3202. #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
  3203. #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
  3204. /****************** Bit definition for ADC_JOFR1 register *******************/
  3205. #define ADC_JOFR1_JOFFSET1_Pos (0U)
  3206. #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
  3207. #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
  3208. /****************** Bit definition for ADC_JOFR2 register *******************/
  3209. #define ADC_JOFR2_JOFFSET2_Pos (0U)
  3210. #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
  3211. #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
  3212. /****************** Bit definition for ADC_JOFR3 register *******************/
  3213. #define ADC_JOFR3_JOFFSET3_Pos (0U)
  3214. #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
  3215. #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
  3216. /****************** Bit definition for ADC_JOFR4 register *******************/
  3217. #define ADC_JOFR4_JOFFSET4_Pos (0U)
  3218. #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
  3219. #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
  3220. /******************* Bit definition for ADC_HTR register ********************/
  3221. #define ADC_HTR_HT_Pos (0U)
  3222. #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
  3223. #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
  3224. /******************* Bit definition for ADC_LTR register ********************/
  3225. #define ADC_LTR_LT_Pos (0U)
  3226. #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
  3227. #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
  3228. /******************* Bit definition for ADC_SQR1 register *******************/
  3229. #define ADC_SQR1_SQ13_Pos (0U)
  3230. #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
  3231. #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
  3232. #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
  3233. #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
  3234. #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
  3235. #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
  3236. #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
  3237. #define ADC_SQR1_SQ14_Pos (5U)
  3238. #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
  3239. #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
  3240. #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
  3241. #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
  3242. #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
  3243. #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
  3244. #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
  3245. #define ADC_SQR1_SQ15_Pos (10U)
  3246. #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
  3247. #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
  3248. #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
  3249. #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
  3250. #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
  3251. #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
  3252. #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
  3253. #define ADC_SQR1_SQ16_Pos (15U)
  3254. #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
  3255. #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
  3256. #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
  3257. #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
  3258. #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
  3259. #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
  3260. #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
  3261. #define ADC_SQR1_L_Pos (20U)
  3262. #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
  3263. #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
  3264. #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
  3265. #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
  3266. #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
  3267. #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
  3268. /******************* Bit definition for ADC_SQR2 register *******************/
  3269. #define ADC_SQR2_SQ7_Pos (0U)
  3270. #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
  3271. #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
  3272. #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
  3273. #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
  3274. #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
  3275. #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
  3276. #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
  3277. #define ADC_SQR2_SQ8_Pos (5U)
  3278. #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
  3279. #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
  3280. #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
  3281. #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
  3282. #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
  3283. #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
  3284. #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
  3285. #define ADC_SQR2_SQ9_Pos (10U)
  3286. #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
  3287. #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
  3288. #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
  3289. #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
  3290. #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
  3291. #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
  3292. #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
  3293. #define ADC_SQR2_SQ10_Pos (15U)
  3294. #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
  3295. #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
  3296. #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
  3297. #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
  3298. #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
  3299. #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
  3300. #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
  3301. #define ADC_SQR2_SQ11_Pos (20U)
  3302. #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
  3303. #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
  3304. #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
  3305. #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
  3306. #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
  3307. #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
  3308. #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
  3309. #define ADC_SQR2_SQ12_Pos (25U)
  3310. #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
  3311. #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
  3312. #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
  3313. #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
  3314. #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
  3315. #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
  3316. #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
  3317. /******************* Bit definition for ADC_SQR3 register *******************/
  3318. #define ADC_SQR3_SQ1_Pos (0U)
  3319. #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
  3320. #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
  3321. #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
  3322. #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
  3323. #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
  3324. #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
  3325. #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
  3326. #define ADC_SQR3_SQ2_Pos (5U)
  3327. #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
  3328. #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
  3329. #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
  3330. #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
  3331. #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
  3332. #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
  3333. #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
  3334. #define ADC_SQR3_SQ3_Pos (10U)
  3335. #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
  3336. #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
  3337. #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
  3338. #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
  3339. #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
  3340. #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
  3341. #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
  3342. #define ADC_SQR3_SQ4_Pos (15U)
  3343. #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
  3344. #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
  3345. #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
  3346. #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
  3347. #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
  3348. #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
  3349. #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
  3350. #define ADC_SQR3_SQ5_Pos (20U)
  3351. #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
  3352. #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
  3353. #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
  3354. #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
  3355. #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
  3356. #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
  3357. #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
  3358. #define ADC_SQR3_SQ6_Pos (25U)
  3359. #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
  3360. #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
  3361. #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
  3362. #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
  3363. #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
  3364. #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
  3365. #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
  3366. /******************* Bit definition for ADC_JSQR register *******************/
  3367. #define ADC_JSQR_JSQ1_Pos (0U)
  3368. #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
  3369. #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
  3370. #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
  3371. #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
  3372. #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
  3373. #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
  3374. #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
  3375. #define ADC_JSQR_JSQ2_Pos (5U)
  3376. #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
  3377. #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
  3378. #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
  3379. #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
  3380. #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
  3381. #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
  3382. #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
  3383. #define ADC_JSQR_JSQ3_Pos (10U)
  3384. #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
  3385. #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
  3386. #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
  3387. #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
  3388. #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
  3389. #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
  3390. #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
  3391. #define ADC_JSQR_JSQ4_Pos (15U)
  3392. #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
  3393. #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
  3394. #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
  3395. #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
  3396. #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
  3397. #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
  3398. #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
  3399. #define ADC_JSQR_JL_Pos (20U)
  3400. #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
  3401. #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
  3402. #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
  3403. #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
  3404. /******************* Bit definition for ADC_JDR1 register *******************/
  3405. #define ADC_JDR1_JDATA_Pos (0U)
  3406. #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
  3407. #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
  3408. /******************* Bit definition for ADC_JDR2 register *******************/
  3409. #define ADC_JDR2_JDATA_Pos (0U)
  3410. #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
  3411. #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
  3412. /******************* Bit definition for ADC_JDR3 register *******************/
  3413. #define ADC_JDR3_JDATA_Pos (0U)
  3414. #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
  3415. #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
  3416. /******************* Bit definition for ADC_JDR4 register *******************/
  3417. #define ADC_JDR4_JDATA_Pos (0U)
  3418. #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
  3419. #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
  3420. /******************** Bit definition for ADC_DR register ********************/
  3421. #define ADC_DR_DATA_Pos (0U)
  3422. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  3423. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
  3424. #define ADC_DR_ADC2DATA_Pos (16U)
  3425. #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
  3426. #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
  3427. /*****************************************************************************/
  3428. /* */
  3429. /* Timers (TIM) */
  3430. /* */
  3431. /*****************************************************************************/
  3432. /******************* Bit definition for TIM_CR1 register *******************/
  3433. #define TIM_CR1_CEN_Pos (0U)
  3434. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  3435. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  3436. #define TIM_CR1_UDIS_Pos (1U)
  3437. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  3438. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  3439. #define TIM_CR1_URS_Pos (2U)
  3440. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  3441. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  3442. #define TIM_CR1_OPM_Pos (3U)
  3443. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  3444. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  3445. #define TIM_CR1_DIR_Pos (4U)
  3446. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  3447. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  3448. #define TIM_CR1_CMS_Pos (5U)
  3449. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  3450. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  3451. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
  3452. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
  3453. #define TIM_CR1_ARPE_Pos (7U)
  3454. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  3455. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  3456. #define TIM_CR1_CKD_Pos (8U)
  3457. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  3458. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  3459. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
  3460. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
  3461. /******************* Bit definition for TIM_CR2 register *******************/
  3462. #define TIM_CR2_CCPC_Pos (0U)
  3463. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  3464. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  3465. #define TIM_CR2_CCUS_Pos (2U)
  3466. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  3467. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  3468. #define TIM_CR2_CCDS_Pos (3U)
  3469. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  3470. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  3471. #define TIM_CR2_MMS_Pos (4U)
  3472. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  3473. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  3474. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
  3475. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
  3476. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
  3477. #define TIM_CR2_TI1S_Pos (7U)
  3478. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  3479. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  3480. #define TIM_CR2_OIS1_Pos (8U)
  3481. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  3482. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  3483. #define TIM_CR2_OIS1N_Pos (9U)
  3484. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  3485. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  3486. #define TIM_CR2_OIS2_Pos (10U)
  3487. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  3488. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  3489. #define TIM_CR2_OIS2N_Pos (11U)
  3490. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  3491. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  3492. #define TIM_CR2_OIS3_Pos (12U)
  3493. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  3494. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  3495. #define TIM_CR2_OIS3N_Pos (13U)
  3496. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  3497. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  3498. #define TIM_CR2_OIS4_Pos (14U)
  3499. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  3500. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  3501. /******************* Bit definition for TIM_SMCR register ******************/
  3502. #define TIM_SMCR_SMS_Pos (0U)
  3503. #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
  3504. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  3505. #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
  3506. #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
  3507. #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
  3508. #define TIM_SMCR_TS_Pos (4U)
  3509. #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
  3510. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  3511. #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
  3512. #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
  3513. #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
  3514. #define TIM_SMCR_MSM_Pos (7U)
  3515. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  3516. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  3517. #define TIM_SMCR_ETF_Pos (8U)
  3518. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  3519. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  3520. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
  3521. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
  3522. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
  3523. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
  3524. #define TIM_SMCR_ETPS_Pos (12U)
  3525. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  3526. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  3527. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
  3528. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
  3529. #define TIM_SMCR_ECE_Pos (14U)
  3530. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  3531. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  3532. #define TIM_SMCR_ETP_Pos (15U)
  3533. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  3534. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  3535. /******************* Bit definition for TIM_DIER register ******************/
  3536. #define TIM_DIER_UIE_Pos (0U)
  3537. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  3538. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  3539. #define TIM_DIER_CC1IE_Pos (1U)
  3540. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  3541. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  3542. #define TIM_DIER_CC2IE_Pos (2U)
  3543. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  3544. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  3545. #define TIM_DIER_CC3IE_Pos (3U)
  3546. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  3547. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  3548. #define TIM_DIER_CC4IE_Pos (4U)
  3549. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  3550. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  3551. #define TIM_DIER_COMIE_Pos (5U)
  3552. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  3553. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  3554. #define TIM_DIER_TIE_Pos (6U)
  3555. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  3556. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  3557. #define TIM_DIER_BIE_Pos (7U)
  3558. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  3559. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  3560. #define TIM_DIER_UDE_Pos (8U)
  3561. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  3562. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  3563. #define TIM_DIER_CC1DE_Pos (9U)
  3564. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  3565. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  3566. #define TIM_DIER_CC2DE_Pos (10U)
  3567. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  3568. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  3569. #define TIM_DIER_CC3DE_Pos (11U)
  3570. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  3571. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  3572. #define TIM_DIER_CC4DE_Pos (12U)
  3573. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  3574. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  3575. #define TIM_DIER_COMDE_Pos (13U)
  3576. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  3577. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  3578. #define TIM_DIER_TDE_Pos (14U)
  3579. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  3580. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  3581. /******************** Bit definition for TIM_SR register *******************/
  3582. #define TIM_SR_UIF_Pos (0U)
  3583. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  3584. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  3585. #define TIM_SR_CC1IF_Pos (1U)
  3586. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  3587. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  3588. #define TIM_SR_CC2IF_Pos (2U)
  3589. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  3590. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  3591. #define TIM_SR_CC3IF_Pos (3U)
  3592. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  3593. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  3594. #define TIM_SR_CC4IF_Pos (4U)
  3595. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  3596. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  3597. #define TIM_SR_COMIF_Pos (5U)
  3598. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  3599. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  3600. #define TIM_SR_TIF_Pos (6U)
  3601. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  3602. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  3603. #define TIM_SR_BIF_Pos (7U)
  3604. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  3605. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  3606. #define TIM_SR_CC1OF_Pos (9U)
  3607. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  3608. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  3609. #define TIM_SR_CC2OF_Pos (10U)
  3610. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  3611. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  3612. #define TIM_SR_CC3OF_Pos (11U)
  3613. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  3614. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  3615. #define TIM_SR_CC4OF_Pos (12U)
  3616. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  3617. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  3618. /******************* Bit definition for TIM_EGR register *******************/
  3619. #define TIM_EGR_UG_Pos (0U)
  3620. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  3621. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  3622. #define TIM_EGR_CC1G_Pos (1U)
  3623. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  3624. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  3625. #define TIM_EGR_CC2G_Pos (2U)
  3626. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  3627. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  3628. #define TIM_EGR_CC3G_Pos (3U)
  3629. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  3630. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  3631. #define TIM_EGR_CC4G_Pos (4U)
  3632. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  3633. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  3634. #define TIM_EGR_COMG_Pos (5U)
  3635. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  3636. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  3637. #define TIM_EGR_TG_Pos (6U)
  3638. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  3639. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  3640. #define TIM_EGR_BG_Pos (7U)
  3641. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  3642. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  3643. /****************** Bit definition for TIM_CCMR1 register ******************/
  3644. #define TIM_CCMR1_CC1S_Pos (0U)
  3645. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  3646. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  3647. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
  3648. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
  3649. #define TIM_CCMR1_OC1FE_Pos (2U)
  3650. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  3651. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  3652. #define TIM_CCMR1_OC1PE_Pos (3U)
  3653. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  3654. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  3655. #define TIM_CCMR1_OC1M_Pos (4U)
  3656. #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
  3657. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  3658. #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
  3659. #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
  3660. #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
  3661. #define TIM_CCMR1_OC1CE_Pos (7U)
  3662. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  3663. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
  3664. #define TIM_CCMR1_CC2S_Pos (8U)
  3665. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  3666. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  3667. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
  3668. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
  3669. #define TIM_CCMR1_OC2FE_Pos (10U)
  3670. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  3671. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  3672. #define TIM_CCMR1_OC2PE_Pos (11U)
  3673. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  3674. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  3675. #define TIM_CCMR1_OC2M_Pos (12U)
  3676. #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
  3677. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  3678. #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
  3679. #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
  3680. #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
  3681. #define TIM_CCMR1_OC2CE_Pos (15U)
  3682. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  3683. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  3684. /*---------------------------------------------------------------------------*/
  3685. #define TIM_CCMR1_IC1PSC_Pos (2U)
  3686. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  3687. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  3688. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
  3689. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
  3690. #define TIM_CCMR1_IC1F_Pos (4U)
  3691. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  3692. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  3693. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
  3694. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
  3695. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
  3696. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
  3697. #define TIM_CCMR1_IC2PSC_Pos (10U)
  3698. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  3699. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  3700. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
  3701. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
  3702. #define TIM_CCMR1_IC2F_Pos (12U)
  3703. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  3704. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  3705. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
  3706. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
  3707. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
  3708. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
  3709. /****************** Bit definition for TIM_CCMR2 register ******************/
  3710. #define TIM_CCMR2_CC3S_Pos (0U)
  3711. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  3712. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  3713. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
  3714. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
  3715. #define TIM_CCMR2_OC3FE_Pos (2U)
  3716. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  3717. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  3718. #define TIM_CCMR2_OC3PE_Pos (3U)
  3719. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  3720. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  3721. #define TIM_CCMR2_OC3M_Pos (4U)
  3722. #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
  3723. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  3724. #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
  3725. #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
  3726. #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
  3727. #define TIM_CCMR2_OC3CE_Pos (7U)
  3728. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  3729. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  3730. #define TIM_CCMR2_CC4S_Pos (8U)
  3731. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  3732. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  3733. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
  3734. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
  3735. #define TIM_CCMR2_OC4FE_Pos (10U)
  3736. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  3737. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  3738. #define TIM_CCMR2_OC4PE_Pos (11U)
  3739. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  3740. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  3741. #define TIM_CCMR2_OC4M_Pos (12U)
  3742. #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
  3743. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  3744. #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
  3745. #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
  3746. #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
  3747. #define TIM_CCMR2_OC4CE_Pos (15U)
  3748. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  3749. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  3750. /*---------------------------------------------------------------------------*/
  3751. #define TIM_CCMR2_IC3PSC_Pos (2U)
  3752. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  3753. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  3754. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
  3755. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
  3756. #define TIM_CCMR2_IC3F_Pos (4U)
  3757. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  3758. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  3759. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
  3760. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
  3761. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
  3762. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
  3763. #define TIM_CCMR2_IC4PSC_Pos (10U)
  3764. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  3765. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  3766. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
  3767. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
  3768. #define TIM_CCMR2_IC4F_Pos (12U)
  3769. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  3770. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  3771. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
  3772. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
  3773. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
  3774. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
  3775. /******************* Bit definition for TIM_CCER register ******************/
  3776. #define TIM_CCER_CC1E_Pos (0U)
  3777. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  3778. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  3779. #define TIM_CCER_CC1P_Pos (1U)
  3780. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  3781. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  3782. #define TIM_CCER_CC1NE_Pos (2U)
  3783. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  3784. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  3785. #define TIM_CCER_CC1NP_Pos (3U)
  3786. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  3787. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  3788. #define TIM_CCER_CC2E_Pos (4U)
  3789. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  3790. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  3791. #define TIM_CCER_CC2P_Pos (5U)
  3792. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  3793. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  3794. #define TIM_CCER_CC2NE_Pos (6U)
  3795. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  3796. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  3797. #define TIM_CCER_CC2NP_Pos (7U)
  3798. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  3799. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  3800. #define TIM_CCER_CC3E_Pos (8U)
  3801. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  3802. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  3803. #define TIM_CCER_CC3P_Pos (9U)
  3804. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  3805. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  3806. #define TIM_CCER_CC3NE_Pos (10U)
  3807. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  3808. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  3809. #define TIM_CCER_CC3NP_Pos (11U)
  3810. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  3811. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  3812. #define TIM_CCER_CC4E_Pos (12U)
  3813. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  3814. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  3815. #define TIM_CCER_CC4P_Pos (13U)
  3816. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  3817. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  3818. /******************* Bit definition for TIM_CNT register *******************/
  3819. #define TIM_CNT_CNT_Pos (0U)
  3820. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  3821. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  3822. /******************* Bit definition for TIM_PSC register *******************/
  3823. #define TIM_PSC_PSC_Pos (0U)
  3824. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  3825. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  3826. /******************* Bit definition for TIM_ARR register *******************/
  3827. #define TIM_ARR_ARR_Pos (0U)
  3828. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  3829. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
  3830. /******************* Bit definition for TIM_RCR register *******************/
  3831. #define TIM_RCR_REP_Pos (0U)
  3832. #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
  3833. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  3834. /******************* Bit definition for TIM_CCR1 register ******************/
  3835. #define TIM_CCR1_CCR1_Pos (0U)
  3836. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  3837. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  3838. /******************* Bit definition for TIM_CCR2 register ******************/
  3839. #define TIM_CCR2_CCR2_Pos (0U)
  3840. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  3841. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  3842. /******************* Bit definition for TIM_CCR3 register ******************/
  3843. #define TIM_CCR3_CCR3_Pos (0U)
  3844. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  3845. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  3846. /******************* Bit definition for TIM_CCR4 register ******************/
  3847. #define TIM_CCR4_CCR4_Pos (0U)
  3848. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  3849. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  3850. /******************* Bit definition for TIM_BDTR register ******************/
  3851. #define TIM_BDTR_DTG_Pos (0U)
  3852. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  3853. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  3854. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
  3855. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
  3856. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
  3857. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
  3858. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
  3859. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
  3860. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
  3861. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
  3862. #define TIM_BDTR_LOCK_Pos (8U)
  3863. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  3864. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  3865. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
  3866. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
  3867. #define TIM_BDTR_OSSI_Pos (10U)
  3868. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  3869. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  3870. #define TIM_BDTR_OSSR_Pos (11U)
  3871. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  3872. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  3873. #define TIM_BDTR_BKE_Pos (12U)
  3874. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  3875. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
  3876. #define TIM_BDTR_BKP_Pos (13U)
  3877. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  3878. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
  3879. #define TIM_BDTR_AOE_Pos (14U)
  3880. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  3881. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  3882. #define TIM_BDTR_MOE_Pos (15U)
  3883. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  3884. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  3885. /******************* Bit definition for TIM_DCR register *******************/
  3886. #define TIM_DCR_DBA_Pos (0U)
  3887. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  3888. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  3889. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
  3890. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
  3891. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
  3892. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
  3893. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
  3894. #define TIM_DCR_DBL_Pos (8U)
  3895. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  3896. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  3897. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
  3898. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
  3899. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
  3900. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
  3901. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
  3902. /******************* Bit definition for TIM_DMAR register ******************/
  3903. #define TIM_DMAR_DMAB_Pos (0U)
  3904. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  3905. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  3906. /******************************************************************************/
  3907. /* */
  3908. /* Real-Time Clock */
  3909. /* */
  3910. /******************************************************************************/
  3911. /******************* Bit definition for RTC_CRH register ********************/
  3912. #define RTC_CRH_SECIE_Pos (0U)
  3913. #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
  3914. #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
  3915. #define RTC_CRH_ALRIE_Pos (1U)
  3916. #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
  3917. #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
  3918. #define RTC_CRH_OWIE_Pos (2U)
  3919. #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
  3920. #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
  3921. /******************* Bit definition for RTC_CRL register ********************/
  3922. #define RTC_CRL_SECF_Pos (0U)
  3923. #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
  3924. #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
  3925. #define RTC_CRL_ALRF_Pos (1U)
  3926. #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
  3927. #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
  3928. #define RTC_CRL_OWF_Pos (2U)
  3929. #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
  3930. #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
  3931. #define RTC_CRL_RSF_Pos (3U)
  3932. #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
  3933. #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
  3934. #define RTC_CRL_CNF_Pos (4U)
  3935. #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
  3936. #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
  3937. #define RTC_CRL_RTOFF_Pos (5U)
  3938. #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
  3939. #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
  3940. /******************* Bit definition for RTC_PRLH register *******************/
  3941. #define RTC_PRLH_PRL_Pos (0U)
  3942. #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
  3943. #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
  3944. /******************* Bit definition for RTC_PRLL register *******************/
  3945. #define RTC_PRLL_PRL_Pos (0U)
  3946. #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
  3947. #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
  3948. /******************* Bit definition for RTC_DIVH register *******************/
  3949. #define RTC_DIVH_RTC_DIV_Pos (0U)
  3950. #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
  3951. #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
  3952. /******************* Bit definition for RTC_DIVL register *******************/
  3953. #define RTC_DIVL_RTC_DIV_Pos (0U)
  3954. #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
  3955. #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
  3956. /******************* Bit definition for RTC_CNTH register *******************/
  3957. #define RTC_CNTH_RTC_CNT_Pos (0U)
  3958. #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
  3959. #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
  3960. /******************* Bit definition for RTC_CNTL register *******************/
  3961. #define RTC_CNTL_RTC_CNT_Pos (0U)
  3962. #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
  3963. #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
  3964. /******************* Bit definition for RTC_ALRH register *******************/
  3965. #define RTC_ALRH_RTC_ALR_Pos (0U)
  3966. #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
  3967. #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
  3968. /******************* Bit definition for RTC_ALRL register *******************/
  3969. #define RTC_ALRL_RTC_ALR_Pos (0U)
  3970. #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
  3971. #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
  3972. /******************************************************************************/
  3973. /* */
  3974. /* Independent WATCHDOG (IWDG) */
  3975. /* */
  3976. /******************************************************************************/
  3977. /******************* Bit definition for IWDG_KR register ********************/
  3978. #define IWDG_KR_KEY_Pos (0U)
  3979. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  3980. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
  3981. /******************* Bit definition for IWDG_PR register ********************/
  3982. #define IWDG_PR_PR_Pos (0U)
  3983. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  3984. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
  3985. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
  3986. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
  3987. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
  3988. /******************* Bit definition for IWDG_RLR register *******************/
  3989. #define IWDG_RLR_RL_Pos (0U)
  3990. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  3991. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
  3992. /******************* Bit definition for IWDG_SR register ********************/
  3993. #define IWDG_SR_PVU_Pos (0U)
  3994. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  3995. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
  3996. #define IWDG_SR_RVU_Pos (1U)
  3997. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  3998. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
  3999. /******************************************************************************/
  4000. /* */
  4001. /* Window WATCHDOG (WWDG) */
  4002. /* */
  4003. /******************************************************************************/
  4004. /******************* Bit definition for WWDG_CR register ********************/
  4005. #define WWDG_CR_T_Pos (0U)
  4006. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  4007. #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
  4008. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
  4009. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
  4010. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
  4011. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
  4012. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
  4013. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
  4014. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
  4015. /* Legacy defines */
  4016. #define WWDG_CR_T0 WWDG_CR_T_0
  4017. #define WWDG_CR_T1 WWDG_CR_T_1
  4018. #define WWDG_CR_T2 WWDG_CR_T_2
  4019. #define WWDG_CR_T3 WWDG_CR_T_3
  4020. #define WWDG_CR_T4 WWDG_CR_T_4
  4021. #define WWDG_CR_T5 WWDG_CR_T_5
  4022. #define WWDG_CR_T6 WWDG_CR_T_6
  4023. #define WWDG_CR_WDGA_Pos (7U)
  4024. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  4025. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
  4026. /******************* Bit definition for WWDG_CFR register *******************/
  4027. #define WWDG_CFR_W_Pos (0U)
  4028. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  4029. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
  4030. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
  4031. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
  4032. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
  4033. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
  4034. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
  4035. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
  4036. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
  4037. /* Legacy defines */
  4038. #define WWDG_CFR_W0 WWDG_CFR_W_0
  4039. #define WWDG_CFR_W1 WWDG_CFR_W_1
  4040. #define WWDG_CFR_W2 WWDG_CFR_W_2
  4041. #define WWDG_CFR_W3 WWDG_CFR_W_3
  4042. #define WWDG_CFR_W4 WWDG_CFR_W_4
  4043. #define WWDG_CFR_W5 WWDG_CFR_W_5
  4044. #define WWDG_CFR_W6 WWDG_CFR_W_6
  4045. #define WWDG_CFR_WDGTB_Pos (7U)
  4046. #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
  4047. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
  4048. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
  4049. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
  4050. /* Legacy defines */
  4051. #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
  4052. #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
  4053. #define WWDG_CFR_EWI_Pos (9U)
  4054. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  4055. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
  4056. /******************* Bit definition for WWDG_SR register ********************/
  4057. #define WWDG_SR_EWIF_Pos (0U)
  4058. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  4059. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
  4060. /******************************************************************************/
  4061. /* */
  4062. /* USB Device FS */
  4063. /* */
  4064. /******************************************************************************/
  4065. /*!< Endpoint-specific registers */
  4066. #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
  4067. #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
  4068. #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
  4069. #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
  4070. #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
  4071. #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
  4072. #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
  4073. #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
  4074. /* bit positions */
  4075. #define USB_EP_CTR_RX_Pos (15U)
  4076. #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
  4077. #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
  4078. #define USB_EP_DTOG_RX_Pos (14U)
  4079. #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
  4080. #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
  4081. #define USB_EPRX_STAT_Pos (12U)
  4082. #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
  4083. #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
  4084. #define USB_EP_SETUP_Pos (11U)
  4085. #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */
  4086. #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
  4087. #define USB_EP_T_FIELD_Pos (9U)
  4088. #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
  4089. #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
  4090. #define USB_EP_KIND_Pos (8U)
  4091. #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */
  4092. #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
  4093. #define USB_EP_CTR_TX_Pos (7U)
  4094. #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
  4095. #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
  4096. #define USB_EP_DTOG_TX_Pos (6U)
  4097. #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
  4098. #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
  4099. #define USB_EPTX_STAT_Pos (4U)
  4100. #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
  4101. #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
  4102. #define USB_EPADDR_FIELD_Pos (0U)
  4103. #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
  4104. #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
  4105. /* EndPoint REGister MASK (no toggle fields) */
  4106. #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
  4107. /*!< EP_TYPE[1:0] EndPoint TYPE */
  4108. #define USB_EP_TYPE_MASK_Pos (9U)
  4109. #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
  4110. #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
  4111. #define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
  4112. #define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
  4113. #define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
  4114. #define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
  4115. #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
  4116. #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
  4117. /*!< STAT_TX[1:0] STATus for TX transfer */
  4118. #define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
  4119. #define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
  4120. #define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
  4121. #define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
  4122. #define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
  4123. #define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
  4124. #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
  4125. /*!< STAT_RX[1:0] STATus for RX transfer */
  4126. #define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
  4127. #define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
  4128. #define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
  4129. #define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
  4130. #define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
  4131. #define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
  4132. #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
  4133. /******************* Bit definition for USB_EP0R register *******************/
  4134. #define USB_EP0R_EA_Pos (0U)
  4135. #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */
  4136. #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
  4137. #define USB_EP0R_STAT_TX_Pos (4U)
  4138. #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
  4139. #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4140. #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
  4141. #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
  4142. #define USB_EP0R_DTOG_TX_Pos (6U)
  4143. #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
  4144. #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4145. #define USB_EP0R_CTR_TX_Pos (7U)
  4146. #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
  4147. #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4148. #define USB_EP0R_EP_KIND_Pos (8U)
  4149. #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
  4150. #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
  4151. #define USB_EP0R_EP_TYPE_Pos (9U)
  4152. #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
  4153. #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4154. #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
  4155. #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
  4156. #define USB_EP0R_SETUP_Pos (11U)
  4157. #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
  4158. #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
  4159. #define USB_EP0R_STAT_RX_Pos (12U)
  4160. #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
  4161. #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4162. #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
  4163. #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
  4164. #define USB_EP0R_DTOG_RX_Pos (14U)
  4165. #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
  4166. #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4167. #define USB_EP0R_CTR_RX_Pos (15U)
  4168. #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
  4169. #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4170. /******************* Bit definition for USB_EP1R register *******************/
  4171. #define USB_EP1R_EA_Pos (0U)
  4172. #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */
  4173. #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
  4174. #define USB_EP1R_STAT_TX_Pos (4U)
  4175. #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
  4176. #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4177. #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
  4178. #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
  4179. #define USB_EP1R_DTOG_TX_Pos (6U)
  4180. #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
  4181. #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4182. #define USB_EP1R_CTR_TX_Pos (7U)
  4183. #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
  4184. #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4185. #define USB_EP1R_EP_KIND_Pos (8U)
  4186. #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
  4187. #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
  4188. #define USB_EP1R_EP_TYPE_Pos (9U)
  4189. #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
  4190. #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4191. #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
  4192. #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
  4193. #define USB_EP1R_SETUP_Pos (11U)
  4194. #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
  4195. #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
  4196. #define USB_EP1R_STAT_RX_Pos (12U)
  4197. #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
  4198. #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4199. #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
  4200. #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
  4201. #define USB_EP1R_DTOG_RX_Pos (14U)
  4202. #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
  4203. #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4204. #define USB_EP1R_CTR_RX_Pos (15U)
  4205. #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
  4206. #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4207. /******************* Bit definition for USB_EP2R register *******************/
  4208. #define USB_EP2R_EA_Pos (0U)
  4209. #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */
  4210. #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
  4211. #define USB_EP2R_STAT_TX_Pos (4U)
  4212. #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
  4213. #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4214. #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
  4215. #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
  4216. #define USB_EP2R_DTOG_TX_Pos (6U)
  4217. #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
  4218. #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4219. #define USB_EP2R_CTR_TX_Pos (7U)
  4220. #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
  4221. #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4222. #define USB_EP2R_EP_KIND_Pos (8U)
  4223. #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
  4224. #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
  4225. #define USB_EP2R_EP_TYPE_Pos (9U)
  4226. #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
  4227. #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4228. #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
  4229. #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
  4230. #define USB_EP2R_SETUP_Pos (11U)
  4231. #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
  4232. #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
  4233. #define USB_EP2R_STAT_RX_Pos (12U)
  4234. #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
  4235. #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4236. #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
  4237. #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
  4238. #define USB_EP2R_DTOG_RX_Pos (14U)
  4239. #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
  4240. #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4241. #define USB_EP2R_CTR_RX_Pos (15U)
  4242. #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
  4243. #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4244. /******************* Bit definition for USB_EP3R register *******************/
  4245. #define USB_EP3R_EA_Pos (0U)
  4246. #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */
  4247. #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
  4248. #define USB_EP3R_STAT_TX_Pos (4U)
  4249. #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
  4250. #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4251. #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
  4252. #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
  4253. #define USB_EP3R_DTOG_TX_Pos (6U)
  4254. #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
  4255. #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4256. #define USB_EP3R_CTR_TX_Pos (7U)
  4257. #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
  4258. #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4259. #define USB_EP3R_EP_KIND_Pos (8U)
  4260. #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
  4261. #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
  4262. #define USB_EP3R_EP_TYPE_Pos (9U)
  4263. #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
  4264. #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4265. #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
  4266. #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
  4267. #define USB_EP3R_SETUP_Pos (11U)
  4268. #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
  4269. #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
  4270. #define USB_EP3R_STAT_RX_Pos (12U)
  4271. #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
  4272. #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4273. #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
  4274. #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
  4275. #define USB_EP3R_DTOG_RX_Pos (14U)
  4276. #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
  4277. #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4278. #define USB_EP3R_CTR_RX_Pos (15U)
  4279. #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
  4280. #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4281. /******************* Bit definition for USB_EP4R register *******************/
  4282. #define USB_EP4R_EA_Pos (0U)
  4283. #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */
  4284. #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
  4285. #define USB_EP4R_STAT_TX_Pos (4U)
  4286. #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
  4287. #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4288. #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
  4289. #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
  4290. #define USB_EP4R_DTOG_TX_Pos (6U)
  4291. #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
  4292. #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4293. #define USB_EP4R_CTR_TX_Pos (7U)
  4294. #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
  4295. #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4296. #define USB_EP4R_EP_KIND_Pos (8U)
  4297. #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
  4298. #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
  4299. #define USB_EP4R_EP_TYPE_Pos (9U)
  4300. #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
  4301. #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4302. #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
  4303. #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
  4304. #define USB_EP4R_SETUP_Pos (11U)
  4305. #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
  4306. #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
  4307. #define USB_EP4R_STAT_RX_Pos (12U)
  4308. #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
  4309. #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4310. #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
  4311. #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
  4312. #define USB_EP4R_DTOG_RX_Pos (14U)
  4313. #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
  4314. #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4315. #define USB_EP4R_CTR_RX_Pos (15U)
  4316. #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
  4317. #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4318. /******************* Bit definition for USB_EP5R register *******************/
  4319. #define USB_EP5R_EA_Pos (0U)
  4320. #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */
  4321. #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
  4322. #define USB_EP5R_STAT_TX_Pos (4U)
  4323. #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
  4324. #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4325. #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
  4326. #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
  4327. #define USB_EP5R_DTOG_TX_Pos (6U)
  4328. #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
  4329. #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4330. #define USB_EP5R_CTR_TX_Pos (7U)
  4331. #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
  4332. #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4333. #define USB_EP5R_EP_KIND_Pos (8U)
  4334. #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
  4335. #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
  4336. #define USB_EP5R_EP_TYPE_Pos (9U)
  4337. #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
  4338. #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4339. #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
  4340. #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
  4341. #define USB_EP5R_SETUP_Pos (11U)
  4342. #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
  4343. #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
  4344. #define USB_EP5R_STAT_RX_Pos (12U)
  4345. #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
  4346. #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4347. #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
  4348. #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
  4349. #define USB_EP5R_DTOG_RX_Pos (14U)
  4350. #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
  4351. #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4352. #define USB_EP5R_CTR_RX_Pos (15U)
  4353. #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
  4354. #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4355. /******************* Bit definition for USB_EP6R register *******************/
  4356. #define USB_EP6R_EA_Pos (0U)
  4357. #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */
  4358. #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
  4359. #define USB_EP6R_STAT_TX_Pos (4U)
  4360. #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
  4361. #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4362. #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
  4363. #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
  4364. #define USB_EP6R_DTOG_TX_Pos (6U)
  4365. #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
  4366. #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4367. #define USB_EP6R_CTR_TX_Pos (7U)
  4368. #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
  4369. #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4370. #define USB_EP6R_EP_KIND_Pos (8U)
  4371. #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
  4372. #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
  4373. #define USB_EP6R_EP_TYPE_Pos (9U)
  4374. #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
  4375. #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4376. #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
  4377. #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
  4378. #define USB_EP6R_SETUP_Pos (11U)
  4379. #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
  4380. #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
  4381. #define USB_EP6R_STAT_RX_Pos (12U)
  4382. #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
  4383. #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4384. #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
  4385. #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
  4386. #define USB_EP6R_DTOG_RX_Pos (14U)
  4387. #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
  4388. #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4389. #define USB_EP6R_CTR_RX_Pos (15U)
  4390. #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
  4391. #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4392. /******************* Bit definition for USB_EP7R register *******************/
  4393. #define USB_EP7R_EA_Pos (0U)
  4394. #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */
  4395. #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
  4396. #define USB_EP7R_STAT_TX_Pos (4U)
  4397. #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
  4398. #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
  4399. #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
  4400. #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
  4401. #define USB_EP7R_DTOG_TX_Pos (6U)
  4402. #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
  4403. #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
  4404. #define USB_EP7R_CTR_TX_Pos (7U)
  4405. #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
  4406. #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
  4407. #define USB_EP7R_EP_KIND_Pos (8U)
  4408. #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
  4409. #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
  4410. #define USB_EP7R_EP_TYPE_Pos (9U)
  4411. #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
  4412. #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
  4413. #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
  4414. #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
  4415. #define USB_EP7R_SETUP_Pos (11U)
  4416. #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
  4417. #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
  4418. #define USB_EP7R_STAT_RX_Pos (12U)
  4419. #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
  4420. #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
  4421. #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
  4422. #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
  4423. #define USB_EP7R_DTOG_RX_Pos (14U)
  4424. #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
  4425. #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
  4426. #define USB_EP7R_CTR_RX_Pos (15U)
  4427. #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
  4428. #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
  4429. /*!< Common registers */
  4430. /******************* Bit definition for USB_CNTR register *******************/
  4431. #define USB_CNTR_FRES_Pos (0U)
  4432. #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
  4433. #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
  4434. #define USB_CNTR_PDWN_Pos (1U)
  4435. #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
  4436. #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
  4437. #define USB_CNTR_LP_MODE_Pos (2U)
  4438. #define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
  4439. #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
  4440. #define USB_CNTR_FSUSP_Pos (3U)
  4441. #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
  4442. #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
  4443. #define USB_CNTR_RESUME_Pos (4U)
  4444. #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
  4445. #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
  4446. #define USB_CNTR_ESOFM_Pos (8U)
  4447. #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
  4448. #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
  4449. #define USB_CNTR_SOFM_Pos (9U)
  4450. #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
  4451. #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
  4452. #define USB_CNTR_RESETM_Pos (10U)
  4453. #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
  4454. #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
  4455. #define USB_CNTR_SUSPM_Pos (11U)
  4456. #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
  4457. #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
  4458. #define USB_CNTR_WKUPM_Pos (12U)
  4459. #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
  4460. #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
  4461. #define USB_CNTR_ERRM_Pos (13U)
  4462. #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
  4463. #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
  4464. #define USB_CNTR_PMAOVRM_Pos (14U)
  4465. #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
  4466. #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
  4467. #define USB_CNTR_CTRM_Pos (15U)
  4468. #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
  4469. #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
  4470. /******************* Bit definition for USB_ISTR register *******************/
  4471. #define USB_ISTR_EP_ID_Pos (0U)
  4472. #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
  4473. #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
  4474. #define USB_ISTR_DIR_Pos (4U)
  4475. #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
  4476. #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
  4477. #define USB_ISTR_ESOF_Pos (8U)
  4478. #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
  4479. #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
  4480. #define USB_ISTR_SOF_Pos (9U)
  4481. #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
  4482. #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
  4483. #define USB_ISTR_RESET_Pos (10U)
  4484. #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
  4485. #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
  4486. #define USB_ISTR_SUSP_Pos (11U)
  4487. #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
  4488. #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
  4489. #define USB_ISTR_WKUP_Pos (12U)
  4490. #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
  4491. #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
  4492. #define USB_ISTR_ERR_Pos (13U)
  4493. #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
  4494. #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
  4495. #define USB_ISTR_PMAOVR_Pos (14U)
  4496. #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
  4497. #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
  4498. #define USB_ISTR_CTR_Pos (15U)
  4499. #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
  4500. #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
  4501. /******************* Bit definition for USB_FNR register ********************/
  4502. #define USB_FNR_FN_Pos (0U)
  4503. #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */
  4504. #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
  4505. #define USB_FNR_LSOF_Pos (11U)
  4506. #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
  4507. #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
  4508. #define USB_FNR_LCK_Pos (13U)
  4509. #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */
  4510. #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
  4511. #define USB_FNR_RXDM_Pos (14U)
  4512. #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
  4513. #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
  4514. #define USB_FNR_RXDP_Pos (15U)
  4515. #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
  4516. #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
  4517. /****************** Bit definition for USB_DADDR register *******************/
  4518. #define USB_DADDR_ADD_Pos (0U)
  4519. #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
  4520. #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
  4521. #define USB_DADDR_ADD0_Pos (0U)
  4522. #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
  4523. #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
  4524. #define USB_DADDR_ADD1_Pos (1U)
  4525. #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
  4526. #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
  4527. #define USB_DADDR_ADD2_Pos (2U)
  4528. #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
  4529. #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
  4530. #define USB_DADDR_ADD3_Pos (3U)
  4531. #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
  4532. #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
  4533. #define USB_DADDR_ADD4_Pos (4U)
  4534. #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
  4535. #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
  4536. #define USB_DADDR_ADD5_Pos (5U)
  4537. #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
  4538. #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
  4539. #define USB_DADDR_ADD6_Pos (6U)
  4540. #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
  4541. #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
  4542. #define USB_DADDR_EF_Pos (7U)
  4543. #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */
  4544. #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
  4545. /****************** Bit definition for USB_BTABLE register ******************/
  4546. #define USB_BTABLE_BTABLE_Pos (3U)
  4547. #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
  4548. #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
  4549. /*!< Buffer descriptor table */
  4550. /***************** Bit definition for USB_ADDR0_TX register *****************/
  4551. #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
  4552. #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
  4553. #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
  4554. /***************** Bit definition for USB_ADDR1_TX register *****************/
  4555. #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
  4556. #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
  4557. #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
  4558. /***************** Bit definition for USB_ADDR2_TX register *****************/
  4559. #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
  4560. #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
  4561. #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
  4562. /***************** Bit definition for USB_ADDR3_TX register *****************/
  4563. #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
  4564. #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
  4565. #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
  4566. /***************** Bit definition for USB_ADDR4_TX register *****************/
  4567. #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
  4568. #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
  4569. #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
  4570. /***************** Bit definition for USB_ADDR5_TX register *****************/
  4571. #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
  4572. #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
  4573. #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
  4574. /***************** Bit definition for USB_ADDR6_TX register *****************/
  4575. #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
  4576. #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
  4577. #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
  4578. /***************** Bit definition for USB_ADDR7_TX register *****************/
  4579. #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
  4580. #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
  4581. #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
  4582. /*----------------------------------------------------------------------------*/
  4583. /***************** Bit definition for USB_COUNT0_TX register ****************/
  4584. #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
  4585. #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
  4586. #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
  4587. /***************** Bit definition for USB_COUNT1_TX register ****************/
  4588. #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
  4589. #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
  4590. #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
  4591. /***************** Bit definition for USB_COUNT2_TX register ****************/
  4592. #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
  4593. #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
  4594. #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
  4595. /***************** Bit definition for USB_COUNT3_TX register ****************/
  4596. #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
  4597. #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
  4598. #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
  4599. /***************** Bit definition for USB_COUNT4_TX register ****************/
  4600. #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
  4601. #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
  4602. #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
  4603. /***************** Bit definition for USB_COUNT5_TX register ****************/
  4604. #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
  4605. #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
  4606. #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
  4607. /***************** Bit definition for USB_COUNT6_TX register ****************/
  4608. #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
  4609. #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
  4610. #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
  4611. /***************** Bit definition for USB_COUNT7_TX register ****************/
  4612. #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
  4613. #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
  4614. #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
  4615. /*----------------------------------------------------------------------------*/
  4616. /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
  4617. #define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
  4618. /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
  4619. #define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
  4620. /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
  4621. #define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
  4622. /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
  4623. #define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
  4624. /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
  4625. #define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
  4626. /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
  4627. #define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
  4628. /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
  4629. #define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
  4630. /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
  4631. #define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
  4632. /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
  4633. #define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
  4634. /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
  4635. #define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
  4636. /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
  4637. #define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
  4638. /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
  4639. #define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
  4640. /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
  4641. #define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
  4642. /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
  4643. #define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
  4644. /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
  4645. #define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
  4646. /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
  4647. #define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
  4648. /*----------------------------------------------------------------------------*/
  4649. /***************** Bit definition for USB_ADDR0_RX register *****************/
  4650. #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
  4651. #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
  4652. #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
  4653. /***************** Bit definition for USB_ADDR1_RX register *****************/
  4654. #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
  4655. #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
  4656. #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
  4657. /***************** Bit definition for USB_ADDR2_RX register *****************/
  4658. #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
  4659. #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
  4660. #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
  4661. /***************** Bit definition for USB_ADDR3_RX register *****************/
  4662. #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
  4663. #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
  4664. #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
  4665. /***************** Bit definition for USB_ADDR4_RX register *****************/
  4666. #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
  4667. #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
  4668. #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
  4669. /***************** Bit definition for USB_ADDR5_RX register *****************/
  4670. #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
  4671. #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
  4672. #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
  4673. /***************** Bit definition for USB_ADDR6_RX register *****************/
  4674. #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
  4675. #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
  4676. #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
  4677. /***************** Bit definition for USB_ADDR7_RX register *****************/
  4678. #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
  4679. #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
  4680. #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
  4681. /*----------------------------------------------------------------------------*/
  4682. /***************** Bit definition for USB_COUNT0_RX register ****************/
  4683. #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
  4684. #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
  4685. #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
  4686. #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
  4687. #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4688. #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4689. #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4690. #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4691. #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4692. #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4693. #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4694. #define USB_COUNT0_RX_BLSIZE_Pos (15U)
  4695. #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4696. #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
  4697. /***************** Bit definition for USB_COUNT1_RX register ****************/
  4698. #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
  4699. #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
  4700. #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
  4701. #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
  4702. #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4703. #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4704. #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4705. #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4706. #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4707. #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4708. #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4709. #define USB_COUNT1_RX_BLSIZE_Pos (15U)
  4710. #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4711. #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
  4712. /***************** Bit definition for USB_COUNT2_RX register ****************/
  4713. #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
  4714. #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
  4715. #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
  4716. #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
  4717. #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4718. #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4719. #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4720. #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4721. #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4722. #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4723. #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4724. #define USB_COUNT2_RX_BLSIZE_Pos (15U)
  4725. #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4726. #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
  4727. /***************** Bit definition for USB_COUNT3_RX register ****************/
  4728. #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
  4729. #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
  4730. #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
  4731. #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
  4732. #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4733. #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4734. #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4735. #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4736. #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4737. #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4738. #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4739. #define USB_COUNT3_RX_BLSIZE_Pos (15U)
  4740. #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4741. #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
  4742. /***************** Bit definition for USB_COUNT4_RX register ****************/
  4743. #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
  4744. #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
  4745. #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
  4746. #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
  4747. #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4748. #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4749. #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4750. #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4751. #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4752. #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4753. #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4754. #define USB_COUNT4_RX_BLSIZE_Pos (15U)
  4755. #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4756. #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
  4757. /***************** Bit definition for USB_COUNT5_RX register ****************/
  4758. #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
  4759. #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
  4760. #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
  4761. #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
  4762. #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4763. #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4764. #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4765. #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4766. #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4767. #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4768. #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4769. #define USB_COUNT5_RX_BLSIZE_Pos (15U)
  4770. #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4771. #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
  4772. /***************** Bit definition for USB_COUNT6_RX register ****************/
  4773. #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
  4774. #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
  4775. #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
  4776. #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
  4777. #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4778. #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4779. #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4780. #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4781. #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4782. #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4783. #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4784. #define USB_COUNT6_RX_BLSIZE_Pos (15U)
  4785. #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4786. #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
  4787. /***************** Bit definition for USB_COUNT7_RX register ****************/
  4788. #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
  4789. #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
  4790. #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
  4791. #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
  4792. #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
  4793. #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
  4794. #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
  4795. #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
  4796. #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
  4797. #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
  4798. #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
  4799. #define USB_COUNT7_RX_BLSIZE_Pos (15U)
  4800. #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
  4801. #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
  4802. /*----------------------------------------------------------------------------*/
  4803. /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
  4804. #define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4805. #define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4806. #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4807. #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4808. #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4809. #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4810. #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4811. #define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4812. /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
  4813. #define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4814. #define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4815. #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
  4816. #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4817. #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4818. #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4819. #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4820. #define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4821. /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
  4822. #define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4823. #define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4824. #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4825. #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4826. #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4827. #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4828. #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4829. #define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4830. /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
  4831. #define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4832. #define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4833. #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4834. #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4835. #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4836. #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4837. #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4838. #define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4839. /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
  4840. #define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4841. #define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4842. #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4843. #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4844. #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4845. #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4846. #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4847. #define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4848. /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
  4849. #define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4850. #define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4851. #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4852. #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4853. #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4854. #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4855. #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4856. #define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4857. /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
  4858. #define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4859. #define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4860. #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4861. #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4862. #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4863. #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4864. #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4865. #define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4866. /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
  4867. #define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4868. #define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4869. #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4870. #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4871. #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4872. #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4873. #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4874. #define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4875. /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
  4876. #define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4877. #define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4878. #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4879. #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4880. #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4881. #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4882. #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4883. #define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4884. /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
  4885. #define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4886. #define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4887. #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4888. #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4889. #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4890. #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4891. #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4892. #define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4893. /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
  4894. #define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4895. #define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4896. #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4897. #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4898. #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4899. #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4900. #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4901. #define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4902. /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
  4903. #define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4904. #define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4905. #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4906. #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4907. #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4908. #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4909. #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4910. #define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4911. /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
  4912. #define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4913. #define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4914. #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4915. #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4916. #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4917. #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4918. #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4919. #define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4920. /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
  4921. #define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4922. #define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4923. #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4924. #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4925. #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4926. #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4927. #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4928. #define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4929. /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
  4930. #define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
  4931. #define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
  4932. #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
  4933. #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
  4934. #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
  4935. #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
  4936. #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
  4937. #define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
  4938. /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
  4939. #define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
  4940. #define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
  4941. #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
  4942. #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
  4943. #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
  4944. #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
  4945. #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
  4946. #define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
  4947. /******************************************************************************/
  4948. /* */
  4949. /* Controller Area Network */
  4950. /* */
  4951. /******************************************************************************/
  4952. /*!< CAN control and status registers */
  4953. /******************* Bit definition for CAN_MCR register ********************/
  4954. #define CAN_MCR_INRQ_Pos (0U)
  4955. #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
  4956. #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
  4957. #define CAN_MCR_SLEEP_Pos (1U)
  4958. #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
  4959. #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
  4960. #define CAN_MCR_TXFP_Pos (2U)
  4961. #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
  4962. #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
  4963. #define CAN_MCR_RFLM_Pos (3U)
  4964. #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
  4965. #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
  4966. #define CAN_MCR_NART_Pos (4U)
  4967. #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
  4968. #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
  4969. #define CAN_MCR_AWUM_Pos (5U)
  4970. #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
  4971. #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
  4972. #define CAN_MCR_ABOM_Pos (6U)
  4973. #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
  4974. #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
  4975. #define CAN_MCR_TTCM_Pos (7U)
  4976. #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
  4977. #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
  4978. #define CAN_MCR_RESET_Pos (15U)
  4979. #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
  4980. #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
  4981. #define CAN_MCR_DBF_Pos (16U)
  4982. #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
  4983. #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
  4984. /******************* Bit definition for CAN_MSR register ********************/
  4985. #define CAN_MSR_INAK_Pos (0U)
  4986. #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
  4987. #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
  4988. #define CAN_MSR_SLAK_Pos (1U)
  4989. #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
  4990. #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
  4991. #define CAN_MSR_ERRI_Pos (2U)
  4992. #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
  4993. #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
  4994. #define CAN_MSR_WKUI_Pos (3U)
  4995. #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
  4996. #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
  4997. #define CAN_MSR_SLAKI_Pos (4U)
  4998. #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
  4999. #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
  5000. #define CAN_MSR_TXM_Pos (8U)
  5001. #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
  5002. #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
  5003. #define CAN_MSR_RXM_Pos (9U)
  5004. #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
  5005. #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
  5006. #define CAN_MSR_SAMP_Pos (10U)
  5007. #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
  5008. #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
  5009. #define CAN_MSR_RX_Pos (11U)
  5010. #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
  5011. #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
  5012. /******************* Bit definition for CAN_TSR register ********************/
  5013. #define CAN_TSR_RQCP0_Pos (0U)
  5014. #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
  5015. #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
  5016. #define CAN_TSR_TXOK0_Pos (1U)
  5017. #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
  5018. #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
  5019. #define CAN_TSR_ALST0_Pos (2U)
  5020. #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
  5021. #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
  5022. #define CAN_TSR_TERR0_Pos (3U)
  5023. #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
  5024. #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
  5025. #define CAN_TSR_ABRQ0_Pos (7U)
  5026. #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
  5027. #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
  5028. #define CAN_TSR_RQCP1_Pos (8U)
  5029. #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
  5030. #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
  5031. #define CAN_TSR_TXOK1_Pos (9U)
  5032. #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
  5033. #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
  5034. #define CAN_TSR_ALST1_Pos (10U)
  5035. #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
  5036. #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
  5037. #define CAN_TSR_TERR1_Pos (11U)
  5038. #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
  5039. #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
  5040. #define CAN_TSR_ABRQ1_Pos (15U)
  5041. #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
  5042. #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
  5043. #define CAN_TSR_RQCP2_Pos (16U)
  5044. #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
  5045. #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
  5046. #define CAN_TSR_TXOK2_Pos (17U)
  5047. #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
  5048. #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
  5049. #define CAN_TSR_ALST2_Pos (18U)
  5050. #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
  5051. #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
  5052. #define CAN_TSR_TERR2_Pos (19U)
  5053. #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
  5054. #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
  5055. #define CAN_TSR_ABRQ2_Pos (23U)
  5056. #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
  5057. #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
  5058. #define CAN_TSR_CODE_Pos (24U)
  5059. #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
  5060. #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
  5061. #define CAN_TSR_TME_Pos (26U)
  5062. #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
  5063. #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
  5064. #define CAN_TSR_TME0_Pos (26U)
  5065. #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
  5066. #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
  5067. #define CAN_TSR_TME1_Pos (27U)
  5068. #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
  5069. #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
  5070. #define CAN_TSR_TME2_Pos (28U)
  5071. #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
  5072. #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
  5073. #define CAN_TSR_LOW_Pos (29U)
  5074. #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
  5075. #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
  5076. #define CAN_TSR_LOW0_Pos (29U)
  5077. #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
  5078. #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
  5079. #define CAN_TSR_LOW1_Pos (30U)
  5080. #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
  5081. #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
  5082. #define CAN_TSR_LOW2_Pos (31U)
  5083. #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
  5084. #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
  5085. /******************* Bit definition for CAN_RF0R register *******************/
  5086. #define CAN_RF0R_FMP0_Pos (0U)
  5087. #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
  5088. #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
  5089. #define CAN_RF0R_FULL0_Pos (3U)
  5090. #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
  5091. #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
  5092. #define CAN_RF0R_FOVR0_Pos (4U)
  5093. #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
  5094. #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
  5095. #define CAN_RF0R_RFOM0_Pos (5U)
  5096. #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
  5097. #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
  5098. /******************* Bit definition for CAN_RF1R register *******************/
  5099. #define CAN_RF1R_FMP1_Pos (0U)
  5100. #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
  5101. #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
  5102. #define CAN_RF1R_FULL1_Pos (3U)
  5103. #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
  5104. #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
  5105. #define CAN_RF1R_FOVR1_Pos (4U)
  5106. #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
  5107. #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
  5108. #define CAN_RF1R_RFOM1_Pos (5U)
  5109. #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
  5110. #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
  5111. /******************** Bit definition for CAN_IER register *******************/
  5112. #define CAN_IER_TMEIE_Pos (0U)
  5113. #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
  5114. #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
  5115. #define CAN_IER_FMPIE0_Pos (1U)
  5116. #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
  5117. #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
  5118. #define CAN_IER_FFIE0_Pos (2U)
  5119. #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
  5120. #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
  5121. #define CAN_IER_FOVIE0_Pos (3U)
  5122. #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
  5123. #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
  5124. #define CAN_IER_FMPIE1_Pos (4U)
  5125. #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
  5126. #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
  5127. #define CAN_IER_FFIE1_Pos (5U)
  5128. #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
  5129. #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
  5130. #define CAN_IER_FOVIE1_Pos (6U)
  5131. #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
  5132. #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
  5133. #define CAN_IER_EWGIE_Pos (8U)
  5134. #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
  5135. #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
  5136. #define CAN_IER_EPVIE_Pos (9U)
  5137. #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
  5138. #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
  5139. #define CAN_IER_BOFIE_Pos (10U)
  5140. #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
  5141. #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
  5142. #define CAN_IER_LECIE_Pos (11U)
  5143. #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
  5144. #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
  5145. #define CAN_IER_ERRIE_Pos (15U)
  5146. #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
  5147. #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
  5148. #define CAN_IER_WKUIE_Pos (16U)
  5149. #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
  5150. #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
  5151. #define CAN_IER_SLKIE_Pos (17U)
  5152. #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
  5153. #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
  5154. /******************** Bit definition for CAN_ESR register *******************/
  5155. #define CAN_ESR_EWGF_Pos (0U)
  5156. #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
  5157. #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
  5158. #define CAN_ESR_EPVF_Pos (1U)
  5159. #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
  5160. #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
  5161. #define CAN_ESR_BOFF_Pos (2U)
  5162. #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
  5163. #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
  5164. #define CAN_ESR_LEC_Pos (4U)
  5165. #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
  5166. #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
  5167. #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
  5168. #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
  5169. #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
  5170. #define CAN_ESR_TEC_Pos (16U)
  5171. #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
  5172. #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
  5173. #define CAN_ESR_REC_Pos (24U)
  5174. #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
  5175. #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
  5176. /******************* Bit definition for CAN_BTR register ********************/
  5177. #define CAN_BTR_BRP_Pos (0U)
  5178. #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
  5179. #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
  5180. #define CAN_BTR_TS1_Pos (16U)
  5181. #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
  5182. #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
  5183. #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
  5184. #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
  5185. #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
  5186. #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
  5187. #define CAN_BTR_TS2_Pos (20U)
  5188. #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
  5189. #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
  5190. #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
  5191. #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
  5192. #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
  5193. #define CAN_BTR_SJW_Pos (24U)
  5194. #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
  5195. #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
  5196. #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
  5197. #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
  5198. #define CAN_BTR_LBKM_Pos (30U)
  5199. #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
  5200. #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
  5201. #define CAN_BTR_SILM_Pos (31U)
  5202. #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
  5203. #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
  5204. /*!< Mailbox registers */
  5205. /****************** Bit definition for CAN_TI0R register ********************/
  5206. #define CAN_TI0R_TXRQ_Pos (0U)
  5207. #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
  5208. #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
  5209. #define CAN_TI0R_RTR_Pos (1U)
  5210. #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
  5211. #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
  5212. #define CAN_TI0R_IDE_Pos (2U)
  5213. #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
  5214. #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
  5215. #define CAN_TI0R_EXID_Pos (3U)
  5216. #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
  5217. #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
  5218. #define CAN_TI0R_STID_Pos (21U)
  5219. #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
  5220. #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
  5221. /****************** Bit definition for CAN_TDT0R register *******************/
  5222. #define CAN_TDT0R_DLC_Pos (0U)
  5223. #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
  5224. #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
  5225. #define CAN_TDT0R_TGT_Pos (8U)
  5226. #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
  5227. #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
  5228. #define CAN_TDT0R_TIME_Pos (16U)
  5229. #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  5230. #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
  5231. /****************** Bit definition for CAN_TDL0R register *******************/
  5232. #define CAN_TDL0R_DATA0_Pos (0U)
  5233. #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
  5234. #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
  5235. #define CAN_TDL0R_DATA1_Pos (8U)
  5236. #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  5237. #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
  5238. #define CAN_TDL0R_DATA2_Pos (16U)
  5239. #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  5240. #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
  5241. #define CAN_TDL0R_DATA3_Pos (24U)
  5242. #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
  5243. #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
  5244. /****************** Bit definition for CAN_TDH0R register *******************/
  5245. #define CAN_TDH0R_DATA4_Pos (0U)
  5246. #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
  5247. #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
  5248. #define CAN_TDH0R_DATA5_Pos (8U)
  5249. #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  5250. #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
  5251. #define CAN_TDH0R_DATA6_Pos (16U)
  5252. #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  5253. #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
  5254. #define CAN_TDH0R_DATA7_Pos (24U)
  5255. #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
  5256. #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
  5257. /******************* Bit definition for CAN_TI1R register *******************/
  5258. #define CAN_TI1R_TXRQ_Pos (0U)
  5259. #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
  5260. #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
  5261. #define CAN_TI1R_RTR_Pos (1U)
  5262. #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
  5263. #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
  5264. #define CAN_TI1R_IDE_Pos (2U)
  5265. #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
  5266. #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
  5267. #define CAN_TI1R_EXID_Pos (3U)
  5268. #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
  5269. #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
  5270. #define CAN_TI1R_STID_Pos (21U)
  5271. #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
  5272. #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
  5273. /******************* Bit definition for CAN_TDT1R register ******************/
  5274. #define CAN_TDT1R_DLC_Pos (0U)
  5275. #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
  5276. #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
  5277. #define CAN_TDT1R_TGT_Pos (8U)
  5278. #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
  5279. #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
  5280. #define CAN_TDT1R_TIME_Pos (16U)
  5281. #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  5282. #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
  5283. /******************* Bit definition for CAN_TDL1R register ******************/
  5284. #define CAN_TDL1R_DATA0_Pos (0U)
  5285. #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
  5286. #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
  5287. #define CAN_TDL1R_DATA1_Pos (8U)
  5288. #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  5289. #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
  5290. #define CAN_TDL1R_DATA2_Pos (16U)
  5291. #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  5292. #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
  5293. #define CAN_TDL1R_DATA3_Pos (24U)
  5294. #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
  5295. #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
  5296. /******************* Bit definition for CAN_TDH1R register ******************/
  5297. #define CAN_TDH1R_DATA4_Pos (0U)
  5298. #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
  5299. #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
  5300. #define CAN_TDH1R_DATA5_Pos (8U)
  5301. #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  5302. #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
  5303. #define CAN_TDH1R_DATA6_Pos (16U)
  5304. #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  5305. #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
  5306. #define CAN_TDH1R_DATA7_Pos (24U)
  5307. #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
  5308. #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
  5309. /******************* Bit definition for CAN_TI2R register *******************/
  5310. #define CAN_TI2R_TXRQ_Pos (0U)
  5311. #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
  5312. #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
  5313. #define CAN_TI2R_RTR_Pos (1U)
  5314. #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
  5315. #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
  5316. #define CAN_TI2R_IDE_Pos (2U)
  5317. #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
  5318. #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
  5319. #define CAN_TI2R_EXID_Pos (3U)
  5320. #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
  5321. #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
  5322. #define CAN_TI2R_STID_Pos (21U)
  5323. #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
  5324. #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
  5325. /******************* Bit definition for CAN_TDT2R register ******************/
  5326. #define CAN_TDT2R_DLC_Pos (0U)
  5327. #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
  5328. #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
  5329. #define CAN_TDT2R_TGT_Pos (8U)
  5330. #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
  5331. #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
  5332. #define CAN_TDT2R_TIME_Pos (16U)
  5333. #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
  5334. #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
  5335. /******************* Bit definition for CAN_TDL2R register ******************/
  5336. #define CAN_TDL2R_DATA0_Pos (0U)
  5337. #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
  5338. #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
  5339. #define CAN_TDL2R_DATA1_Pos (8U)
  5340. #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
  5341. #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
  5342. #define CAN_TDL2R_DATA2_Pos (16U)
  5343. #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
  5344. #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
  5345. #define CAN_TDL2R_DATA3_Pos (24U)
  5346. #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
  5347. #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
  5348. /******************* Bit definition for CAN_TDH2R register ******************/
  5349. #define CAN_TDH2R_DATA4_Pos (0U)
  5350. #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
  5351. #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
  5352. #define CAN_TDH2R_DATA5_Pos (8U)
  5353. #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
  5354. #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
  5355. #define CAN_TDH2R_DATA6_Pos (16U)
  5356. #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
  5357. #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
  5358. #define CAN_TDH2R_DATA7_Pos (24U)
  5359. #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
  5360. #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
  5361. /******************* Bit definition for CAN_RI0R register *******************/
  5362. #define CAN_RI0R_RTR_Pos (1U)
  5363. #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
  5364. #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
  5365. #define CAN_RI0R_IDE_Pos (2U)
  5366. #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
  5367. #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
  5368. #define CAN_RI0R_EXID_Pos (3U)
  5369. #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
  5370. #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
  5371. #define CAN_RI0R_STID_Pos (21U)
  5372. #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
  5373. #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
  5374. /******************* Bit definition for CAN_RDT0R register ******************/
  5375. #define CAN_RDT0R_DLC_Pos (0U)
  5376. #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
  5377. #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
  5378. #define CAN_RDT0R_FMI_Pos (8U)
  5379. #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
  5380. #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
  5381. #define CAN_RDT0R_TIME_Pos (16U)
  5382. #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
  5383. #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
  5384. /******************* Bit definition for CAN_RDL0R register ******************/
  5385. #define CAN_RDL0R_DATA0_Pos (0U)
  5386. #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
  5387. #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
  5388. #define CAN_RDL0R_DATA1_Pos (8U)
  5389. #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
  5390. #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
  5391. #define CAN_RDL0R_DATA2_Pos (16U)
  5392. #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
  5393. #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
  5394. #define CAN_RDL0R_DATA3_Pos (24U)
  5395. #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
  5396. #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
  5397. /******************* Bit definition for CAN_RDH0R register ******************/
  5398. #define CAN_RDH0R_DATA4_Pos (0U)
  5399. #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
  5400. #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
  5401. #define CAN_RDH0R_DATA5_Pos (8U)
  5402. #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
  5403. #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
  5404. #define CAN_RDH0R_DATA6_Pos (16U)
  5405. #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
  5406. #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
  5407. #define CAN_RDH0R_DATA7_Pos (24U)
  5408. #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
  5409. #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
  5410. /******************* Bit definition for CAN_RI1R register *******************/
  5411. #define CAN_RI1R_RTR_Pos (1U)
  5412. #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
  5413. #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
  5414. #define CAN_RI1R_IDE_Pos (2U)
  5415. #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
  5416. #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
  5417. #define CAN_RI1R_EXID_Pos (3U)
  5418. #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
  5419. #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
  5420. #define CAN_RI1R_STID_Pos (21U)
  5421. #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
  5422. #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
  5423. /******************* Bit definition for CAN_RDT1R register ******************/
  5424. #define CAN_RDT1R_DLC_Pos (0U)
  5425. #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
  5426. #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
  5427. #define CAN_RDT1R_FMI_Pos (8U)
  5428. #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
  5429. #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
  5430. #define CAN_RDT1R_TIME_Pos (16U)
  5431. #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
  5432. #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
  5433. /******************* Bit definition for CAN_RDL1R register ******************/
  5434. #define CAN_RDL1R_DATA0_Pos (0U)
  5435. #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
  5436. #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
  5437. #define CAN_RDL1R_DATA1_Pos (8U)
  5438. #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
  5439. #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
  5440. #define CAN_RDL1R_DATA2_Pos (16U)
  5441. #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
  5442. #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
  5443. #define CAN_RDL1R_DATA3_Pos (24U)
  5444. #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
  5445. #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
  5446. /******************* Bit definition for CAN_RDH1R register ******************/
  5447. #define CAN_RDH1R_DATA4_Pos (0U)
  5448. #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
  5449. #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
  5450. #define CAN_RDH1R_DATA5_Pos (8U)
  5451. #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
  5452. #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
  5453. #define CAN_RDH1R_DATA6_Pos (16U)
  5454. #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
  5455. #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
  5456. #define CAN_RDH1R_DATA7_Pos (24U)
  5457. #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
  5458. #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
  5459. /*!< CAN filter registers */
  5460. /******************* Bit definition for CAN_FMR register ********************/
  5461. #define CAN_FMR_FINIT_Pos (0U)
  5462. #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
  5463. #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
  5464. #define CAN_FMR_CAN2SB_Pos (8U)
  5465. #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
  5466. #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
  5467. /******************* Bit definition for CAN_FM1R register *******************/
  5468. #define CAN_FM1R_FBM_Pos (0U)
  5469. #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
  5470. #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
  5471. #define CAN_FM1R_FBM0_Pos (0U)
  5472. #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
  5473. #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
  5474. #define CAN_FM1R_FBM1_Pos (1U)
  5475. #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
  5476. #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
  5477. #define CAN_FM1R_FBM2_Pos (2U)
  5478. #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
  5479. #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
  5480. #define CAN_FM1R_FBM3_Pos (3U)
  5481. #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
  5482. #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
  5483. #define CAN_FM1R_FBM4_Pos (4U)
  5484. #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
  5485. #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
  5486. #define CAN_FM1R_FBM5_Pos (5U)
  5487. #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
  5488. #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
  5489. #define CAN_FM1R_FBM6_Pos (6U)
  5490. #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
  5491. #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
  5492. #define CAN_FM1R_FBM7_Pos (7U)
  5493. #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
  5494. #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
  5495. #define CAN_FM1R_FBM8_Pos (8U)
  5496. #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
  5497. #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
  5498. #define CAN_FM1R_FBM9_Pos (9U)
  5499. #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
  5500. #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
  5501. #define CAN_FM1R_FBM10_Pos (10U)
  5502. #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
  5503. #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
  5504. #define CAN_FM1R_FBM11_Pos (11U)
  5505. #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
  5506. #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
  5507. #define CAN_FM1R_FBM12_Pos (12U)
  5508. #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
  5509. #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
  5510. #define CAN_FM1R_FBM13_Pos (13U)
  5511. #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
  5512. #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
  5513. /******************* Bit definition for CAN_FS1R register *******************/
  5514. #define CAN_FS1R_FSC_Pos (0U)
  5515. #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
  5516. #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
  5517. #define CAN_FS1R_FSC0_Pos (0U)
  5518. #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
  5519. #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
  5520. #define CAN_FS1R_FSC1_Pos (1U)
  5521. #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
  5522. #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
  5523. #define CAN_FS1R_FSC2_Pos (2U)
  5524. #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
  5525. #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
  5526. #define CAN_FS1R_FSC3_Pos (3U)
  5527. #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
  5528. #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
  5529. #define CAN_FS1R_FSC4_Pos (4U)
  5530. #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
  5531. #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
  5532. #define CAN_FS1R_FSC5_Pos (5U)
  5533. #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
  5534. #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
  5535. #define CAN_FS1R_FSC6_Pos (6U)
  5536. #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
  5537. #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
  5538. #define CAN_FS1R_FSC7_Pos (7U)
  5539. #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
  5540. #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
  5541. #define CAN_FS1R_FSC8_Pos (8U)
  5542. #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
  5543. #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
  5544. #define CAN_FS1R_FSC9_Pos (9U)
  5545. #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
  5546. #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
  5547. #define CAN_FS1R_FSC10_Pos (10U)
  5548. #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
  5549. #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
  5550. #define CAN_FS1R_FSC11_Pos (11U)
  5551. #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
  5552. #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
  5553. #define CAN_FS1R_FSC12_Pos (12U)
  5554. #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
  5555. #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
  5556. #define CAN_FS1R_FSC13_Pos (13U)
  5557. #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
  5558. #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
  5559. /****************** Bit definition for CAN_FFA1R register *******************/
  5560. #define CAN_FFA1R_FFA_Pos (0U)
  5561. #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
  5562. #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
  5563. #define CAN_FFA1R_FFA0_Pos (0U)
  5564. #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
  5565. #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
  5566. #define CAN_FFA1R_FFA1_Pos (1U)
  5567. #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
  5568. #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
  5569. #define CAN_FFA1R_FFA2_Pos (2U)
  5570. #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
  5571. #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
  5572. #define CAN_FFA1R_FFA3_Pos (3U)
  5573. #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
  5574. #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
  5575. #define CAN_FFA1R_FFA4_Pos (4U)
  5576. #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
  5577. #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
  5578. #define CAN_FFA1R_FFA5_Pos (5U)
  5579. #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
  5580. #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
  5581. #define CAN_FFA1R_FFA6_Pos (6U)
  5582. #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
  5583. #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
  5584. #define CAN_FFA1R_FFA7_Pos (7U)
  5585. #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
  5586. #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
  5587. #define CAN_FFA1R_FFA8_Pos (8U)
  5588. #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
  5589. #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
  5590. #define CAN_FFA1R_FFA9_Pos (9U)
  5591. #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
  5592. #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
  5593. #define CAN_FFA1R_FFA10_Pos (10U)
  5594. #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
  5595. #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
  5596. #define CAN_FFA1R_FFA11_Pos (11U)
  5597. #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
  5598. #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
  5599. #define CAN_FFA1R_FFA12_Pos (12U)
  5600. #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
  5601. #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
  5602. #define CAN_FFA1R_FFA13_Pos (13U)
  5603. #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
  5604. #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
  5605. /******************* Bit definition for CAN_FA1R register *******************/
  5606. #define CAN_FA1R_FACT_Pos (0U)
  5607. #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
  5608. #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
  5609. #define CAN_FA1R_FACT0_Pos (0U)
  5610. #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
  5611. #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
  5612. #define CAN_FA1R_FACT1_Pos (1U)
  5613. #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
  5614. #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
  5615. #define CAN_FA1R_FACT2_Pos (2U)
  5616. #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
  5617. #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
  5618. #define CAN_FA1R_FACT3_Pos (3U)
  5619. #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
  5620. #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
  5621. #define CAN_FA1R_FACT4_Pos (4U)
  5622. #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
  5623. #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
  5624. #define CAN_FA1R_FACT5_Pos (5U)
  5625. #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
  5626. #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
  5627. #define CAN_FA1R_FACT6_Pos (6U)
  5628. #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
  5629. #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
  5630. #define CAN_FA1R_FACT7_Pos (7U)
  5631. #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
  5632. #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
  5633. #define CAN_FA1R_FACT8_Pos (8U)
  5634. #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
  5635. #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
  5636. #define CAN_FA1R_FACT9_Pos (9U)
  5637. #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
  5638. #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
  5639. #define CAN_FA1R_FACT10_Pos (10U)
  5640. #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
  5641. #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
  5642. #define CAN_FA1R_FACT11_Pos (11U)
  5643. #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
  5644. #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
  5645. #define CAN_FA1R_FACT12_Pos (12U)
  5646. #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
  5647. #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
  5648. #define CAN_FA1R_FACT13_Pos (13U)
  5649. #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
  5650. #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
  5651. /******************* Bit definition for CAN_F0R1 register *******************/
  5652. #define CAN_F0R1_FB0_Pos (0U)
  5653. #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
  5654. #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
  5655. #define CAN_F0R1_FB1_Pos (1U)
  5656. #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
  5657. #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
  5658. #define CAN_F0R1_FB2_Pos (2U)
  5659. #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
  5660. #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
  5661. #define CAN_F0R1_FB3_Pos (3U)
  5662. #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
  5663. #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
  5664. #define CAN_F0R1_FB4_Pos (4U)
  5665. #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
  5666. #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
  5667. #define CAN_F0R1_FB5_Pos (5U)
  5668. #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
  5669. #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
  5670. #define CAN_F0R1_FB6_Pos (6U)
  5671. #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
  5672. #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
  5673. #define CAN_F0R1_FB7_Pos (7U)
  5674. #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
  5675. #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
  5676. #define CAN_F0R1_FB8_Pos (8U)
  5677. #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
  5678. #define CAN_F0R1_FB8