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stm32f1xx_ll_bus.h 44KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f1xx_ll_bus.h
  4. * @author MCD Application Team
  5. * @brief Header file of BUS LL module.
  6. @verbatim
  7. ##### RCC Limitations #####
  8. ==============================================================================
  9. [..]
  10. A delay between an RCC peripheral clock enable and the effective peripheral
  11. enabling should be taken into account in order to manage the peripheral read/write
  12. from/to registers.
  13. (+) This delay depends on the peripheral mapping.
  14. (++) AHB & APB peripherals, 1 dummy read is necessary
  15. [..]
  16. Workarounds:
  17. (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
  18. inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
  19. @endverbatim
  20. ******************************************************************************
  21. * @attention
  22. *
  23. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  24. * All rights reserved.</center></h2>
  25. *
  26. * This software component is licensed by ST under BSD 3-Clause license,
  27. * the "License"; You may not use this file except in compliance with the
  28. * License. You may obtain a copy of the License at:
  29. * opensource.org/licenses/BSD-3-Clause
  30. *
  31. ******************************************************************************
  32. */
  33. /* Define to prevent recursive inclusion -------------------------------------*/
  34. #ifndef __STM32F1xx_LL_BUS_H
  35. #define __STM32F1xx_LL_BUS_H
  36. #ifdef __cplusplus
  37. extern "C" {
  38. #endif
  39. /* Includes ------------------------------------------------------------------*/
  40. #include "stm32f1xx.h"
  41. /** @addtogroup STM32F1xx_LL_Driver
  42. * @{
  43. */
  44. #if defined(RCC)
  45. /** @defgroup BUS_LL BUS
  46. * @{
  47. */
  48. /* Private types -------------------------------------------------------------*/
  49. /* Private variables ---------------------------------------------------------*/
  50. /* Private constants ---------------------------------------------------------*/
  51. #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
  52. #define RCC_AHBRSTR_SUPPORT
  53. #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
  54. /* Private macros ------------------------------------------------------------*/
  55. /* Exported types ------------------------------------------------------------*/
  56. /* Exported constants --------------------------------------------------------*/
  57. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
  58. * @{
  59. */
  60. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
  61. * @{
  62. */
  63. #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  64. #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
  65. #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
  66. #if defined(DMA2)
  67. #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
  68. #endif /*DMA2*/
  69. #if defined(ETH)
  70. #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
  71. #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
  72. #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
  73. #endif /*ETH*/
  74. #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
  75. #if defined(FSMC_Bank1)
  76. #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
  77. #endif /*FSMC_Bank1*/
  78. #if defined(USB_OTG_FS)
  79. #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
  80. #endif /*USB_OTG_FS*/
  81. #if defined(SDIO)
  82. #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
  83. #endif /*SDIO*/
  84. #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
  85. /**
  86. * @}
  87. */
  88. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
  89. * @{
  90. */
  91. #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  92. #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
  93. #if defined(CAN1)
  94. #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
  95. #endif /*CAN1*/
  96. #if defined(CAN2)
  97. #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
  98. #endif /*CAN2*/
  99. #if defined(CEC)
  100. #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
  101. #endif /*CEC*/
  102. #if defined(DAC)
  103. #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
  104. #endif /*DAC*/
  105. #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
  106. #if defined(I2C2)
  107. #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
  108. #endif /*I2C2*/
  109. #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
  110. #if defined(SPI2)
  111. #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
  112. #endif /*SPI2*/
  113. #if defined(SPI3)
  114. #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
  115. #endif /*SPI3*/
  116. #if defined(TIM12)
  117. #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
  118. #endif /*TIM12*/
  119. #if defined(TIM13)
  120. #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
  121. #endif /*TIM13*/
  122. #if defined(TIM14)
  123. #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
  124. #endif /*TIM14*/
  125. #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
  126. #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
  127. #if defined(TIM4)
  128. #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
  129. #endif /*TIM4*/
  130. #if defined(TIM5)
  131. #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
  132. #endif /*TIM5*/
  133. #if defined(TIM6)
  134. #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
  135. #endif /*TIM6*/
  136. #if defined(TIM7)
  137. #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
  138. #endif /*TIM7*/
  139. #if defined(UART4)
  140. #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
  141. #endif /*UART4*/
  142. #if defined(UART5)
  143. #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
  144. #endif /*UART5*/
  145. #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
  146. #if defined(USART3)
  147. #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
  148. #endif /*USART3*/
  149. #if defined(USB)
  150. #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
  151. #endif /*USB*/
  152. #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
  153. /**
  154. * @}
  155. */
  156. /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
  157. * @{
  158. */
  159. #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
  160. #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
  161. #if defined(ADC2)
  162. #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
  163. #endif /*ADC2*/
  164. #if defined(ADC3)
  165. #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
  166. #endif /*ADC3*/
  167. #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
  168. #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
  169. #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
  170. #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
  171. #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
  172. #if defined(GPIOE)
  173. #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
  174. #endif /*GPIOE*/
  175. #if defined(GPIOF)
  176. #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
  177. #endif /*GPIOF*/
  178. #if defined(GPIOG)
  179. #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
  180. #endif /*GPIOG*/
  181. #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
  182. #if defined(TIM10)
  183. #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
  184. #endif /*TIM10*/
  185. #if defined(TIM11)
  186. #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
  187. #endif /*TIM11*/
  188. #if defined(TIM15)
  189. #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
  190. #endif /*TIM15*/
  191. #if defined(TIM16)
  192. #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
  193. #endif /*TIM16*/
  194. #if defined(TIM17)
  195. #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
  196. #endif /*TIM17*/
  197. #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
  198. #if defined(TIM8)
  199. #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
  200. #endif /*TIM8*/
  201. #if defined(TIM9)
  202. #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
  203. #endif /*TIM9*/
  204. #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
  205. /**
  206. * @}
  207. */
  208. /**
  209. * @}
  210. */
  211. /* Exported macro ------------------------------------------------------------*/
  212. /* Exported functions --------------------------------------------------------*/
  213. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
  214. * @{
  215. */
  216. /** @defgroup BUS_LL_EF_AHB1 AHB1
  217. * @{
  218. */
  219. /**
  220. * @brief Enable AHB1 peripherals clock.
  221. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
  222. * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
  223. * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
  224. * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
  225. * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
  226. * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
  227. * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
  228. * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
  229. * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
  230. * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
  231. * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
  232. * @param Periphs This parameter can be a combination of the following values:
  233. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  234. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  235. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  236. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  237. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  238. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  239. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  240. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  241. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  242. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  243. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  244. *
  245. * (*) value not defined in all devices.
  246. * @retval None
  247. */
  248. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
  249. {
  250. __IO uint32_t tmpreg;
  251. SET_BIT(RCC->AHBENR, Periphs);
  252. /* Delay after an RCC peripheral clock enabling */
  253. tmpreg = READ_BIT(RCC->AHBENR, Periphs);
  254. (void)tmpreg;
  255. }
  256. /**
  257. * @brief Check if AHB1 peripheral clock is enabled or not
  258. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
  259. * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
  260. * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
  261. * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
  262. * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
  263. * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
  264. * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
  265. * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
  266. * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
  267. * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
  268. * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
  269. * @param Periphs This parameter can be a combination of the following values:
  270. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  271. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  272. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  273. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  274. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  275. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  276. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  277. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  278. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  279. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  280. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  281. *
  282. * (*) value not defined in all devices.
  283. * @retval State of Periphs (1 or 0).
  284. */
  285. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
  286. {
  287. return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
  288. }
  289. /**
  290. * @brief Disable AHB1 peripherals clock.
  291. * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
  292. * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
  293. * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
  294. * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
  295. * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
  296. * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
  297. * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
  298. * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
  299. * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
  300. * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
  301. * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
  302. * @param Periphs This parameter can be a combination of the following values:
  303. * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
  304. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
  305. * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
  306. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  307. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
  308. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
  309. * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
  310. * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
  311. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  312. * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
  313. * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
  314. *
  315. * (*) value not defined in all devices.
  316. * @retval None
  317. */
  318. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
  319. {
  320. CLEAR_BIT(RCC->AHBENR, Periphs);
  321. }
  322. #if defined(RCC_AHBRSTR_SUPPORT)
  323. /**
  324. * @brief Force AHB1 peripherals reset.
  325. * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
  326. * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
  327. * @param Periphs This parameter can be a combination of the following values:
  328. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  329. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  330. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  331. *
  332. * (*) value not defined in all devices.
  333. * @retval None
  334. */
  335. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
  336. {
  337. SET_BIT(RCC->AHBRSTR, Periphs);
  338. }
  339. /**
  340. * @brief Release AHB1 peripherals reset.
  341. * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
  342. * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
  343. * @param Periphs This parameter can be a combination of the following values:
  344. * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
  345. * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
  346. * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
  347. *
  348. * (*) value not defined in all devices.
  349. * @retval None
  350. */
  351. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
  352. {
  353. CLEAR_BIT(RCC->AHBRSTR, Periphs);
  354. }
  355. #endif /* RCC_AHBRSTR_SUPPORT */
  356. /**
  357. * @}
  358. */
  359. /** @defgroup BUS_LL_EF_APB1 APB1
  360. * @{
  361. */
  362. /**
  363. * @brief Enable APB1 peripherals clock.
  364. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
  365. * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
  366. * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
  367. * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
  368. * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
  369. * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
  370. * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
  371. * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
  372. * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
  373. * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
  374. * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
  375. * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
  376. * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
  377. * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
  378. * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
  379. * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
  380. * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
  381. * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
  382. * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
  383. * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
  384. * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
  385. * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
  386. * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
  387. * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
  388. * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
  389. * @param Periphs This parameter can be a combination of the following values:
  390. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  391. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  392. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  393. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  394. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  395. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  396. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  397. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  398. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  399. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  400. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  401. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  402. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  403. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  404. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  405. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  406. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  407. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  408. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  409. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  410. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  411. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  412. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  413. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  414. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  415. *
  416. * (*) value not defined in all devices.
  417. * @retval None
  418. */
  419. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
  420. {
  421. __IO uint32_t tmpreg;
  422. SET_BIT(RCC->APB1ENR, Periphs);
  423. /* Delay after an RCC peripheral clock enabling */
  424. tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
  425. (void)tmpreg;
  426. }
  427. /**
  428. * @brief Check if APB1 peripheral clock is enabled or not
  429. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
  430. * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
  431. * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
  432. * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
  433. * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
  434. * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
  435. * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
  436. * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
  437. * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
  438. * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
  439. * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
  440. * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
  441. * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
  442. * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
  443. * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
  444. * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
  445. * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
  446. * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
  447. * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
  448. * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
  449. * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
  450. * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
  451. * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
  452. * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
  453. * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
  454. * @param Periphs This parameter can be a combination of the following values:
  455. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  456. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  457. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  458. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  459. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  460. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  461. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  462. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  463. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  464. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  465. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  466. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  467. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  468. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  469. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  470. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  471. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  472. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  473. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  474. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  475. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  476. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  477. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  478. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  479. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  480. *
  481. * (*) value not defined in all devices.
  482. * @retval State of Periphs (1 or 0).
  483. */
  484. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
  485. {
  486. return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
  487. }
  488. /**
  489. * @brief Disable APB1 peripherals clock.
  490. * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
  491. * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
  492. * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
  493. * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
  494. * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
  495. * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
  496. * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
  497. * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
  498. * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
  499. * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
  500. * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
  501. * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
  502. * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
  503. * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
  504. * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
  505. * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
  506. * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
  507. * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
  508. * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
  509. * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
  510. * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
  511. * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
  512. * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
  513. * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
  514. * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
  515. * @param Periphs This parameter can be a combination of the following values:
  516. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  517. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  518. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  519. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  520. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  521. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  522. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  523. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  524. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  525. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  526. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  527. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  528. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  529. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  530. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  531. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  532. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  533. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  534. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  535. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  536. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  537. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  538. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  539. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  540. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  541. *
  542. * (*) value not defined in all devices.
  543. * @retval None
  544. */
  545. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
  546. {
  547. CLEAR_BIT(RCC->APB1ENR, Periphs);
  548. }
  549. /**
  550. * @brief Force APB1 peripherals reset.
  551. * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
  552. * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
  553. * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
  554. * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
  555. * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
  556. * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
  557. * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
  558. * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
  559. * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
  560. * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
  561. * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
  562. * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
  563. * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
  564. * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
  565. * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
  566. * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
  567. * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
  568. * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
  569. * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
  570. * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
  571. * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
  572. * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
  573. * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
  574. * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
  575. * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
  576. * @param Periphs This parameter can be a combination of the following values:
  577. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  578. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  579. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  580. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  581. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  582. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  583. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  584. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  585. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  586. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  587. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  588. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  589. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  590. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  591. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  592. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  593. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  594. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  595. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  596. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  597. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  598. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  599. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  600. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  601. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  602. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  603. *
  604. * (*) value not defined in all devices.
  605. * @retval None
  606. */
  607. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
  608. {
  609. SET_BIT(RCC->APB1RSTR, Periphs);
  610. }
  611. /**
  612. * @brief Release APB1 peripherals reset.
  613. * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
  614. * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
  615. * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
  616. * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
  617. * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
  618. * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
  619. * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
  620. * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
  621. * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
  622. * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
  623. * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
  624. * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
  625. * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
  626. * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
  627. * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
  628. * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
  629. * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
  630. * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
  631. * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
  632. * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
  633. * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
  634. * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
  635. * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
  636. * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
  637. * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
  638. * @param Periphs This parameter can be a combination of the following values:
  639. * @arg @ref LL_APB1_GRP1_PERIPH_ALL
  640. * @arg @ref LL_APB1_GRP1_PERIPH_BKP
  641. * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
  642. * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
  643. * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
  644. * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
  645. * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
  646. * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
  647. * @arg @ref LL_APB1_GRP1_PERIPH_PWR
  648. * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
  649. * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
  650. * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
  651. * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
  652. * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
  653. * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
  654. * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
  655. * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
  656. * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
  657. * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
  658. * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
  659. * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
  660. * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
  661. * @arg @ref LL_APB1_GRP1_PERIPH_USART2
  662. * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
  663. * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
  664. * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
  665. *
  666. * (*) value not defined in all devices.
  667. * @retval None
  668. */
  669. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
  670. {
  671. CLEAR_BIT(RCC->APB1RSTR, Periphs);
  672. }
  673. /**
  674. * @}
  675. */
  676. /** @defgroup BUS_LL_EF_APB2 APB2
  677. * @{
  678. */
  679. /**
  680. * @brief Enable APB2 peripherals clock.
  681. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
  682. * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
  683. * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
  684. * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
  685. * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
  686. * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
  687. * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
  688. * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
  689. * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
  690. * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
  691. * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
  692. * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
  693. * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
  694. * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
  695. * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
  696. * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
  697. * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
  698. * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
  699. * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
  700. * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
  701. * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
  702. * @param Periphs This parameter can be a combination of the following values:
  703. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  704. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  705. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  706. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  707. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  708. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  709. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  710. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  711. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  712. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  713. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  714. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  715. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  716. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  717. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  718. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  719. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  720. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  721. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  722. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  723. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  724. *
  725. * (*) value not defined in all devices.
  726. * @retval None
  727. */
  728. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
  729. {
  730. __IO uint32_t tmpreg;
  731. SET_BIT(RCC->APB2ENR, Periphs);
  732. /* Delay after an RCC peripheral clock enabling */
  733. tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
  734. (void)tmpreg;
  735. }
  736. /**
  737. * @brief Check if APB2 peripheral clock is enabled or not
  738. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
  739. * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
  740. * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
  741. * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
  742. * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
  743. * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
  744. * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
  745. * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
  746. * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
  747. * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
  748. * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
  749. * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
  750. * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
  751. * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
  752. * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
  753. * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
  754. * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
  755. * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
  756. * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
  757. * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
  758. * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
  759. * @param Periphs This parameter can be a combination of the following values:
  760. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  761. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  762. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  763. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  764. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  765. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  766. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  767. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  768. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  769. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  770. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  771. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  772. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  773. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  774. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  775. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  776. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  777. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  778. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  779. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  780. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  781. *
  782. * (*) value not defined in all devices.
  783. * @retval State of Periphs (1 or 0).
  784. */
  785. __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
  786. {
  787. return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
  788. }
  789. /**
  790. * @brief Disable APB2 peripherals clock.
  791. * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
  792. * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
  793. * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
  794. * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
  795. * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
  796. * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
  797. * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
  798. * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
  799. * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
  800. * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
  801. * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
  802. * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
  803. * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
  804. * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
  805. * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
  806. * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
  807. * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
  808. * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
  809. * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
  810. * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
  811. * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
  812. * @param Periphs This parameter can be a combination of the following values:
  813. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  814. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  815. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  816. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  817. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  818. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  819. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  820. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  821. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  822. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  823. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  824. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  825. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  826. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  827. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  828. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  829. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  830. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  831. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  832. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  833. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  834. *
  835. * (*) value not defined in all devices.
  836. * @retval None
  837. */
  838. __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
  839. {
  840. CLEAR_BIT(RCC->APB2ENR, Periphs);
  841. }
  842. /**
  843. * @brief Force APB2 peripherals reset.
  844. * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
  845. * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
  846. * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
  847. * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
  848. * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
  849. * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
  850. * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
  851. * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
  852. * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
  853. * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
  854. * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
  855. * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
  856. * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
  857. * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
  858. * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
  859. * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
  860. * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
  861. * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
  862. * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
  863. * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
  864. * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
  865. * @param Periphs This parameter can be a combination of the following values:
  866. * @arg @ref LL_APB2_GRP1_PERIPH_ALL
  867. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  868. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  869. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  870. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  871. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  872. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  873. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  874. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  875. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  876. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  877. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  878. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  879. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  880. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  881. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  882. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  883. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  884. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  885. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  886. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  887. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  888. *
  889. * (*) value not defined in all devices.
  890. * @retval None
  891. */
  892. __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
  893. {
  894. SET_BIT(RCC->APB2RSTR, Periphs);
  895. }
  896. /**
  897. * @brief Release APB2 peripherals reset.
  898. * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
  899. * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
  900. * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
  901. * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
  902. * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
  903. * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
  904. * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
  905. * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
  906. * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
  907. * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
  908. * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
  909. * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
  910. * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
  911. * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
  912. * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
  913. * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
  914. * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
  915. * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
  916. * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
  917. * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
  918. * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
  919. * @param Periphs This parameter can be a combination of the following values:
  920. * @arg @ref LL_APB2_GRP1_PERIPH_ALL
  921. * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
  922. * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
  923. * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
  924. * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
  925. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
  926. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
  927. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
  928. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
  929. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
  930. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
  931. * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
  932. * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
  933. * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
  934. * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
  935. * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
  936. * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
  937. * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
  938. * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
  939. * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
  940. * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
  941. * @arg @ref LL_APB2_GRP1_PERIPH_USART1
  942. *
  943. * (*) value not defined in all devices.
  944. * @retval None
  945. */
  946. __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
  947. {
  948. CLEAR_BIT(RCC->APB2RSTR, Periphs);
  949. }
  950. /**
  951. * @}
  952. */
  953. /**
  954. * @}
  955. */
  956. /**
  957. * @}
  958. */
  959. #endif /* defined(RCC) */
  960. /**
  961. * @}
  962. */
  963. #ifdef __cplusplus
  964. }
  965. #endif
  966. #endif /* __STM32F1xx_LL_BUS_H */
  967. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/