91 lines
1.9 KiB
VHDL
91 lines
1.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY data_memory_test IS
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END data_memory_test;
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ARCHITECTURE behavior OF data_memory_test IS
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COMPONENT data_memory
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PORT(
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addr : IN std_logic_vector(7 downto 0);
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data : IN std_logic_vector(7 downto 0);
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rw : IN std_logic;
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rst : IN std_logic;
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clk : IN std_logic;
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q : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal addr : std_logic_vector(7 downto 0) := (others => '0');
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signal data : std_logic_vector(7 downto 0) := (others => '0');
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signal rw : std_logic := '0';
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signal rst : std_logic := '0';
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signal clk : std_logic := '0';
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--Outputs
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signal q : std_logic_vector(7 downto 0);
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: data_memory PORT MAP (
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addr => addr,
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data => data,
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rw => rw,
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rst => rst,
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clk => clk,
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q => q
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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addr <=
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"00000000",
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"00000010" after 1*CLK_period,
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"00000110" after 2*CLK_period,
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"00001000" after 3*CLK_period,
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"00001100" after 4*CLK_period,
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"00000000" after 5*CLK_period,
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"00000001" after 6*CLK_period,
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"00000010" after 8*CLK_period,
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"00000000" after 9*CLK_period,
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"00001111" after 11*CLK_period;
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DATA <=
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"01010101",
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"10101010" after 6*CLK_period,
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"00000000" after 7*CLK_period,
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"11111111" after 8*CLK_period,
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"00001111" after 10*CLK_period;
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rw <=
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'1',
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'0' after 5*CLK_period,
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'1' after 9*CLK_period,
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'0' after 10*CLK_period;
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RST <= '1' after clk_period, '0' after 12*CLK_period;
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wait;
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end process;
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END;
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