53 lines
911 B
VHDL
53 lines
911 B
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY CPU_test IS
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END CPU_test;
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ARCHITECTURE behavior OF CPU_test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT CPU
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PORT(
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clk : in STD_LOGIC;
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rst : IN std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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-- Clock period definitions
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constant clk_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: CPU PORT MAP (
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clk => clk,
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rst => rst
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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rst <= '1' after 2*clk_period;
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wait for 10*clk_period;
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wait;
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end process;
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END;
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