78 lines
1.6 KiB
VHDL
78 lines
1.6 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY ALU_test IS
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END ALU_test;
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ARCHITECTURE behavior OF ALU_test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT ALU
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PORT(
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A : IN std_logic_vector(7 downto 0);
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B : IN std_logic_vector(7 downto 0);
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S : OUT std_logic_vector(7 downto 0);
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O : OUT std_logic;
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Z : OUT std_logic;
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C : OUT std_logic;
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Ctrl : IN std_logic_vector(1 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal A : std_logic_vector(7 downto 0) := (others => '0');
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signal B : std_logic_vector(7 downto 0) := (others => '0');
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signal Ctrl : std_logic_vector(1 downto 0) := (others => '0');
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--Outputs
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signal S : std_logic_vector(7 downto 0);
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signal O : std_logic;
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signal Z : std_logic;
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signal C : std_logic;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: ALU PORT MAP (
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A => A,
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B => B,
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S => S,
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O => O,
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Z => Z,
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C => C,
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Ctrl => Ctrl
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);
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-- Stimulus process
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stim_proc: process
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begin
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A <=
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"00000001",
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"11111000" after 1 ms,
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"00000010" after 2 ms,
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"11001100" after 3 ms,
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"00000011" after 4 ms,
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"00000001" after 5 ms;
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B <=
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"00000011",
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"10000000" after 1 ms,
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"00000011" after 2 ms,
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"01100101" after 3 ms,
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"00000001" after 4 ms,
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"00000011" after 5 ms;
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Ctrl <=
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"01",
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"11" after 2 ms,
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"10" after 4 ms,
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"00" after 6 ms,
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"00" after 7 ms;
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wait;
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end process;
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END;
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