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instruction_memory.vhd 1.7KB

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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4. entity instruction_memory is
  5. Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
  6. q : out STD_LOGIC_VECTOR (31 downto 0);
  7. clk : in STD_LOGIC);
  8. end instruction_memory;
  9. architecture Behavioral of instruction_memory is
  10. constant NOP : std_logic_vector(7 downto 0) := "00000000";
  11. constant ADD : std_logic_vector(7 downto 0) := "00000001";
  12. constant MUL : std_logic_vector(7 downto 0) := "00000010";
  13. constant SOU : std_logic_vector(7 downto 0) := "00000011";
  14. constant DIV : std_logic_vector(7 downto 0) := "00000100";
  15. constant COP : std_logic_vector(7 downto 0) := "00000101";
  16. constant AFC : std_logic_vector(7 downto 0) := "00000110";
  17. constant LOAD : std_logic_vector(7 downto 0) := "00000111";
  18. constant STORE: std_logic_vector(7 downto 0) := "00001000";
  19. type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
  20. signal memory: MEMORY_TYPE := (
  21. 1 => AFC & "00000001" & "00000010" & "00000000", -- r1 <= 2
  22. 2 => COP & "00000011" & "00000001" & "00000000", -- r3 <= r1 (= 2)
  23. 3 => ADD & "00000100" & "00000001" & "00000011", -- 2 + 2 = 4 dans R4
  24. 4 => MUL & "00000101" & "00000100" & "00000001", -- 4 * 2 = 8 dans R5
  25. 5 => SOU & "00000010" & "00000101" & "00000100", -- 8 - 4 = 4 dans R2
  26. 6 => STORE & "00001000" & "00000010" & "00000000", -- store R2 (4) at address 8
  27. 7 => STORE & "00010100" & "00000101" & "00000000", -- store R5 (8) at address 20
  28. 8 => LOAD & "00000111" & "00001000" & "00000000", -- load mem@8 (4) in R7
  29. 9 => LOAD & "00001000" & "00010100" & "00000000", -- load mem@20 (8) in R8
  30. others => (others => '0'));
  31. begin
  32. q <= memory(to_integer(unsigned(addr)));
  33. end Behavioral;