processor-2000/instruction_memory.vhd
2021-05-10 10:39:57 +02:00

37 lines
1.7 KiB
VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity instruction_memory is
Port ( addr : in STD_LOGIC_VECTOR (7 downto 0);
q : out STD_LOGIC_VECTOR (31 downto 0);
clk : in STD_LOGIC);
end instruction_memory;
architecture Behavioral of instruction_memory is
constant NOP : std_logic_vector(7 downto 0) := "00000000";
constant ADD : std_logic_vector(7 downto 0) := "00000001";
constant MUL : std_logic_vector(7 downto 0) := "00000010";
constant SOU : std_logic_vector(7 downto 0) := "00000011";
constant DIV : std_logic_vector(7 downto 0) := "00000100";
constant COP : std_logic_vector(7 downto 0) := "00000101";
constant AFC : std_logic_vector(7 downto 0) := "00000110";
constant LOAD : std_logic_vector(7 downto 0) := "00000111";
constant STORE: std_logic_vector(7 downto 0) := "00001000";
type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
signal memory: MEMORY_TYPE := (
1 => AFC & "00000001" & "00000010" & "00000000", -- r1 <= 2
2 => COP & "00000011" & "00000001" & "00000000", -- r3 <= r1 (= 2)
3 => ADD & "00000100" & "00000001" & "00000011", -- 2 + 2 = 4 dans R4
4 => MUL & "00000101" & "00000100" & "00000001", -- 4 * 2 = 8 dans R5
5 => SOU & "00000010" & "00000101" & "00000100", -- 8 - 4 = 4 dans R2
6 => STORE & "00001000" & "00000010" & "00000000", -- store R2 (4) at address 8
7 => STORE & "00010100" & "00000101" & "00000000", -- store R5 (8) at address 20
8 => LOAD & "00000111" & "00001000" & "00000000", -- load mem@8 (4) in R7
9 => LOAD & "00001000" & "00010100" & "00000000", -- load mem@20 (8) in R8
others => (others => '0'));
begin
q <= memory(to_integer(unsigned(addr)));
end Behavioral;