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compare: ysimard:fd03450f1cc223eb057488ae952c40d5847d8cc6
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b96be573b4 ... fd03450f1c

Author SHA1 Message Date
Simard Yohan
fd03450f1c Add all instructions support + bubbles (wip) 2021-05-04 15:29:08 +02:00
6 changed files with 119 additions and 56 deletions
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4
.gitignore vendored
View file

@ -6,3 +6,7 @@
# Except vhdl files # Except vhdl files
!.gitignore !.gitignore
!*.vhd !*.vhd
# and simulation config files
!*.wcfg

18
ALU.vhd
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@ -14,6 +14,10 @@ entity ALU is
end ALU; end ALU;
architecture Behavioral of ALU is architecture Behavioral of ALU is
constant Ctrl_ADD : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant Ctrl_MUL : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant Ctrl_SOU : STD_LOGIC_VECTOR (1 downto 0) := "11";
SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0); SIGNAL aux : STD_LOGIC_VECTOR (7 downto 0);
SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0); SIGNAL A9 : STD_LOGIC_VECTOR (8 downto 0);
SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0); SIGNAL B9 : STD_LOGIC_VECTOR (8 downto 0);
@ -26,15 +30,15 @@ begin
ADD <= A9 + B9; ADD <= A9 + B9;
SUB <= A9 - B9; SUB <= A9 - B9;
MUL <= A * B; MUL <= A * B;
aux <= ADD(7 downto 0) when Ctrl = "01" else aux <= ADD(7 downto 0) when Ctrl = Ctrl_ADD else
SUB(7 downto 0) when Ctrl = "10" else SUB(7 downto 0) when Ctrl = Ctrl_SOU else
MUL(7 downto 0) when Ctrl = "11" else MUL(7 downto 0) when Ctrl = Ctrl_MUL else
(others => '0'); (others => '0');
O <= ADD(8) when Ctrl = "01" else O <= ADD(8) when Ctrl = Ctrl_ADD else
'0' when Ctrl = "11" and MUL(15 downto 8) = "00000000" else '0' when Ctrl = Ctrl_MUL and MUL(15 downto 8) = "00000000" else
'1' when Ctrl = "11" else '1' when Ctrl = Ctrl_MUL else
'0'; '0';
C <= ADD(8) when Ctrl = "01" else '0'; C <= ADD(8) when Ctrl = Ctrl_ADD else '0';
Z <= '1' when aux = "00000000" else '0'; Z <= '1' when aux = "00000000" else '0';
S <= aux; S <= aux;
end Behavioral; end Behavioral;

84
CPU.vhd
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@ -1,6 +1,7 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL; use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CPU is entity CPU is
Port ( Port (
@ -10,8 +11,20 @@ entity CPU is
end CPU; end CPU;
architecture Behavioral of CPU is architecture Behavioral of CPU is
constant NOP : std_logic_vector(7 downto 0) := "00000000";
constant ADD : std_logic_vector(7 downto 0) := "00000001";
constant MUL : std_logic_vector(7 downto 0) := "00000010";
constant SOU : std_logic_vector(7 downto 0) := "00000011";
constant DIV : std_logic_vector(7 downto 0) := "00000100";
constant COP : std_logic_vector(7 downto 0) := "00000101";
constant AFC : std_logic_vector(7 downto 0) := "00000110"; constant AFC : std_logic_vector(7 downto 0) := "00000110";
constant HALT : std_logic_vector(7 downto 0) := "00000000"; constant LOAD : std_logic_vector(7 downto 0) := "00000111";
constant STORE: std_logic_vector(7 downto 0) := "00001000";
-- constant HALT : std_logic_vector(7 downto 0) := "00001001";
constant MX1: std_logic_vector(8 downto 0) := "100111110";
constant MX2: std_logic_vector(8 downto 0) := "000011110";
constant needBubbles: std_logic_vector(8 downto 0) := "111111110";
COMPONENT ALU COMPONENT ALU
PORT( PORT(
@ -73,7 +86,7 @@ architecture Behavioral of CPU is
signal registers_addr_A : std_logic_vector(3 downto 0); signal registers_addr_A : std_logic_vector(3 downto 0);
signal registers_addr_B : std_logic_vector(3 downto 0); signal registers_addr_B : std_logic_vector(3 downto 0);
signal registers_addr_W : std_logic_vector(3 downto 0); signal registers_addr_W : std_logic_vector(3 downto 0);
signal registers_W : std_logic; signal registers_W : std_logic := '0';
signal registers_DATA : std_logic_vector(7 downto 0); signal registers_DATA : std_logic_vector(7 downto 0);
signal registers_QA : std_logic_vector(7 downto 0); signal registers_QA : std_logic_vector(7 downto 0);
signal registers_QB : std_logic_vector(7 downto 0); signal registers_QB : std_logic_vector(7 downto 0);
@ -109,8 +122,7 @@ architecture Behavioral of CPU is
signal A4 : STD_LOGIC_VECTOR(7 downto 0); signal A4 : STD_LOGIC_VECTOR(7 downto 0);
signal B4 : STD_LOGIC_VECTOR(7 downto 0); signal B4 : STD_LOGIC_VECTOR(7 downto 0);
-- Etage 5 signal bubble : integer := 2;
begin begin
myalu: ALU PORT MAP ( myalu: ALU PORT MAP (
@ -150,47 +162,71 @@ begin
clk => clk clk => clk
); );
instr_memory_addr <= IP;
registers_addr_W <= A4(3 downto 0);
registers_W <= '0' when (OP4 = NOP or OP4 = STORE) else '1';
registers_data <= B4;
registers_addr_A <= B1(3 downto 0);
registers_addr_B <= C1(3 downto 0);
ALU_A <= B2;
ALU_B <= C2;
ALU_Ctrl <= OP2(1 downto 0);
data_memory_RW <= '0' when (OP3 = STORE) else '1';
data_memory_addr <= A3 when (OP3 = STORE) else B3;
data_memory_data <= B3;
process process
begin begin
wait until CLK'event and CLK='1'; wait until CLK'event and CLK='1';
if (halted = '0') then if (halted = '0') then
-- Etage 5 -- Etage 3 -> 4
registers_addr_W <= A4(3 downto 0);
if OP4 = AFC then
registers_W <= '1';
elsif OP4 = HALT then
halted <= '1';
else
registers_W <= '0';
end if;
registers_data <= B4;
-- Etage 4
OP4 <= OP3; OP4 <= OP3;
A4 <= A3; A4 <= A3;
if (OP3 = LOAD) then
B4 <= data_memory_Q;
else
B4 <= B3; B4 <= B3;
end if;
-- Etage 3 -- Etage 2 -> 3
OP3 <= OP2; OP3 <= OP2;
A3 <= A2; A3 <= A2;
if (MX2(to_integer(unsigned(OP2))) = '1') then
B3 <= ALU_S;
else
B3 <= B2; B3 <= B2;
end if;
-- Etage 2 -- Etage 1 -> 2
OP2 <= OP1; OP2 <= OP1;
A2 <= A1; A2 <= A1;
if (MX1(to_integer(unsigned(OP1))) = '1') then
B2 <= registers_QA;
else
B2 <= B1; B2 <= B1;
C2 <= C1; end if;
C2 <= registers_QB;
-- Memoire -> etage 1
-- Etage 1 if (bubble = 0) then
instr_memory_addr <= IP;
C1 <= instr_memory_q(7 downto 0); C1 <= instr_memory_q(7 downto 0);
B1 <= instr_memory_q(15 downto 8); B1 <= instr_memory_q(15 downto 8);
A1 <= instr_memory_q(23 downto 16); A1 <= instr_memory_q(23 downto 16);
OP1 <= instr_memory_q(31 downto 24); OP1 <= instr_memory_q(31 downto 24);
IP <= IP + 1;
-- IP <= IP + 1; if (needBubbles(to_integer(unsigned(instr_memory_q(31 downto 24)))) = '1') then
bubble <= 3;
end if;
else
C1 <= "00000000";
B1 <= "00000000";
A1 <= "00000000";
OP1 <= NOP;
bubble <= bubble - 1;
end if;
end if; end if;
end process; end process;

21
config_simu.wcfg
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@ -26,21 +26,20 @@
<obj_property name="ElementShortName">clk_period</obj_property> <obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property> <obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject> </wvobject>
<wvobject fp_name="group7" type="group"> <wvobject fp_name="/cpu_test/uut/ip" type="array" db_ref_id="1">
<obj_property name="label">Instruction</obj_property> <obj_property name="ElementShortName">ip[7:0]</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="ObjectShortName">ip[7:0]</obj_property>
<wvobject fp_name="/cpu_test/uut/instr_memory_addr" type="array" db_ref_id="1"> <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
<obj_property name="ElementShortName">instr_memory_addr[7:0]</obj_property>
<obj_property name="ObjectShortName">instr_memory_addr[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/instr_memory_q" type="array" db_ref_id="1">
<obj_property name="ElementShortName">instr_memory_q[31:0]</obj_property>
<obj_property name="ObjectShortName">instr_memory_q[31:0]</obj_property>
</wvobject>
</wvobject> </wvobject>
<wvobject fp_name="group39" type="group"> <wvobject fp_name="group39" type="group">
<obj_property name="label">etage 1</obj_property> <obj_property name="label">etage 1</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<wvobject fp_name="/cpu_test/uut/bubble" type="other" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">bubble</obj_property>
<obj_property name="ObjectShortName">bubble</obj_property>
<obj_property name="label">bubble</obj_property>
</wvobject>
<wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1"> <wvobject fp_name="/cpu_test/uut/op1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">op1[7:0]</obj_property> <obj_property name="ElementShortName">op1[7:0]</obj_property>
<obj_property name="ObjectShortName">op1[7:0]</obj_property> <obj_property name="ObjectShortName">op1[7:0]</obj_property>

6
data_memory.vhd
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@ -22,9 +22,9 @@ begin
memory <= (others => (others => '0')); memory <= (others => (others => '0'));
elsif (rw = '0') then elsif (rw = '0') then
memory(to_integer(unsigned(addr))) <= data; memory(to_integer(unsigned(addr))) <= data;
else
q <= memory(to_integer(unsigned(addr)));
end if; end if;
end process; end process;
end Behavioral;
q <= memory(to_integer(unsigned(addr)));
end Behavioral;

22
instruction_memory.vhd
View file

@ -9,8 +9,28 @@ entity instruction_memory is
end instruction_memory; end instruction_memory;
architecture Behavioral of instruction_memory is architecture Behavioral of instruction_memory is
constant NOP : std_logic_vector(7 downto 0) := "00000000";
constant ADD : std_logic_vector(7 downto 0) := "00000001";
constant MUL : std_logic_vector(7 downto 0) := "00000010";
constant SOU : std_logic_vector(7 downto 0) := "00000011";
constant DIV : std_logic_vector(7 downto 0) := "00000100";
constant COP : std_logic_vector(7 downto 0) := "00000101";
constant AFC : std_logic_vector(7 downto 0) := "00000110";
constant LOAD : std_logic_vector(7 downto 0) := "00000111";
constant STORE: std_logic_vector(7 downto 0) := "00001000";
type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0); type MEMORY_TYPE is array (256 downto 0) of std_logic_vector(31 downto 0);
signal memory: MEMORY_TYPE := (0 => "00000110000000010000001000000000", others => (others => '0')); signal memory: MEMORY_TYPE := (
1 => AFC & "00000001" & "00000010" & "00000000", -- r1 <= 2
2 => COP & "00000011" & "00000001" & "00000000", -- r3 <= r1 (= 2)
3 => ADD & "00000100" & "00000001" & "00000011", -- 2 + 2 = 4 dans R4
4 => MUL & "00000101" & "00000100" & "00000001", -- 4 * 2 = 8 dans R5
5 => SOU & "00000010" & "00000101" & "00000100", -- 8 - 4 = 4 dans R2
6 => STORE & "00001000" & "00000010" & "00000000", -- store R2 (4) at address 8
7 => STORE & "00010100" & "00000101" & "00000000", -- store R5 (8) at address 20
8 => LOAD & "00000111" & "00001000" & "00000000", -- load mem@8 (4) in R7
9 => LOAD & "00001000" & "00010100" & "00000000", -- load mem@20 (8) in R8
others => (others => '0'));
begin begin
process process
begin begin