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108
Article_Scientifique/main.tex
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@ -179,7 +179,8 @@ carries higher hardware costs (sensors, processing power).
FOC provides faster response times and better load disturbance rejection \cite{jomsa-nga_torque_2024}. FOC provides faster response times and better load disturbance rejection \cite{jomsa-nga_torque_2024}.
\section{Research gap}
\section{Research Gap}
The literature presented in the previous sections shows that significant work has been carried out on BLDC The literature presented in the previous sections shows that significant work has been carried out on BLDC
motor control strategies, especially for torque ripple reduction, efficiency improvement, and dynamic performance motor control strategies, especially for torque ripple reduction, efficiency improvement, and dynamic performance
@ -247,7 +248,7 @@ assistance based on system dynamics.
Table~\ref{tab:foc_vs_trap} summarizes the key differences between the Table~\ref{tab:foc_vs_trap} summarizes the key differences between the
two commutation strategies, based on the literature reviewed in two commutation strategies, based on the literature reviewed in
Section~\ref{sec:relatedwork}. Section~\ref{sec:related}.
\begin{table}[htbp] \begin{table}[htbp]
\caption{Comparison between FOC and trapezoidal (six-step) commutation} \caption{Comparison between FOC and trapezoidal (six-step) commutation}
@ -310,73 +311,82 @@ assistance based on system dynamics.
\subsection{Pin Compatibility Verification: L476 vs F405} \subsection{Pin Compatibility Verification: L476 vs F405}
Before modifying the PCB, a thorough pin compatibility check was Before starting the PCB modifications, a pin compatibility study was carried out between the STM32L476
performed between the STM32L476 and the STM32F405 used on the Rocacher tile and the STM32F405 originally used in the Cheap FOCer-2 design. The objective
(original Cheap FOCer-2 design). The following aspects were examined: was to verify that the main functions required by the VESC firmware could still be used after replacing
the original microcontroller.
The verification mainly focused on:
\begin{itemize} \begin{itemize}
\item Physical pinout in LQFP64 package. \item Physical pinout compatibility in the LQFP64 package,
\item Alternate functions for PWM timers. \item PWM timer for Alternate functions,
\item USB DP/DM pins (PA11/PA12). \item USB DP/DM pins (PA11/PA12),
\item Analog inputs for current sensing. \item Analog inputs for current sensing,
\item UART for BLE communication. \item UART communication for BLE integration.
\end{itemize} \end{itemize}
Three pin conflicts were identified and resolved as follows. During this analysis, three main pin conflicts were identified.
First, the SPI\_MISO function on PA6 for the STM32F405 conflicts with a The first conflict concerned the SPI\_MISO signal on pin PA6. In the original STM32F405 design, this pin is
DAC output on the same pin for the STM32L476 tile. Since this pin is used for SPI communication related to current sensing. On the STM32L476 tile, the same pin is associated with
used for current sensing via SPI in the original Cheap FOCer-2 design, a DAC output, creating a functional conflict. To solve this issue, the SPI communication line was remapped
the SPI communication was remapped to PA5 on the L476, which provides a to PA5 on the L476, which offers a compatible alternate function.
compatible alternate function.
Second, the gate driver enable signal (EN\_GATE) was originally assigned The second issue concerned the EN\_GATE signal. In the original design, this signal was connected to PB5 on
to PB5 on the F405. This pin is not accessible on the L476 the STM32F405. However, this pin is not accessible on the L476 tile. The signal was therefore moved to PC5,
tile. The signal was therefore moved to PC5, which is available and configured as a standard GPIO output.
can be configured as a standard GPIO output.
Third, Hall sensor C was originally connected to PC8 (TIM8) on the F405. Finally, Hall sensor C was originally connected to PC8 (TIM8) on the STM32F405. Since this pin is not available
This pin is not available on the L476 tile. The Hall sensor input was on the tile connector, the Hall sensor input was reassigned to PB3 using the TIM2\_CH2 alternate function,
therefore reassigned to PB3, configured as TIM2\_CH2, which provides which preserves the input capture capability required for Hall sensor decoding.
the necessary input capture functionality for Hall signal decoding.
All other critical functions (PWM timers, complementary PWM, enable All other important functions remained compatible between the two microcontrollers, including PWM generation,
signals, encoder inputs, UART, USB, and CAN) remain fully compatible complementary PWM outputs, encoder inputs, UART, USB, and CAN communication. Some differences between the ADC
between the two microcontrollers. The ADC channel differences between peripherals of the STM32F405 and STM32L476 still remain and will require firmware adaptations in future work.
the F405 (ADC123/ADC12) and the L476 (ADC3) must still be handled in
firmware, as noted previously.
\subsection{Schematic Design and KiCad Implementation} \subsection{Schematic Design and KiCad Implementation}
The original Cheap FOCer-2 schematic was modified in KiCad to replace the The original Cheap FOCer-2 schematic was modified in KiCad in order to replace the integrated STM32F405
integrated F405 with connectors for the L476 tile. The main modifications microcontroller with connectors for the Rocacher STM32L476 tile. The objective was to make the control part more
included: modular and easier to replace without modifying the power stage of the board.
The main modifications performed on the schematic were:
\begin{itemize} \begin{itemize}
\item Removal of the F405 and its associated passive components. \item Removal of the STM32F405 and its associated passive components.
\item Addition of two 20-pin headers to receive the Rocacher tile. \item Addition of two 20-pin headers for the L476 tile connection.
\item Re-routing of PWM, ADC, and USB signals to the headers. \item Re-routing of PWM, ADC, USB, and communication signals toward the headers.
\end{itemize} \end{itemize}
The schematic passed Electrical Rule Check (ERC) with no errors. Special attention was given to the routing of critical control signals, especially the PWM outputs used for
motor commutation and the analog signals used for current sensing.
After the modifications, the schematic was verified using the KiCad Electrical Rule Check (ERC). No electrical
errors were detected during this verification step, which validated the consistency of the schematic before
starting the PCB routing phase.
\subsection{Routing Challenges and Current Status} \subsection{Routing Challenges and Current Status}
The PCB layout was then started. The original Cheap FOCer-2 routing is After validating the schematic, the PCB routing phase was started in KiCad. The original Cheap FOCer-2 board
very dense. Inserting connectors for the removable tile while maintaining signal integrity proved uses a very compact layout with dense routing around the STM32F405 microcontroller and the power stage.
difficult. Integrating connectors for a removable STM32L476 tile introduced several additional routing constraints.
The main issues encountered were: One of the main difficulties was maintaining proper signal routing while keeping enough space for the tile
connectors and preserving the integrity of the control signals. Particular attention had to be given to the PWM
signals, current sensing traces, and power connections.
Several issues were encountered during the routing process:
\begin{itemize} \begin{itemize}
\item Some footprints for the tile connectors did not appear correctly \item Some connector footprints associated with the tile did not appear correctly after importing the schematic
in the layout after schematic import. into the PCB layout.
\item Routing of high-current paths (battery, motor phases) around the \item The routing of high-current paths, especially the battery and motor phase connections, become more complex
connectors required additional vias, increasing resistance. due to the additional connectors and required extra vias.
\item Decoupling capacitors had to be repositioned, raising concerns \item Some Decoupling capacitors had to be repositioned, which could potentially affect switching noise and power
about switching noise. supply stability.
\end{itemize} \end{itemize}
Currently, the schematic is validated, and the layout is under At the current stage of the project, the schematic has been validated and the PCB layout is still under development.
development. Once routing is completed, the board will be manufactured Once the routing is completed, the board will be manufactured and tested using the VESC firmware adapted for the
and tested with the VESC firmware adapted to the L476 tile. STM32L476 tile.
% ************************************** SOFTWARE AND CONNECTIVITY ***************************************************** % ************************************** SOFTWARE AND CONNECTIVITY *****************************************************