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Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/usage_statistics_webtalk.html
Lacroix Raphael b3d75a1a46 Fixed typos
2023-05-31 18:38:35 +02:00

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<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
<TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2258646</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed May 31 17:58:23 2023</TD>
<TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>LIN64</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.2 (64-bit)</TD>
<TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>aef36ef3a0d94dac9e6058b656907afd</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>12</TD>
<TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>6ef722b6-53ec-42dc-bc5c-9d79054a9923</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>6ef722b6-53ec-42dc-bc5c-9d79054a9923</TD>
<TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
<TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>cpg236</TD>
<TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-9500 CPU @ 3.00GHz</TD>
<TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3000.000 MHz</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Ubuntu</TD>
<TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>Ubuntu 20.04.6 LTS</TD>
</TR><TR ALIGN='LEFT'> <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
<TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>abstractcombinedpanel_add_element=36</TD>
<TD>abstractcombinedpanel_remove_selected_elements=13</TD>
<TD>abstractfileview_close=1</TD>
<TD>abstractfileview_reload=1</TD>
</TR><TR ALIGN='LEFT'> <TD>addsrcwizard_specify_hdl_netlist_block_design=1</TD>
<TD>addsrcwizard_specify_or_create_constraint_files=4</TD>
<TD>addsrcwizard_specify_simulation_specific_hdl_files=3</TD>
<TD>basedialog_apply=2</TD>
</TR><TR ALIGN='LEFT'> <TD>basedialog_cancel=31</TD>
<TD>basedialog_no=2</TD>
<TD>basedialog_ok=234</TD>
<TD>basedialog_yes=40</TD>
</TR><TR ALIGN='LEFT'> <TD>clockcreationpanel_clock_name=1</TD>
<TD>clockcreationpanel_enter_positive_number=5</TD>
<TD>cmdmsgdialog_messages=6</TD>
<TD>cmdmsgdialog_ok=33</TD>
</TR><TR ALIGN='LEFT'> <TD>cmdmsgdialog_open_messages_view=1</TD>
<TD>combinationalconstraintstablepanel_table=1</TD>
<TD>commandsinput_type_tcl_command_here=4</TD>
<TD>constraintschooserpanel_add_existing_or_create_new_constraints=5</TD>
</TR><TR ALIGN='LEFT'> <TD>constraintschooserpanel_add_files=4</TD>
<TD>constraintschooserpanel_create_file=4</TD>
<TD>constraintschooserpanel_file_table=2</TD>
<TD>createconstraintsfilepanel_file_name=3</TD>
</TR><TR ALIGN='LEFT'> <TD>createrunreportdialog_report_name=1</TD>
<TD>createsrcfiledialog_file_name=15</TD>
<TD>createsrcfiledialog_file_type=1</TD>
<TD>definemodulesdialog_define_modules_and_specify_io_ports=148</TD>
</TR><TR ALIGN='LEFT'> <TD>definemodulesdialog_entity_name=3</TD>
<TD>editcreateclocktablepanel_edit_create_clock_table=13</TD>
<TD>expreporttreepanel_edit_report_options=1</TD>
<TD>expreporttreepanel_exp_report_tree_table=9</TD>
</TR><TR ALIGN='LEFT'> <TD>expruntreepanel_exp_run_tree_table=2</TD>
<TD>filesetpanel_file_set_panel_tree=606</TD>
<TD>filesetpanel_messages=1</TD>
<TD>flownavigatortreepanel_flow_navigator_tree=374</TD>
</TR><TR ALIGN='LEFT'> <TD>gettingstartedview_create_new_project=1</TD>
<TD>gettingstartedview_open_project=3</TD>
<TD>graphicalview_zoom_fit=6</TD>
<TD>graphicalview_zoom_in=135</TD>
</TR><TR ALIGN='LEFT'> <TD>graphicalview_zoom_out=149</TD>
<TD>hcodeeditor_close=2</TD>
<TD>hcodeeditor_search_text_combo_box=40</TD>
<TD>hinputhandler_toggle_line_comments=1</TD>
</TR><TR ALIGN='LEFT'> <TD>hpopuptitle_close=1</TD>
<TD>inputoutputtablepanel_table=1</TD>
<TD>logmonitor_monitor=1</TD>
<TD>logpanel_copy=1</TD>
</TR><TR ALIGN='LEFT'> <TD>logpanel_find=1</TD>
<TD>logpanel_pause_output=2</TD>
<TD>logpanel_toggle_column_selection_mode=2</TD>
<TD>mainmenumgr_checkpoint=18</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_edit=16</TD>
<TD>mainmenumgr_export=7</TD>
<TD>mainmenumgr_file=76</TD>
<TD>mainmenumgr_flow=10</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_io_planning=1</TD>
<TD>mainmenumgr_ip=12</TD>
<TD>mainmenumgr_open_recent_project=25</TD>
<TD>mainmenumgr_project=51</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_reports=12</TD>
<TD>mainmenumgr_settings=2</TD>
<TD>mainmenumgr_simulation_waveform=15</TD>
<TD>mainmenumgr_text_editor=10</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_timing=1</TD>
<TD>mainmenumgr_tools=16</TD>
<TD>mainmenumgr_unselect_type=1</TD>
<TD>mainmenumgr_view=8</TD>
</TR><TR ALIGN='LEFT'> <TD>mainmenumgr_window=16</TD>
<TD>maintoolbarmgr_run=7</TD>
<TD>mainwinmenumgr_layout=12</TD>
<TD>mainwinmenumgr_load=1</TD>
</TR><TR ALIGN='LEFT'> <TD>messagewithoptiondialog_dont_show_this_dialog_again=1</TD>
<TD>msgtreepanel_message_severity=1</TD>
<TD>msgtreepanel_message_view_tree=172</TD>
<TD>msgview_clear_messages_resulting_from_user_executed=9</TD>
</TR><TR ALIGN='LEFT'> <TD>msgview_critical_warnings=2</TD>
<TD>msgview_error_messages=2</TD>
<TD>msgview_information_messages=3</TD>
<TD>msgview_warning_messages=1</TD>
</TR><TR ALIGN='LEFT'> <TD>navigabletimingreporttab_timing_report_navigation_tree=5</TD>
<TD>numjobschooser_number_of_jobs=2</TD>
<TD>openfileaction_cancel=2</TD>
<TD>openfileaction_open_directory=4</TD>
</TR><TR ALIGN='LEFT'> <TD>opentargetwizard_connect_to=3</TD>
<TD>packagetreepanel_package_tree_panel=5</TD>
<TD>pacommandnames_add_config_memory=3</TD>
<TD>pacommandnames_add_sources=21</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_auto_connect_target=2</TD>
<TD>pacommandnames_auto_update_hier=26</TD>
<TD>pacommandnames_fileset_window=3</TD>
<TD>pacommandnames_goto_instantiation=1</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_log_window=10</TD>
<TD>pacommandnames_open_project=1</TD>
<TD>pacommandnames_open_recent_target=3</TD>
<TD>pacommandnames_open_target_wizard=4</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_program_fpga=4</TD>
<TD>pacommandnames_report_clock_networks=1</TD>
<TD>pacommandnames_reports_window=5</TD>
<TD>pacommandnames_run_bitgen=1</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_run_synthesis=3</TD>
<TD>pacommandnames_set_as_top=6</TD>
<TD>pacommandnames_set_target_ucf=3</TD>
<TD>pacommandnames_simulation_relaunch=5</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_simulation_reset=1</TD>
<TD>pacommandnames_simulation_run=1</TD>
<TD>pacommandnames_simulation_run_behavioral=174</TD>
<TD>pacommandnames_simulation_run_post_synthesis_functional=1</TD>
</TR><TR ALIGN='LEFT'> <TD>pacommandnames_simulation_settings=9</TD>
<TD>pacommandnames_src_replace_file=5</TD>
<TD>paviews_code=41</TD>
<TD>paviews_device=3</TD>
</TR><TR ALIGN='LEFT'> <TD>paviews_project_summary=2</TD>
<TD>planaheadtab_show_flow_navigator=4</TD>
<TD>primaryclockspanel_recommended_constraints_table=6</TD>
<TD>programdebugtab_open_recently_opened_target=13</TD>
</TR><TR ALIGN='LEFT'> <TD>programdebugtab_open_target=2</TD>
<TD>programdebugtab_refresh_device=1</TD>
<TD>programfpgadialog_check_end_of_startup=1</TD>
<TD>programfpgadialog_program=12</TD>
</TR><TR ALIGN='LEFT'> <TD>programfpgadialog_specify_bitstream_file=2</TD>
<TD>progressdialog_background=16</TD>
<TD>progressdialog_cancel=1</TD>
<TD>projectsettingsgadget_edit_project_settings=2</TD>
</TR><TR ALIGN='LEFT'> <TD>projectsettingssimulationpanel_select_testbench_top_module=2</TD>
<TD>projectsettingssimulationpanel_tabbed_pane=7</TD>
<TD>projecttab_close_design=4</TD>
<TD>projecttab_reload=7</TD>
</TR><TR ALIGN='LEFT'> <TD>rdicommands_custom_commands=4</TD>
<TD>rdicommands_delete=5</TD>
<TD>rdicommands_line_comment=23</TD>
<TD>rdicommands_save_file=10</TD>
</TR><TR ALIGN='LEFT'> <TD>rdiviews_waveform_viewer=787</TD>
<TD>removesourcesdialog_also_delete=1</TD>
<TD>reportnavigationholder_rerun=2</TD>
<TD>rtloptionspanel_select_top_module_of_your_design=2</TD>
</TR><TR ALIGN='LEFT'> <TD>rungadget_show_error_and_critical_warning_messages=1</TD>
<TD>saveprojectutils_cancel=1</TD>
<TD>saveprojectutils_save=46</TD>
<TD>selecttopmoduledialog_select_top_module=8</TD>
</TR><TR ALIGN='LEFT'> <TD>settingsdialog_project_tree=1</TD>
<TD>signaltreepanel_signal_tree_table=13</TD>
<TD>simulationobjectspanel_simulation_objects_tree_table=55</TD>
<TD>simulationscopespanel_simulate_scope_table=80</TD>
</TR><TR ALIGN='LEFT'> <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=4</TD>
<TD>srcchooserpanel_add_or_create_source_file=21</TD>
<TD>srcchooserpanel_create_file=15</TD>
<TD>srcchoosertable_src_chooser_table=2</TD>
</TR><TR ALIGN='LEFT'> <TD>srcmenu_ip_hierarchy=26</TD>
<TD>srcmenu_refresh_hierarchy=2</TD>
<TD>stalerundialog_yes=2</TD>
<TD>statemonitor_reset_run=3</TD>
</TR><TR ALIGN='LEFT'> <TD>syntheticagettingstartedview_recent_projects=8</TD>
<TD>syntheticastatemonitor_cancel=8</TD>
<TD>taskbanner_close=6</TD>
<TD>tclconsoleview_clear_all_output_in_tcl_console=3</TD>
</TR><TR ALIGN='LEFT'> <TD>tclconsoleview_tcl_console_code_editor=50</TD>
<TD>timingconstraintswizard_create_check_timing_report=6</TD>
<TD>timingconstraintswizard_create_methodology_report=2</TD>
<TD>timingconstraintswizard_create_timing_summary_report=6</TD>
</TR><TR ALIGN='LEFT'> <TD>timingconstraintswizard_goto_constraints_summary_page=4</TD>
<TD>timingconstraintswizard_view_timing_constraints=6</TD>
<TD>touchpointsurveydialog_no=1</TD>
<TD>waveformnametree_waveform_name_tree=275</TD>
</TR><TR ALIGN='LEFT'> <TD>waveformoptionsview_reset_to_defaults=1</TD>
<TD>waveformoptionsview_show_signal_indices=4</TD>
<TD>waveformview_add_marker=4</TD>
<TD>waveformview_goto_last_time=4</TD>
</TR><TR ALIGN='LEFT'> <TD>waveformview_goto_time_0=3</TD>
<TD>waveformview_next_marker=3</TD>
<TD>xdceditorview_apply_all_changes_to_xdc_constraints=2</TD>
<TD>xdcviewertreetablepanel_xdc_viewer_tree_table=4</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'> <TD>addcfgmem=1</TD>
<TD>addsources=24</TD>
<TD>autoconnecttarget=2</TD>
<TD>closeproject=2</TD>
</TR><TR ALIGN='LEFT'> <TD>editdelete=5</TD>
<TD>editpaste=5</TD>
<TD>editundo=1</TD>
<TD>launchopentarget=4</TD>
</TR><TR ALIGN='LEFT'> <TD>launchprogramfpga=15</TD>
<TD>newproject=1</TD>
<TD>openhardwaremanager=24</TD>
<TD>openproject=4</TD>
</TR><TR ALIGN='LEFT'> <TD>openrecenttarget=14</TD>
<TD>programdevice=18</TD>
<TD>reporttimingsummary=1</TD>
<TD>runbitgen=47</TD>
</TR><TR ALIGN='LEFT'> <TD>runimplementation=6</TD>
<TD>runsynthesis=22</TD>
<TD>savefileproxyhandler=4</TD>
<TD>settargetconstrfile=3</TD>
</TR><TR ALIGN='LEFT'> <TD>settopnode=1</TD>
<TD>showsource=1</TD>
<TD>showview=53</TD>
<TD>simulationrelaunch=5</TD>
</TR><TR ALIGN='LEFT'> <TD>simulationrun=172</TD>
<TD>timingconstraintswizard=7</TD>
<TD>toggleviewnavigator=4</TD>
<TD>toolssettings=15</TD>
</TR><TR ALIGN='LEFT'> <TD>updatesourcefiles=5</TD>
<TD>viewlayoutcmd=1</TD>
<TD>viewtaskimplementation=4</TD>
<TD>viewtasksynthesis=1</TD>
</TR><TR ALIGN='LEFT'> <TD>waveformsaveconfiguration=13</TD>
<TD>xdccreateclock=1</TD>
</TR> </TABLE>
</TR><TR ALIGN='LEFT'> <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>guimode=24</TD>
</TR> </TABLE>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'> <TD>constraintsetcount=1</TD>
<TD>core_container=false</TD>
<TD>currentimplrun=impl_1</TD>
<TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'> <TD>default_library=xil_defaultlib</TD>
<TD>designmode=RTL</TD>
<TD>export_simulation_activehdl=0</TD>
<TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_modelsim=0</TD>
<TD>export_simulation_questa=0</TD>
<TD>export_simulation_riviera=0</TD>
<TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>export_simulation_xsim=0</TD>
<TD>implstrategy=Vivado Implementation Defaults</TD>
<TD>launch_simulation_activehdl=0</TD>
<TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_modelsim=0</TD>
<TD>launch_simulation_questa=0</TD>
<TD>launch_simulation_riviera=0</TD>
<TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'> <TD>launch_simulation_xsim=174</TD>
<TD>simulator_language=Mixed</TD>
<TD>srcsetcount=11</TD>
<TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'> <TD>target_language=VHDL</TD>
<TD>target_simulator=XSim</TD>
<TD>totalimplruns=1</TD>
<TD>totalsynthesisruns=1</TD>
</TR> </TABLE>
</TR> </TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=1</TD>
<TD>carry4=33</TD>
<TD>fdre=330</TD>
<TD>fdse=12</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
<TD>ibuf=5</TD>
<TD>lut2=51</TD>
<TD>lut3=67</TD>
</TR><TR ALIGN='LEFT'> <TD>lut4=41</TD>
<TD>lut5=55</TD>
<TD>lut6=209</TD>
<TD>muxf7=19</TD>
</TR><TR ALIGN='LEFT'> <TD>obuf=8</TD>
<TD>vcc=5</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg=1</TD>
<TD>carry4=33</TD>
<TD>fdre=330</TD>
<TD>fdse=12</TD>
</TR><TR ALIGN='LEFT'> <TD>gnd=8</TD>
<TD>ibuf=5</TD>
<TD>lut2=51</TD>
<TD>lut3=67</TD>
</TR><TR ALIGN='LEFT'> <TD>lut4=41</TD>
<TD>lut5=55</TD>
<TD>lut6=209</TD>
<TD>muxf7=19</TD>
</TR><TR ALIGN='LEFT'> <TD>obuf=8</TD>
<TD>vcc=5</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-internal=default::[not_specified]</TD>
<TD>-internal_only=default::[not_specified]</TD>
<TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-name=default::[not_specified]</TD>
<TD>-no_waivers=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
<TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-upgrade_cw=default::[not_specified]</TD>
<TD>-waived=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'> <TD>cfgbvs-1=1</TD>
<TD>lutlp-2=2</TD>
<TD>nstd-1=1</TD>
<TD>ucio-1=1</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>nstd-1=Warning</TD>
<TD>ucio-1=Warning</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-append=default::[not_specified]</TD>
<TD>-checks=default::[not_specified]</TD>
<TD>-fail_on=default::[not_specified]</TD>
<TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-format=default::[not_specified]</TD>
<TD>-messages=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-waived=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'> <TD>timing-17=342</TD>
<TD>timing-23=1</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>nstd-1=Warning</TD>
<TD>ucio-1=Warning</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-advisory=default::[not_specified]</TD>
<TD>-append=default::[not_specified]</TD>
<TD>-file=[specified]</TD>
<TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'> <TD>-hier=default::power</TD>
<TD>-l=default::[not_specified]</TD>
<TD>-name=default::[not_specified]</TD>
<TD>-no_propagation=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-return_string=default::[not_specified]</TD>
<TD>-rpx=[specified]</TD>
<TD>-verbose=default::[not_specified]</TD>
<TD>-vid=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-xpe=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>airflow=250 (LFM)</TD>
<TD>ambient_temp=25.0 (C)</TD>
<TD>bi-dir_toggle=12.500000</TD>
<TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>board_layers=12to15 (12 to 15 Layers)</TD>
<TD>board_selection=medium (10&quot;x10&quot;)</TD>
<TD>confidence_level_clock_activity=Low</TD>
<TD>confidence_level_design_state=High</TD>
</TR><TR ALIGN='LEFT'> <TD>confidence_level_device_models=High</TD>
<TD>confidence_level_internal_activity=Medium</TD>
<TD>confidence_level_io_activity=Low</TD>
<TD>confidence_level_overall=Low</TD>
</TR><TR ALIGN='LEFT'> <TD>customer=TBD</TD>
<TD>customer_class=TBD</TD>
<TD>devstatic=0.081472</TD>
<TD>die=xc7a35tcpg236-1</TD>
</TR><TR ALIGN='LEFT'> <TD>dsp_output_toggle=12.500000</TD>
<TD>dynamic=3.252769</TD>
<TD>effective_thetaja=5.0</TD>
<TD>enable_probability=0.990000</TD>
</TR><TR ALIGN='LEFT'> <TD>family=artix7</TD>
<TD>ff_toggle=12.500000</TD>
<TD>flow_state=routed</TD>
<TD>heatsink=medium (Medium Profile)</TD>
</TR><TR ALIGN='LEFT'> <TD>i/o=0.804337</TD>
<TD>input_toggle=12.500000</TD>
<TD>junction_temp=41.7 (C)</TD>
<TD>logic=1.293960</TD>
</TR><TR ALIGN='LEFT'> <TD>mgtavcc_dynamic_current=0.000000</TD>
<TD>mgtavcc_static_current=0.000000</TD>
<TD>mgtavcc_total_current=0.000000</TD>
<TD>mgtavcc_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>mgtavtt_dynamic_current=0.000000</TD>
<TD>mgtavtt_static_current=0.000000</TD>
<TD>mgtavtt_total_current=0.000000</TD>
<TD>mgtavtt_voltage=1.200000</TD>
</TR><TR ALIGN='LEFT'> <TD>netlist_net_matched=NA</TD>
<TD>off-chip_power=0.000000</TD>
<TD>on-chip_power=3.334241</TD>
<TD>output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>output_load=5.000000</TD>
<TD>output_toggle=12.500000</TD>
<TD>package=cpg236</TD>
<TD>pct_clock_constrained=0.860000</TD>
</TR><TR ALIGN='LEFT'> <TD>pct_inputs_defined=0</TD>
<TD>platform=lin64</TD>
<TD>process=typical</TD>
<TD>ram_enable=50.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>ram_write=50.000000</TD>
<TD>read_saif=False</TD>
<TD>set/reset_probability=0.000000</TD>
<TD>signal_rate=False</TD>
</TR><TR ALIGN='LEFT'> <TD>signals=1.154472</TD>
<TD>simulation_file=None</TD>
<TD>speedgrade=-1</TD>
<TD>static_prob=False</TD>
</TR><TR ALIGN='LEFT'> <TD>temp_grade=commercial</TD>
<TD>thetajb=7.5 (C/W)</TD>
<TD>thetasa=4.6 (C/W)</TD>
<TD>toggle_rate=False</TD>
</TR><TR ALIGN='LEFT'> <TD>user_board_temp=25.0 (C)</TD>
<TD>user_effective_thetaja=5.0</TD>
<TD>user_junc_temp=41.7 (C)</TD>
<TD>user_thetajb=7.5 (C/W)</TD>
</TR><TR ALIGN='LEFT'> <TD>user_thetasa=4.6 (C/W)</TD>
<TD>vccadc_dynamic_current=0.000000</TD>
<TD>vccadc_static_current=0.020000</TD>
<TD>vccadc_total_current=0.020000</TD>
</TR><TR ALIGN='LEFT'> <TD>vccadc_voltage=1.800000</TD>
<TD>vccaux_dynamic_current=0.028741</TD>
<TD>vccaux_io_dynamic_current=0.000000</TD>
<TD>vccaux_io_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vccaux_io_total_current=0.000000</TD>
<TD>vccaux_io_voltage=1.800000</TD>
<TD>vccaux_static_current=0.013356</TD>
<TD>vccaux_total_current=0.042097</TD>
</TR><TR ALIGN='LEFT'> <TD>vccaux_voltage=1.800000</TD>
<TD>vccbram_dynamic_current=0.000000</TD>
<TD>vccbram_static_current=0.000299</TD>
<TD>vccbram_total_current=0.000299</TD>
</TR><TR ALIGN='LEFT'> <TD>vccbram_voltage=1.000000</TD>
<TD>vccint_dynamic_current=2.468432</TD>
<TD>vccint_static_current=0.017832</TD>
<TD>vccint_total_current=2.486264</TD>
</TR><TR ALIGN='LEFT'> <TD>vccint_voltage=1.000000</TD>
<TD>vcco12_dynamic_current=0.000000</TD>
<TD>vcco12_static_current=0.000000</TD>
<TD>vcco12_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco12_voltage=1.200000</TD>
<TD>vcco135_dynamic_current=0.000000</TD>
<TD>vcco135_static_current=0.000000</TD>
<TD>vcco135_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco135_voltage=1.350000</TD>
<TD>vcco15_dynamic_current=0.000000</TD>
<TD>vcco15_static_current=0.000000</TD>
<TD>vcco15_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco15_voltage=1.500000</TD>
<TD>vcco18_dynamic_current=0.000000</TD>
<TD>vcco18_static_current=0.000000</TD>
<TD>vcco18_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco18_voltage=1.800000</TD>
<TD>vcco25_dynamic_current=0.000000</TD>
<TD>vcco25_static_current=0.000000</TD>
<TD>vcco25_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco25_voltage=2.500000</TD>
<TD>vcco33_dynamic_current=0.222001</TD>
<TD>vcco33_static_current=0.001000</TD>
<TD>vcco33_total_current=0.223001</TD>
</TR><TR ALIGN='LEFT'> <TD>vcco33_voltage=3.300000</TD>
<TD>version=2018.2</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufgctrl_available=32</TD>
<TD>bufgctrl_fixed=0</TD>
<TD>bufgctrl_used=1</TD>
<TD>bufgctrl_util_percentage=3.13</TD>
</TR><TR ALIGN='LEFT'> <TD>bufhce_available=72</TD>
<TD>bufhce_fixed=0</TD>
<TD>bufhce_used=0</TD>
<TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufio_available=20</TD>
<TD>bufio_fixed=0</TD>
<TD>bufio_used=0</TD>
<TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufmrce_available=10</TD>
<TD>bufmrce_fixed=0</TD>
<TD>bufmrce_used=0</TD>
<TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>bufr_available=20</TD>
<TD>bufr_fixed=0</TD>
<TD>bufr_used=0</TD>
<TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>mmcme2_adv_available=5</TD>
<TD>mmcme2_adv_fixed=0</TD>
<TD>mmcme2_adv_used=0</TD>
<TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>plle2_adv_available=5</TD>
<TD>plle2_adv_fixed=0</TD>
<TD>plle2_adv_used=0</TD>
<TD>plle2_adv_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'> <TD>dsps_available=90</TD>
<TD>dsps_fixed=0</TD>
<TD>dsps_used=0</TD>
<TD>dsps_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'> <TD>blvds_25=0</TD>
<TD>diff_hstl_i=0</TD>
<TD>diff_hstl_i_18=0</TD>
<TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_hstl_ii_18=0</TD>
<TD>diff_hsul_12=0</TD>
<TD>diff_mobile_ddr=0</TD>
<TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl135_r=0</TD>
<TD>diff_sstl15=0</TD>
<TD>diff_sstl15_r=0</TD>
<TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'> <TD>diff_sstl18_ii=0</TD>
<TD>hstl_i=0</TD>
<TD>hstl_i_18=0</TD>
<TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>hstl_ii_18=0</TD>
<TD>hsul_12=0</TD>
<TD>lvcmos12=0</TD>
<TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvcmos18=1</TD>
<TD>lvcmos25=0</TD>
<TD>lvcmos33=1</TD>
<TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lvttl=0</TD>
<TD>mini_lvds_25=0</TD>
<TD>mobile_ddr=0</TD>
<TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'> <TD>ppds_25=0</TD>
<TD>rsds_25=0</TD>
<TD>sstl135=0</TD>
<TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'> <TD>sstl15=0</TD>
<TD>sstl15_r=0</TD>
<TD>sstl18_i=0</TD>
<TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'> <TD>tmds_33=0</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'> <TD>block_ram_tile_available=50</TD>
<TD>block_ram_tile_fixed=0</TD>
<TD>block_ram_tile_used=0</TD>
<TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb18_available=100</TD>
<TD>ramb18_fixed=0</TD>
<TD>ramb18_used=0</TD>
<TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>ramb36_fifo_available=50</TD>
<TD>ramb36_fifo_fixed=0</TD>
<TD>ramb36_fifo_used=0</TD>
<TD>ramb36_fifo_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bufg_functional_category=Clock</TD>
<TD>bufg_used=1</TD>
<TD>carry4_functional_category=CarryLogic</TD>
<TD>carry4_used=33</TD>
</TR><TR ALIGN='LEFT'> <TD>fdre_functional_category=Flop &amp; Latch</TD>
<TD>fdre_used=330</TD>
<TD>fdse_functional_category=Flop &amp; Latch</TD>
<TD>fdse_used=12</TD>
</TR><TR ALIGN='LEFT'> <TD>ibuf_functional_category=IO</TD>
<TD>ibuf_used=5</TD>
<TD>lut2_functional_category=LUT</TD>
<TD>lut2_used=51</TD>
</TR><TR ALIGN='LEFT'> <TD>lut3_functional_category=LUT</TD>
<TD>lut3_used=67</TD>
<TD>lut4_functional_category=LUT</TD>
<TD>lut4_used=41</TD>
</TR><TR ALIGN='LEFT'> <TD>lut5_functional_category=LUT</TD>
<TD>lut5_used=55</TD>
<TD>lut6_functional_category=LUT</TD>
<TD>lut6_used=209</TD>
</TR><TR ALIGN='LEFT'> <TD>muxf7_functional_category=MuxFx</TD>
<TD>muxf7_used=19</TD>
<TD>obuf_functional_category=IO</TD>
<TD>obuf_used=8</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'> <TD>f7_muxes_available=16300</TD>
<TD>f7_muxes_fixed=0</TD>
<TD>f7_muxes_used=19</TD>
<TD>f7_muxes_util_percentage=0.12</TD>
</TR><TR ALIGN='LEFT'> <TD>f8_muxes_available=8150</TD>
<TD>f8_muxes_fixed=0</TD>
<TD>f8_muxes_used=0</TD>
<TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=371</TD>
<TD>lut_as_logic_util_percentage=1.78</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_flip_flop_available=41600</TD>
<TD>register_as_flip_flop_fixed=0</TD>
<TD>register_as_flip_flop_used=342</TD>
<TD>register_as_flip_flop_util_percentage=0.82</TD>
</TR><TR ALIGN='LEFT'> <TD>register_as_latch_available=41600</TD>
<TD>register_as_latch_fixed=0</TD>
<TD>register_as_latch_used=0</TD>
<TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_luts_available=20800</TD>
<TD>slice_luts_fixed=0</TD>
<TD>slice_luts_used=371</TD>
<TD>slice_luts_util_percentage=1.78</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_registers_available=41600</TD>
<TD>slice_registers_fixed=0</TD>
<TD>slice_registers_used=342</TD>
<TD>slice_registers_util_percentage=0.82</TD>
</TR><TR ALIGN='LEFT'> <TD>fully_used_lut_ff_pairs_fixed=0.82</TD>
<TD>fully_used_lut_ff_pairs_used=5</TD>
<TD>lut_as_distributed_ram_fixed=0</TD>
<TD>lut_as_distributed_ram_used=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_logic_available=20800</TD>
<TD>lut_as_logic_fixed=0</TD>
<TD>lut_as_logic_used=371</TD>
<TD>lut_as_logic_util_percentage=1.78</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_memory_available=9600</TD>
<TD>lut_as_memory_fixed=0</TD>
<TD>lut_as_memory_used=0</TD>
<TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_as_shift_register_fixed=0</TD>
<TD>lut_as_shift_register_used=0</TD>
<TD>lut_ff_pairs_with_one_unused_flip_flop_fixed=0</TD>
<TD>lut_ff_pairs_with_one_unused_flip_flop_used=37</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_ff_pairs_with_one_unused_lut_output_fixed=37</TD>
<TD>lut_ff_pairs_with_one_unused_lut_output_used=42</TD>
<TD>lut_flip_flop_pairs_available=20800</TD>
<TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>lut_flip_flop_pairs_used=48</TD>
<TD>lut_flip_flop_pairs_util_percentage=0.23</TD>
<TD>slice_available=8150</TD>
<TD>slice_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>slice_used=158</TD>
<TD>slice_util_percentage=1.94</TD>
<TD>slicel_fixed=0</TD>
<TD>slicel_used=103</TD>
</TR><TR ALIGN='LEFT'> <TD>slicem_fixed=0</TD>
<TD>slicem_used=55</TD>
<TD>unique_control_sets_used=36</TD>
<TD>using_o5_and_o6_fixed=36</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o5_and_o6_used=52</TD>
<TD>using_o5_output_only_fixed=52</TD>
<TD>using_o5_output_only_used=0</TD>
<TD>using_o6_output_only_fixed=0</TD>
</TR><TR ALIGN='LEFT'> <TD>using_o6_output_only_used=319</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'> <TD>bscane2_available=4</TD>
<TD>bscane2_fixed=0</TD>
<TD>bscane2_used=0</TD>
<TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>capturee2_available=1</TD>
<TD>capturee2_fixed=0</TD>
<TD>capturee2_used=0</TD>
<TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>dna_port_available=1</TD>
<TD>dna_port_fixed=0</TD>
<TD>dna_port_used=0</TD>
<TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>efuse_usr_available=1</TD>
<TD>efuse_usr_fixed=0</TD>
<TD>efuse_usr_used=0</TD>
<TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>frame_ecce2_available=1</TD>
<TD>frame_ecce2_fixed=0</TD>
<TD>frame_ecce2_used=0</TD>
<TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>icape2_available=2</TD>
<TD>icape2_fixed=0</TD>
<TD>icape2_used=0</TD>
<TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>pcie_2_1_available=1</TD>
<TD>pcie_2_1_fixed=0</TD>
<TD>pcie_2_1_used=0</TD>
<TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>startupe2_available=1</TD>
<TD>startupe2_fixed=0</TD>
<TD>startupe2_used=0</TD>
<TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'> <TD>xadc_available=1</TD>
<TD>xadc_fixed=0</TD>
<TD>xadc_used=0</TD>
<TD>xadc_util_percentage=0.00</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>actual_expansions=336796</TD>
<TD>bogomips=6000</TD>
<TD>bram18=0</TD>
<TD>bram36=0</TD>
</TR><TR ALIGN='LEFT'> <TD>bufg=0</TD>
<TD>bufr=0</TD>
<TD>ctrls=36</TD>
<TD>dsp=0</TD>
</TR><TR ALIGN='LEFT'> <TD>effort=2</TD>
<TD>estimated_expansions=475116</TD>
<TD>ff=342</TD>
<TD>global_clocks=1</TD>
</TR><TR ALIGN='LEFT'> <TD>high_fanout_nets=0</TD>
<TD>iob=13</TD>
<TD>lut=371</TD>
<TD>movable_instances=844</TD>
</TR><TR ALIGN='LEFT'> <TD>nets=925</TD>
<TD>pins=4840</TD>
<TD>pll=0</TD>
<TD>router_runtime=0.000000</TD>
</TR><TR ALIGN='LEFT'> <TD>router_timing_driven=1</TD>
<TD>threads=6</TD>
<TD>timing_constraints_exist=1</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-assert=default::[not_specified]</TD>
<TD>-bufg=default::12</TD>
<TD>-cascade_dsp=default::auto</TD>
<TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-control_set_opt_threshold=default::auto</TD>
<TD>-directive=default::default</TD>
<TD>-fanout_limit=default::10000</TD>
<TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'> <TD>-fsm_extraction=default::auto</TD>
<TD>-gated_clock_conversion=default::off</TD>
<TD>-generic=default::[not_specified]</TD>
<TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-keep_equivalent_registers=default::[not_specified]</TD>
<TD>-max_bram=default::-1</TD>
<TD>-max_bram_cascade_height=default::-1</TD>
<TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-max_uram=default::-1</TD>
<TD>-max_uram_cascade_height=default::-1</TD>
<TD>-mode=default::default</TD>
<TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-no_lc=default::[not_specified]</TD>
<TD>-no_srlextract=default::[not_specified]</TD>
<TD>-no_timing_driven=default::[not_specified]</TD>
<TD>-part=xc7a35tcpg236-1</TD>
</TR><TR ALIGN='LEFT'> <TD>-resource_sharing=default::auto</TD>
<TD>-retiming=default::[not_specified]</TD>
<TD>-rtl=default::[not_specified]</TD>
<TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'> <TD>-rtl_skip_ip=default::[not_specified]</TD>
<TD>-seu_protect=default::none</TD>
<TD>-sfcu=default::[not_specified]</TD>
<TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'> <TD>-top=Pipeline</TD>
<TD>-verilog_define=default::[not_specified]</TD>
</TR> </TABLE>
</TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'> <TD>elapsed=00:00:23s</TD>
<TD>hls_ip=0</TD>
<TD>memory_gain=491.398MB</TD>
<TD>memory_peak=1651.219MB</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
<TR><TD>
<TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
<TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'> <TD>-sim_mode=default::behavioral</TD>
<TD>-sim_type=default::</TD>
</TR> </TABLE>
</TD></TR>
</TABLE><BR>
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