237 lines
15 KiB
Text
237 lines
15 KiB
Text
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*** Running vivado
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with args -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl
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****** Vivado v2018.2 (64-bit)
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**** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
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**** IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
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** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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source ALU.tcl -notrace
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Command: synth_design -top ALU -part xc7a35tcpg236-1
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
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INFO: Launching helper process for spawning children vivado processes
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INFO: Helper process launched with PID 846814
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---------------------------------------------------------------------------------
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Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1255.277 ; gain = 83.809 ; free physical = 100416 ; free virtual = 133773
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---------------------------------------------------------------------------------
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INFO: [Synth 8-638] synthesizing module 'ALU' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
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INFO: [Synth 8-256] done synthesizing module 'ALU' (1#1) [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:46]
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---------------------------------------------------------------------------------
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Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100409 ; free virtual = 133768
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1299.902 ; gain = 128.434 ; free physical = 100408 ; free virtual = 133766
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7a35tcpg236-1
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INFO: [Device 21-403] Loading part xc7a35tcpg236-1
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.906 ; gain = 136.438 ; free physical = 100394 ; free virtual = 133753
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---------------------------------------------------------------------------------
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WARNING: [Synth 8-327] inferring latch for variable 'res_reg' [/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd:49]
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---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1315.914 ; gain = 144.445 ; free physical = 100397 ; free virtual = 133755
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start RTL Component Statistics
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---------------------------------------------------------------------------------
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Detailed RTL Component Info :
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+---Adders :
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3 Input 16 Bit Adders := 1
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+---Muxes :
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2 Input 16 Bit Muxes := 1
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2 Input 1 Bit Muxes := 2
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---------------------------------------------------------------------------------
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Finished RTL Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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Hierarchical RTL Component report
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Module ALU
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Detailed RTL Component Info :
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+---Adders :
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3 Input 16 Bit Adders := 1
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+---Muxes :
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2 Input 16 Bit Muxes := 1
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2 Input 1 Bit Muxes := 2
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---------------------------------------------------------------------------------
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Finished RTL Hierarchical Component Statistics
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Part Resource Summary
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---------------------------------------------------------------------------------
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Part Resources:
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DSPs: 90 (col length:60)
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BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
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---------------------------------------------------------------------------------
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Finished Part Resource Summary
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---------------------------------------------------------------------------------
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Cross Boundary and Area Optimization
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---------------------------------------------------------------------------------
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Warning: Parallel synthesis criteria is not met
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---------------------------------------------------------------------------------
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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No constraint files found.
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---------------------------------------------------------------------------------
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Start Timing Optimization
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:00:10 ; elapsed = 00:00:30 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133619
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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Report Check Netlist:
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+------+------------------+-------+---------+-------+------------------+
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| |Item |Errors |Warnings |Status |Description |
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+------+------------------+-------+---------+-------+------------------+
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|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
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+------+------------------+-------+---------+-------+------------------+
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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Report RTL Partitions:
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+-+--------------+------------+----------+
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| |RTL Partition |Replication |Instances |
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+-+--------------+------------+----------+
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+-+--------------+------------+----------+
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---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Writing Synthesis Report
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---------------------------------------------------------------------------------
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Report BlackBoxes:
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+-+--------------+----------+
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| |BlackBox name |Instances |
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+-+--------------+----------+
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+-+--------------+----------+
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Report Cell Usage:
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+------+-------+------+
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| |Cell |Count |
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+------+-------+------+
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|1 |CARRY4 | 18|
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|2 |LUT2 | 31|
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|3 |LUT3 | 6|
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|4 |LUT4 | 41|
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|5 |LUT5 | 12|
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|6 |LUT6 | 52|
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|7 |LD | 16|
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|8 |IBUF | 19|
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|9 |OBUF | 12|
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+------+-------+------+
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Report Instance Areas:
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+------+---------+-------+------+
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| |Instance |Module |Cells |
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+------+---------+-------+------+
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|1 |top | | 207|
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+------+---------+-------+------+
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---------------------------------------------------------------------------------
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100260 ; free virtual = 133620
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---------------------------------------------------------------------------------
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Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
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Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.023 ; gain = 262.555 ; free physical = 100264 ; free virtual = 133623
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Synthesis Optimization Complete : Time (s): cpu = 00:00:11 ; elapsed = 00:00:31 . Memory (MB): peak = 1434.031 ; gain = 262.555 ; free physical = 100274 ; free virtual = 133633
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INFO: [Project 1-571] Translating synthesized netlist
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INFO: [Netlist 29-17] Analyzing 53 Unisim elements for replacement
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INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
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INFO: [Project 1-570] Preparing netlist for logic optimization
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INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 16 instances were transformed.
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LD => LDCE: 16 instances
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INFO: [Common 17-83] Releasing license: Synthesis
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11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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synth_design completed successfully
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synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 1566.051 ; gain = 406.227 ; free physical = 100237 ; free virtual = 133596
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WARNING: [Constraints 18-5210] No constraint will be written out.
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INFO: [Common 17-1381] The checkpoint '/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/ALU.dcp' has been generated.
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INFO: [runtcl-4] Executing : report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb
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report_utilization: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1590.062 ; gain = 0.000 ; free physical = 100235 ; free virtual = 133594
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INFO: [Common 17-206] Exiting Vivado at Sun May 14 22:49:12 2023...
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