Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/cpu.xdc
2023-05-30 00:49:56 +02:00

1 line
78 B
Tcl

create_clock -period 10.000 -name Clk -waveform {0.000 5.000} [get_ports Clk]