Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log
2023-05-29 13:58:26 +02:00

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INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu