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Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/Compile_Options.txt
alejeune 22c945e716 Added VHDL part of the project
2023-05-29 13:58:26 +02:00

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-wto "aef36ef3a0d94dac9e6058b656907afd" --incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "secureip" --snapshot "Test_Alu_behav" "xil_defaultlib.Test_Alu" -log "elaborate.log"
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