Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd
2023-05-29 13:58:26 +02:00

107 lines
2.7 KiB
VHDL

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.05.2023 17:40:52
-- Design Name:
-- Module Name: Test_Alu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Alu is
-- Port ( );
end Test_Alu;
architecture Behavioral of Test_Alu is
component ALU
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div
S : out STD_LOGIC_VECTOR (7 downto 0);
N : out STD_LOGIC;
O : out STD_LOGIC;
Z : out STD_LOGIC;
C : out STD_LOGIC);
end component;
-- inputs
signal local_A : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal local_B : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal local_Ctrl_Alu : STD_LOGIC_VECTOR (2 downto 0) := (others => '0');
--outputs
signal local_S : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal local_N : STD_LOGIC := '0';
signal local_O : STD_LOGIC := '0';
signal local_Z : STD_LOGIC := '0';
signal local_C : STD_LOGIC := '0';
-- constant Clock_period : time := 10ns;
begin
-- instantiate
instance : ALU PORT MAP (
A => local_A,
B => local_B,
Ctrl_Alu => local_Ctrl_Alu,
S => local_S,
N => local_N,
O => local_O,
Z => local_Z,
C => local_C
);
local_Ctrl_Alu <= "000",
"001" after 20 ns,
"010" after 30 ns,
"100" after 40 ns,
"001" after 50 ns, -- test Z flag
"000" after 60 ns, -- test C flag
"010" after 70 ns; -- test O flag
local_A <= x"00",
x"10" after 10 ns,
x"a2" after 20 ns,
x"12" after 30 ns,
x"18" after 40 ns,
x"19" after 50 ns,
"10000000" after 60 ns;
local_B <= x"00",
x"78" after 10 ns,
x"b9" after 20 ns,
x"02" after 30 ns,
x"a2" after 40 ns,
x"19" after 50 ns,
"10000000" after 60 ns;
end Behavioral;