7 lines
185 B
Text
7 lines
185 B
Text
# compile vhdl design source files
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vhdl xil_defaultlib \
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"../../../../ALU.srcs/sources_1/new/ALU.vhd" \
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"../../../../ALU.srcs/sim_1/new/VHDL.vhd" \
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# Do not sort compile order
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nosort
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