Merge remote-tracking branch 'origin/master'

# Conflicts:
#	VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd

VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd

@@ -40,7 +40,8 @@ end InstructionMemory;
 
 architecture Behavioral of InstructionMemory is
     type Mem_array is array (0 to 255) of STD_LOGIC_VECTOR (31 downto 0);
-    signal Mem : Mem_array;
+    signal Mem : Mem_array := ((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"), others => (x"ff000000"));
+
 begin
 
     process

VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd

@@ -203,7 +203,7 @@ Stage1 : Stage_Li_Di PORT MAP (
     
 -- Registers
 StageRegisters : Registers PORT MAP (
-    Addr_A => Di_B(3 downto 0), -- becquse the registers are on 4 bits
+    Addr_A => Di_B(3 downto 0), -- because the registers are on 4 bits
     Addr_B => Di_C(3 downto 0),
     Addr_W => Re_A(3 downto 0),
     W => Re_W,
@@ -280,9 +280,13 @@ Stage4 : Stage_Mem_Re PORT MAP (
     -- NOT    x"0C"
     -- AND    x"0D"
     -- OR     x"0E"
+    -- JMP    x"0F"
+    -- JMF    x"10"
+    -- CAL    x"11"
+    -- RET    x"12"
+    -- PRI    x"13"
     -- NOP    x"FF"
 
-    
 -- Mux post registers 
 Di_FinalB <= Di_B when 
     Di_OP = x"06" -- AFC

asm

@@ -0,0 +1,20 @@
+AFC 4 2
+COP 3 4
+COP 2 0
+AFC 4 2
+ADD 5 2 4
+COP 0 5
+COP 0 3
+AFC 4 5
+COP 0 4
+AFC 4 19
+AFC 5 2
+ADD 4 4 5
+AFC 5 5
+MUL 4 5 0
+AFC 5 8
+ADD 4 4 5
+AFC 5 2
+MUL 4 4 5
+SUB 5 4 4
+COP 3 5

asm2

@@ -0,0 +1,52 @@
+AFC 0 2
+STORE 4 0
+LOAD 0 4
+STORE 3 0
+LOAD 0 0
+STORE 2 0
+AFC 0 2
+STORE 4 0
+LOAD 0 2
+LOAD 1 4
+ADD 0 0 1
+STORE 5 0
+LOAD 0 5
+STORE 0 0
+LOAD 0 3
+STORE 0 0
+AFC 0 5
+STORE 4 0
+LOAD 0 4
+STORE 0 0
+AFC 0 19
+STORE 4 0
+AFC 0 2
+STORE 5 0
+LOAD 0 4
+LOAD 1 5
+ADD 0 0 1
+STORE 4 0
+AFC 0 5
+STORE 5 0
+LOAD 0 5
+LOAD 1 0
+MUL 0 0 1
+STORE 4 0
+AFC 0 8
+STORE 5 0
+LOAD 0 4
+LOAD 1 5
+ADD 0 0 1
+STORE 4 0
+AFC 0 2
+STORE 5 0
+LOAD 0 4
+LOAD 1 5
+MUL 0 0 1
+STORE 4 0
+LOAD 0 4
+LOAD 1 4
+SUB 0 0 1
+STORE 5 0
+LOAD 0 5
+STORE 3 0

asm3

@@ -0,0 +1 @@
+((x"06000200"),(x"08040000"),(x"07000400"),(x"08030000"),(x"07000000"),(x"08020000"),(x"06000200"),(x"08040000"),(x"07000200"),(x"07010400"),(x"01000001"),(x"08050000"),(x"07000500"),(x"08000000"),(x"07000300"),(x"08000000"),(x"06000500"),(x"08040000"),(x"07000400"),(x"08000000"),(x"06001300"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000500"),(x"08050000"),(x"07000500"),(x"07010000"),(x"02000001"),(x"08040000"),(x"06000800"),(x"08050000"),(x"07000400"),(x"07010500"),(x"01000001"),(x"08040000"),(x"06000200"),(x"08050000"),(x"07000400"),(x"07010500"),(x"02000001"),(x"08040000"),(x"07000400"),(x"07010400"),(x"03000001"),(x"08050000"),(x"07000500"),(x"08030000"))

post-process.py

@@ -1,98 +1,107 @@
 import re
 
 opToBinOP = {
-    "ADD": 1,
+    "ADD": "01",
-    "MUL": 2,
+    "MUL": "02",
-    "SUB": 3,
+    "SUB": "03",
-    "DIV_INT": 4,
+    "DIV": "04",
-    "COP": 5,
+    "COP": "05",
-    "AFC": 6,
+    "AFC": "06",
-    "JMP": 7,
+    "LOAD": "07",
-    "JMF": 8,
+    "STORE": "08",
-    "INF": 9,
+    "INF": "09",
-    "SUP": 10,
+    "SUP": "0A",
-    "EQ": 11,
+    "EQ": "0B",
-    "PRI": 12,
+    "NOT": "0C",
-    "AND": 13,
+    "AND": "0D",
-    "OR": 14,
+    "OR": "0E",
-    "NOT": 15
+    "JMP": "0F",
+    "JMF": "10",
+    "CAL": "11",
+    "RET": "12",
+    "PRI": "13",
+    "NOP": "FF"
 }
 
 
-def output(s):
+def output(s, num, oneline=False):
-    fileOutput = open('asm2', 'w')
+    fileOutput = open(f'asm{num}', 'w')
+    if oneline:
+        fileOutput.write(s)
+    else :
         fileOutput.write("\n".join(s))
     fileOutput.close()
 
 
 def convertToRegister(s):
-    # TODO check if there is a /\d_label/ in s[0] and if so adds it back at the start of the output
     l = []
 
-    if not re.match(r"\d_LABEL .*", s[0]) :
+    if not re.match(r"\d_LABEL", s[0]):
         optionalFlag = ""
         incr = 0
+        op = s[0]
     else:
         optionalFlag = s[0] + " "
         incr = 1
+        op = s[1]
 
-    match s[0]:
+    match op:
         case "ADD":
-            l.append(optionalFlag+"LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("ADD R0 R0 R1")
+            l.append("ADD 0 0 1")
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "MUL":
-            l.append(optionalFlag+"LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("MUL R0 R0 R1")
+            l.append("MUL 0 0 1")
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "SUB":
-            l.append(optionalFlag+"LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("SUB R0 R0 R1")
+            l.append("SUB 0 0 1")
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "DIV_INT":
-            l.append(optionalFlag+"LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("DIV R0 R0 R1")
+            l.append("DIV 0 0 1")
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "COP":
-            l.append(optionalFlag+"LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "AFC":
-            l.append(optionalFlag+"AFC R0 "+s[2+incr])
+            l.append(optionalFlag + "AFC 0 " + s[2 + incr])
-            l.append("STORE "+s[1+incr]+" R0")
+            l.append("STORE " + s[1 + incr] + " 0")
         case "JMP":
-            pass
+            l.append(" ".join(s))
         case "JMF":
-            pass
+            l.append(" ".join(s))
         case "INF":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("INF R2 R0 R1")
+            l.append("INF 2 0 1")
         case "SUP":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("SUP R2 R1 R0")
+            l.append("SUP 2 1 0")
         case "EQ":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("EQ R2 R1 R0")
+            l.append("EQ 2 1 0")
         case "PRI":
-            l.append("PRI "+s[2+incr])
+            l.append(optionalFlag + "PRI " + s[2 + incr])
         case "AND":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("AND R2 R0 R1")
+            l.append("AND 2 0 1")
         case "OR":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("LOAD R1 "+s[3+incr])
+            l.append("LOAD 1 " + s[3 + incr])
-            l.append("OR R2 R0 R1")
+            l.append("OR 2 0 1")
         case "NOT":
-            l.append("LOAD R0 "+s[2+incr])
+            l.append(optionalFlag + "LOAD 0 " + s[2 + incr])
-            l.append("NOT R2 R0")
+            l.append("NOT 2 0")
-    """ R2 contiendra la valeur qui dit s'il faut sauter ou non """
+    """ R2 will contain the information whether to jump or not"""
 
     return l
 
@@ -107,6 +116,7 @@ fileInput.close()
 ASMLinesLabel = ASMLines[:]  # will contain at the end of the first loop the code with labels inserted
 ASMLinesRegister = []  # will contain at the end of the 2nd loop the registry-based code with labels
 ASMLinesFinal = []  # will contain the output, register-based, code
+
 for i, l in enumerate(ASMLines):
     items = l.split(" ")
     if items[0] in ["JMP", "JMF"]:
@@ -119,11 +129,11 @@ for i, l in enumerate(ASMLines):
             ASMLinesLabel[lineToJumpTo] = f"{labelCount}_LABEL " + ASMLines[lineToJumpTo]
             ASMLinesLabel[i] = " ".join(ASMLinesLabel[i].split()[:-1] + [f"{labelCount}_LABEL"])
             labelCount += 1
-print(ASMLinesLabel)
+print("labels : ", ASMLinesLabel)
 
 for i, l in enumerate(ASMLinesLabel):
     ASMLinesRegister.extend(convertToRegister(l.split()))
-print(ASMLinesRegister)
+print("regs : ", ASMLinesRegister)
 
 labels = {}
 for i, l in enumerate(ASMLinesRegister):
@@ -139,9 +149,15 @@ for i, l in enumerate(ASMLinesRegister):
     else:
         ASMLinesFinal.append(l)
 
+print(ASMLinesFinal)
+output(ASMLinesFinal, 2)
 
-print(ASMLinesRegister)
+lines = []
-output(ASMLinesFinal)
+for i, l in enumerate(ASMLinesFinal):
-# - trucs en registre
+    arr = l.split()
-# - décaler les Jumps
+    while len(arr) < 4:
-# - COP -> OPCode
+        arr.append(0)
+    lines.append(f"(x\"{opToBinOP[arr[0]]}{int(arr[1]):02X}{int(arr[2]):02X}{int(arr[3]):02X}\")")
+ASMLinesConverted = "(" + ",".join(lines) + ",others => (x\"ff000000\")"
+print("converted to VHDL-friendly format : " + ASMLinesConverted)
+output(ASMLinesConverted, 3, True)

testFile

@@ -0,0 +1,9 @@
+int main(){
+    int a, d;
+    int b, c = 2;
+    b = a;
+    a = b +2;
+    a = c;
+    a = 5;
+    c = 19 + 2 - (5 * a + 8) * 2;
+}

testFile_no_jmp

@@ -0,0 +1,9 @@
+int main(){
+    int a, d;
+    int b, c = 2;
+    b = a;
+    a = b +2;
+    a = c;
+    a = 5;
+    c = 19 + 2 - (5 * a + 8) * 2;
+}