rlacroix/Projet-Systemes-Informatiques
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2 commits
30d2d7577d ... 202c903459

Author SHA1 Message Date
Raphaël LACROIX
202c903459 big overhaul (2) 2023-05-31 23:21:40 +02:00
Raphaël LACROIX
5e4be22e3d big overhaul 2023-05-31 23:20:18 +02:00
329 changed files with 3667 additions and 11849 deletions
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VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
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version:1
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eof:67023714

36
VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
View file

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4
VHDL/ALU/ALU.cache/wt/project.wpc
View file

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eof:

39
VHDL/ALU/ALU.cache/wt/synthesis.wdf
View file

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3
VHDL/ALU/ALU.cache/wt/synthesis_details.wdf
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@ -1,3 +0,0 @@
version:1
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236
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
View file

@ -1,236 +0,0 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed May 31 18:34:50 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
<property name="ProjectIteration" value="47" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="RTL" type="DesignMode"/>
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddCfgMem" value="1" type="JavaHandler"/>
<property name="AddSources" value="24" type="JavaHandler"/>
<property name="AutoConnectTarget" value="2" type="JavaHandler"/>
<property name="CloseProject" value="2" type="JavaHandler"/>
<property name="EditDelete" value="5" type="JavaHandler"/>
<property name="EditPaste" value="5" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="LaunchOpenTarget" value="4" type="JavaHandler"/>
<property name="LaunchProgramFpga" value="16" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenHardwareManager" value="25" type="JavaHandler"/>
<property name="OpenProject" value="4" type="JavaHandler"/>
<property name="OpenRecentTarget" value="14" type="JavaHandler"/>
<property name="ProgramDevice" value="19" type="JavaHandler"/>
<property name="ReportTimingSummary" value="1" type="JavaHandler"/>
<property name="RunBitgen" value="47" type="JavaHandler"/>
<property name="RunImplementation" value="6" type="JavaHandler"/>
<property name="RunSynthesis" value="22" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="4" type="JavaHandler"/>
<property name="SetTargetConstrFile" value="3" type="JavaHandler"/>
<property name="SetTopNode" value="1" type="JavaHandler"/>
<property name="ShowSource" value="1" type="JavaHandler"/>
<property name="ShowView" value="54" type="JavaHandler"/>
<property name="SimulationRelaunch" value="5" type="JavaHandler"/>
<property name="SimulationRun" value="173" type="JavaHandler"/>
<property name="TimingConstraintsWizard" value="7" type="JavaHandler"/>
<property name="ToggleViewNavigator" value="4" type="JavaHandler"/>
<property name="ToolsSettings" value="15" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
<property name="ViewLayoutCmd" value="1" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="4" type="JavaHandler"/>
<property name="ViewTaskSynthesis" value="1" type="JavaHandler"/>
<property name="WaveformSaveConfiguration" value="13" type="JavaHandler"/>
<property name="XdcCreateClock" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
<property name="AbstractFileView_CLOSE" value="1" type="GuiHandlerData"/>
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<property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="4" type="GuiHandlerData"/>
<property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_APPLY" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="31" type="GuiHandlerData"/>
<property name="BaseDialog_NO" value="2" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="235" type="GuiHandlerData"/>
<property name="BaseDialog_YES" value="40" type="GuiHandlerData"/>
<property name="ClockCreationPanel_CLOCK_NAME" value="1" type="GuiHandlerData"/>
<property name="ClockCreationPanel_ENTER_POSITIVE_NUMBER" value="5" type="GuiHandlerData"/>
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<property name="CmdMsgDialog_OK" value="33" type="GuiHandlerData"/>
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<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
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<property name="GraphicalView_ZOOM_OUT" value="152" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
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<property name="MessageWithOptionDialog_DONT_SHOW_THIS_DIALOG_AGAIN" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_SEVERITY" value="1" type="GuiHandlerData"/>
<property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="172" type="GuiHandlerData"/>
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<property name="NumJobsChooser_NUMBER_OF_JOBS" value="2" type="GuiHandlerData"/>
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<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="8" type="GuiHandlerData"/>
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<property name="WaveformView_NEXT_MARKER" value="3" type="GuiHandlerData"/>
<property name="XdcEditorView_APPLY_ALL_CHANGES_TO_XDC_CONSTRAINTS" value="2" type="GuiHandlerData"/>
<property name="XdcViewerTreeTablePanel_XDC_VIEWER_TREE_TABLE" value="4" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="8" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="5" type="TclMode"/>
</item>
</section>
</application>
</document>

4
VHDL/ALU/ALU.cache/wt/xsim.wdf
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@ -1,4 +0,0 @@
version:1
7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
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eof:241934075

8
VHDL/ALU/ALU.hw/ALU.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0">
<HWSession Dir="hw_1" File="hw.xml"/>
</labtools>

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VHDL/ALU/ALU.hw/hw_1/hw.xml
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2018.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
<hwsession version="1" minor="2">
<device name="xc7a35t_0" gui_info=""/>
<ObjectList object_type="hw_device" gui_info="">
<Object name="xc7a35t_0" gui_info="">
<Properties Property="FULL_PROBES.FILE" value=""/>
<Properties Property="PROBES.FILE" value=""/>
<Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/Pipeline.bit"/>
<Properties Property="SLR.COUNT" value="1"/>
</Object>
</ObjectList>
<probeset name="hw project" active="false"/>
</hwsession>

1
VHDL/ALU/ALU.ip_user_files/README.txt
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_1.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_10.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_11.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_12.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_13.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_14.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_15.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_16.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_17.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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</Runs>

8
VHDL/ALU/ALU.runs/.jobs/vrs_config_18.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
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8
VHDL/ALU/ALU.runs/.jobs/vrs_config_19.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_2.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_20.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_21.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_22.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_23.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

8
VHDL/ALU/ALU.runs/.jobs/vrs_config_24.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_25.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_26.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_27.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
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5
VHDL/ALU/ALU.runs/.jobs/vrs_config_28.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_29.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_3.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_30.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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VHDL/ALU/ALU.runs/.jobs/vrs_config_31.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_32.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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VHDL/ALU/ALU.runs/.jobs/vrs_config_33.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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VHDL/ALU/ALU.runs/.jobs/vrs_config_34.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_35.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_36.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
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VHDL/ALU/ALU.runs/.jobs/vrs_config_37.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_38.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_39.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_4.xml
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<?xml version="1.0"?>
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VHDL/ALU/ALU.runs/.jobs/vrs_config_40.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_41.xml
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@ -1,8 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

8
VHDL/ALU/ALU.runs/.jobs/vrs_config_42.xml
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@ -1,8 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_43.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_44.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_45.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_46.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_47.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_48.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_49.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_5.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_50.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_51.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
</Runs>

5
VHDL/ALU/ALU.runs/.jobs/vrs_config_52.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_53.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_54.xml
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_55.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_56.xml
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@ -1,8 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_57.xml
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@ -1,8 +0,0 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_58.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_59.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_6.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_60.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_61.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
<Parent Id="synth_1"/>
</Run>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_7.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_8.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
</Runs>

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VHDL/ALU/ALU.runs/.jobs/vrs_config_9.xml
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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
</Runs>

0
VHDL/ALU/ALU.runs/impl_1/.Vivado_Implementation.queue.rst
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VHDL/ALU/ALU.runs/impl_1/.init_design.begin.rst
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@ -1,5 +0,0 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="rlacroix" Host="" Pid="144223">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.init_design.end.rst
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VHDL/ALU/ALU.runs/impl_1/.opt_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="rlacroix" Host="" Pid="144223">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.opt_design.end.rst
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VHDL/ALU/ALU.runs/impl_1/.place_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="rlacroix" Host="" Pid="144223">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.place_design.end.rst
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VHDL/ALU/ALU.runs/impl_1/.route_design.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="rlacroix" Host="" Pid="144223">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.route_design.end.rst
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VHDL/ALU/ALU.runs/impl_1/.vivado.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="rlacroix" Host="" Pid="144193">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.vivado.end.rst
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VHDL/ALU/ALU.runs/impl_1/.write_bitstream.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="rlacroix" Host="" Pid="144223">
</Process>
</ProcessHandle>

0
VHDL/ALU/ALU.runs/impl_1/.write_bitstream.end.rst
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244
VHDL/ALU/ALU.runs/impl_1/ISEWrap.js
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//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}

63
VHDL/ALU/ALU.runs/impl_1/ISEWrap.sh
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@ -1,63 +0,0 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL

BIN
VHDL/ALU/ALU.runs/impl_1/Pipeline.bit
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Binary file not shown.

171
VHDL/ALU/ALU.runs/impl_1/Pipeline.tcl
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@ -1,171 +0,0 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
}
start_step init_design
set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a35tcpg236-1
set_property board_part digilentinc.com:basys3:part0:1.1 [current_project]
set_property design_mode GateLvl [current_fileset]
set_param project.singleFileAddWarning.threshold 0
set_property webtalk.parent_dir /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/wt [current_project]
set_property parent.project_path /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr [current_project]
set_property ip_output_repo /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
add_files -quiet /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/synth_1/Pipeline.dcp
read_xdc /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc
link_design -top Pipeline -part xc7a35tcpg236-1
close_msg_db -file init_design.pb
} RESULT]
if {$rc} {
step_failed init_design
return -code error $RESULT
} else {
end_step init_design
unset ACTIVE_STEP
}
start_step opt_design
set ACTIVE_STEP opt_design
set rc [catch {
create_msg_db opt_design.pb
opt_design
write_checkpoint -force Pipeline_opt.dcp
create_report "impl_1_opt_report_drc_0" "report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx"
close_msg_db -file opt_design.pb
} RESULT]
if {$rc} {
step_failed opt_design
return -code error $RESULT
} else {
end_step opt_design
unset ACTIVE_STEP
}
start_step place_design
set ACTIVE_STEP place_design
set rc [catch {
create_msg_db place_design.pb
if { [llength [get_debug_cores -quiet] ] > 0 } {
implement_debug_core
}
place_design
write_checkpoint -force Pipeline_placed.dcp
create_report "impl_1_place_report_io_0" "report_io -file Pipeline_io_placed.rpt"
create_report "impl_1_place_report_utilization_0" "report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb"
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file Pipeline_control_sets_placed.rpt"
close_msg_db -file place_design.pb
} RESULT]
if {$rc} {
step_failed place_design
return -code error $RESULT
} else {
end_step place_design
unset ACTIVE_STEP
}
start_step route_design
set ACTIVE_STEP route_design
set rc [catch {
create_msg_db route_design.pb
route_design
write_checkpoint -force Pipeline_routed.dcp
create_report "impl_1_route_report_drc_0" "report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx"
create_report "impl_1_route_report_methodology_0" "report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx"
create_report "impl_1_route_report_power_0" "report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx"
create_report "impl_1_route_report_route_status_0" "report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb"
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation "
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt"
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file Pipeline_clock_utilization_routed.rpt"
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx"
close_msg_db -file route_design.pb
} RESULT]
if {$rc} {
write_checkpoint -force Pipeline_routed_error.dcp
step_failed route_design
return -code error $RESULT
} else {
end_step route_design
unset ACTIVE_STEP
}
start_step write_bitstream
set ACTIVE_STEP write_bitstream
set rc [catch {
create_msg_db write_bitstream.pb
catch { write_mem_info -force Pipeline.mmi }
write_bitstream -force Pipeline.bit
catch {write_debug_probes -quiet -force Pipeline}
catch {file copy -force Pipeline.ltx debug_nets.ltx}
close_msg_db -file write_bitstream.pb
} RESULT]
if {$rc} {
step_failed write_bitstream
return -code error $RESULT
} else {
end_step write_bitstream
unset ACTIVE_STEP
}

472
VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi
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@ -1,472 +0,0 @@
#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Wed May 31 17:57:08 2023
# Process ID: 144223
# Current directory: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1
# Command line: vivado -log Pipeline.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Pipeline.tcl -notrace
# Log file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline.vdi
# Journal file: /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/vivado.jou
#-----------------------------------------------------------
source Pipeline.tcl -notrace
Command: link_design -top Pipeline -part xc7a35tcpg236-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:1]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-584] No ports matched 'CLK'. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc:2]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/constrs_1/new/test_cpu.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
7 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 1452.633 ; gain = 288.816 ; free physical = 7211 ; free virtual = 18994
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1519.656 ; gain = 67.023 ; free physical = 7187 ; free virtual = 18970
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1e379f571
Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 1976.156 ; gain = 456.500 ; free physical = 6811 ; free virtual = 18594
Starting Logic Optimization Task
Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1e379f571
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 224c05fcb
Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 3 Sweep
Phase 3 Sweep | Checksum: 237fe1223
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 237fe1223
Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 141d47eb5
Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 141d47eb5
Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
Ending Logic Optimization Task | Checksum: 141d47eb5
Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.07 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 141d47eb5
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 141d47eb5
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1976.156 ; gain = 0.000 ; free physical = 6811 ; free virtual = 18594
INFO: [Common 17-83] Releasing license: Implementation
23 Infos, 2 Warnings, 2 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 1976.156 ; gain = 523.523 ; free physical = 6811 ; free virtual = 18594
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2008.172 ; gain = 0.000 ; free physical = 6810 ; free virtual = 18594
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx
Command: report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 6 CPUs
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: cf3c03db
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 82288bfd
Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: e4604ef0
Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: e4604ef0
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 1 Placer Initialization | Checksum: e4604ef0
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: e4604ef0
Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2080.207 ; gain = 0.000 ; free physical = 6756 ; free virtual = 18539
WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer
Phase 2 Global Placement | Checksum: 15cb247ff
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 15cb247ff
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17faf0d06
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1bdff9a1c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1bdff9a1c
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 3 Detail Placement | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 112e53995
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 15dc57f83
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 15dc57f83
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6746 ; free virtual = 18529
Ending Placer Task | Checksum: 8268151a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.211 ; gain = 16.004 ; free physical = 6751 ; free virtual = 18535
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
place_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6750 ; free virtual = 18535
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file Pipeline_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6753 ; free virtual = 18537
INFO: [runtcl-4] Executing : report_utilization -file Pipeline_utilization_placed.rpt -pb Pipeline_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6761 ; free virtual = 18544
INFO: [runtcl-4] Executing : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2096.211 ; gain = 0.000 ; free physical = 6751 ; free virtual = 18534
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 6 CPUs
Checksum: PlaceDB: 1c700adb ConstDB: 0 ShapeSum: 65f80a3f RouteDB: 0
Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 77742d47
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2130.867 ; gain = 34.656 ; free physical = 6653 ; free virtual = 18437
Post Restoration Checksum: NetGraph: 69321eb NumContArr: 70e10b5c Constraints: 0 Timing: 0
Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 77742d47
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 77742d47
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2145.863 ; gain = 49.652 ; free physical = 6639 ; free virtual = 18422
Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 16523de4e
Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6629 ; free virtual = 18412
Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 11b0f7581
Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 97
Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 4 Rip-up And Reroute | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1 Hold Fix Iter | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 6 Post Hold Fix | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 0.153313 %
Global Horizontal Routing Utilization = 0.172046 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Congestion Report
North Dir 1x1 Area, Max Cong = 30.6306%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 22.5225%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
------------------------------
Reporting congestion hotspots
------------------------------
Direction: North
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: South
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: East
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Direction: West
----------------
Congested clusters found at Level 0
Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0
Phase 7 Route finalize | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2155.863 ; gain = 59.652 ; free physical = 6628 ; free virtual = 18412
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 14cade65a
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 16fad2baa
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6628 ; free virtual = 18412
INFO: [Route 35-16] Router Completed Successfully
Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 3 Warnings, 2 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:10 . Memory (MB): peak = 2157.863 ; gain = 61.652 ; free physical = 6646 ; free virtual = 18430
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2157.863 ; gain = 0.000 ; free physical = 6642 ; free virtual = 18427
INFO: [Common 17-1381] The checkpoint '/home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
Command: report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 6 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx
Command: report_methodology -file Pipeline_methodology_drc_routed.rpt -pb Pipeline_methodology_drc_routed.pb -rpx Pipeline_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 6 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /home/rlacroix/Bureau/4ir/syst_info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.runs/impl_1/Pipeline_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx
Command: report_power -file Pipeline_power_routed.rpt -pb Pipeline_power_summary_routed.pb -rpx Pipeline_power_routed.rpx
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
66 Infos, 4 Warnings, 2 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file Pipeline_route_status.rpt -pb Pipeline_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Pipeline_timing_summary_routed.rpt -pb Pipeline_timing_summary_routed.pb -rpx Pipeline_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
INFO: [runtcl-4] Executing : report_incremental_reuse -file Pipeline_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 6 CPUs
Command: write_bitstream -force Pipeline.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 6 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2.
WARNING: [DRC LUTLP-2] Combinatorial Loop Allowed: 3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, and Stage2/aux[7]_i_7.
WARNING: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
WARNING: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 5 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 6 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./Pipeline.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
84 Infos, 10 Warnings, 2 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 2490.594 ; gain = 244.660 ; free physical = 6581 ; free virtual = 18368
INFO: [Common 17-206] Exiting Vivado at Wed May 31 17:58:24 2023...

BIN
VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.pb
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15
VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpt
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@ -1,15 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed May 31 17:58:14 2023
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_bus_skew -warn_on_violation -file Pipeline_bus_skew_routed.rpt -pb Pipeline_bus_skew_routed.pb -rpx Pipeline_bus_skew_routed.rpx
| Design : Pipeline
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.22 2018-03-21
---------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints

BIN
VHDL/ALU/ALU.runs/impl_1/Pipeline_bus_skew_routed.rpx
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145
VHDL/ALU/ALU.runs/impl_1/Pipeline_clock_utilization_routed.rpt
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@ -1,145 +0,0 @@
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed May 31 17:58:14 2023
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_clock_utilization -file Pipeline_clock_utilization_routed.rpt
| Design : Pipeline
| Device : 7a35t-cpg236
| Speed File : -1 PRODUCTION 1.22 2018-03-21
--------------------------------------------------------------------------------------
Clock Utilization Report
Table of Contents
-----------------
1. Clock Primitive Utilization
2. Global Clock Resources
3. Global Clock Source Details
4. Clock Regions: Key Resource Utilization
5. Clock Regions : Global Clock Summary
6. Device Cell Placement Summary for Global Clock g0
7. Clock Region Cell Placement per Global Clock: Region X0Y0
1. Clock Primitive Utilization
------------------------------
+----------+------+-----------+-----+--------------+--------+
| Type | Used | Available | LOC | Clock Region | Pblock |
+----------+------+-----------+-----+--------------+--------+
| BUFGCTRL | 1 | 32 | 0 | 0 | 0 |
| BUFH | 0 | 72 | 0 | 0 | 0 |
| BUFIO | 0 | 20 | 0 | 0 | 0 |
| BUFMR | 0 | 10 | 0 | 0 | 0 |
| BUFR | 0 | 20 | 0 | 0 | 0 |
| MMCM | 0 | 5 | 0 | 0 | 0 |
| PLL | 0 | 5 | 0 | 0 | 0 |
+----------+------+-----------+-----+--------------+--------+
2. Global Clock Resources
-------------------------
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 342 | 0 | | | Clk_IBUF_BUFG_inst/O | Clk_IBUF_BUFG |
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
3. Global Clock Source Details
------------------------------
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
| src0 | g0 | IBUF/O | None | IOB_X0Y128 | X0Y2 | 1 | 0 | | | Clk_IBUF_inst/O | Clk_IBUF |
+-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
4. Clock Regions: Key Resource Utilization
------------------------------------------
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 342 | 1200 | 136 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
5. Clock Regions : Global Clock Summary
---------------------------------------
All Modules
+----+----+----+
| | X0 | X1 |
+----+----+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 1 | 0 |
+----+----+----+
6. Device Cell Placement Summary for Global Clock g0
----------------------------------------------------
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
| g0 | BUFG/O | n/a | | | | 342 | 0 | 0 | 0 | Clk_IBUF_BUFG |
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+
* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
**** GT Loads column represents load cell count of GT types
+----+------+----+
| | X0 | X1 |
+----+------+----+
| Y2 | 0 | 0 |
| Y1 | 0 | 0 |
| Y0 | 342 | 0 |
+----+------+----+
7. Clock Region Cell Placement per Global Clock: Region X0Y0
------------------------------------------------------------
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
| g0 | n/a | BUFG/O | None | 342 | 0 | 342 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Clk_IBUF_BUFG |
+-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+---------------+
* Clock Loads column represents the clock pin loads (pin count)
** Non-Clock Loads column represents the non-clock pin loads (pin count)
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
# Location of BUFG Primitives
set_property LOC BUFGCTRL_X0Y16 [get_cells Clk_IBUF_BUFG_inst]
# Location of IO Primitives which is load of clock spine
# Location of clock ports
set_property LOC IOB_X0Y128 [get_ports Clk]
# Clock net "Clk_IBUF_BUFG" driven by instance "Clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock {CLKAG_Clk_IBUF_BUFG}
add_cells_to_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="Clk_IBUF_BUFG"}]]]
resize_pblock [get_pblocks {CLKAG_Clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}
#endgroup

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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed May 31 17:57:59 2023
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_control_sets -verbose -file Pipeline_control_sets_placed.rpt
| Design : Pipeline
| Device : xc7a35t
-------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 36 |
| Unused register locations in slices containing registers | 12 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 12 | 2 |
| 16+ | 34 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 132 | 23 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 24 | 4 |
| Yes | No | No | 528 | 111 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+----------------+-----------------------+---------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+----------------+-----------------------+---------------------+------------------+----------------+
| Clk_IBUF_BUFG | | Stage1/Di_Op_Final1 | 2 | 12 |
| Clk_IBUF_BUFG | | Stage1/OP_LI_DI1 | 2 | 12 |
| Clk_IBUF_BUFG | Stage3/Mem[6]_8 | | 1 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[6]_9 | | 5 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[10]_8 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[11]_4 | | 5 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[12]_0 | | 5 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[13]_11 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[7]_5 | | 5 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[8]_1 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[9]_12 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs_reg[0][7] | | 2 | 16 |
| Clk_IBUF_BUFG | Stage1/aux_reg[7] | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[1]_14 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[2]_10 | | 5 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[8]_2 | | 1 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[9]_9 | | 3 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[4]_2 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[5]_13 | | 3 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[5]_0 | | 1 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem_reg[1][0] | | 2 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem_reg[2][0] | | 1 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[14]_7 | | 6 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[3]_7 | | 3 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem_reg[13][0] | | 1 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem_reg[14][0] | | 2 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[7]_6 | | 2 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[11]_5 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[12]_1 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[15]_3 | | 7 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[10]_10 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[15]_4 | | 2 | 16 |
| Clk_IBUF_BUFG | Stage4/Regs[3]_6 | | 4 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[0]_11 | | 2 | 16 |
| Clk_IBUF_BUFG | Stage3/Mem[4]_3 | | 3 | 16 |
| Clk_IBUF_BUFG | | | 23 | 132 |
+----------------+-----------------------+---------------------+------------------+----------------+

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VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_opted.rpt
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed May 31 17:57:56 2023
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_drc -file Pipeline_drc_opted.rpt -pb Pipeline_drc_opted.pb -rpx Pipeline_drc_opted.rpx
| Design : Pipeline
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 5
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 |
| NSTD-1 | Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Warning | Unconstrained Logical Port | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
LUTLP-2#1 Warning
Combinatorial Loop Allowed
1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2.
Related violations: <none>
LUTLP-2#2 Warning
Combinatorial Loop Allowed
3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7.
Related violations: <none>
NSTD-1#1 Warning
Unspecified I/O Standard
1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
Related violations: <none>
UCIO-1#1 Warning
Unconstrained Logical Port
1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
Related violations: <none>

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VHDL/ALU/ALU.runs/impl_1/Pipeline_drc_routed.pb
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Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
| Date : Wed May 31 17:58:11 2023
| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
| Command : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
| Design : Pipeline
| Device : xc7a35tcpg236-1
| Speed File : -1
| Design State : Routed
------------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 5
+----------+----------+-----------------------------------------------------+------------+
| Rule | Severity | Description | Violations |
+----------+----------+-----------------------------------------------------+------------+
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 |
| NSTD-1 | Warning | Unspecified I/O Standard | 1 |
| UCIO-1 | Warning | Unconstrained Logical Port | 1 |
+----------+----------+-----------------------------------------------------+------------+
2. REPORT DETAILS
-----------------
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
LUTLP-2#1 Warning
Combinatorial Loop Allowed
1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2.
Related violations: <none>
LUTLP-2#2 Warning
Combinatorial Loop Allowed
3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7.
Related violations: <none>
NSTD-1#1 Warning
Unspecified I/O Standard
1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
Related violations: <none>
UCIO-1#1 Warning
Unconstrained Logical Port
1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
Related violations: <none>

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