72 lines
5.3 KiB
Text
72 lines
5.3 KiB
Text
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
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| Date : Wed May 31 17:58:11 2023
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| Host : insa-20668 running 64-bit Ubuntu 20.04.6 LTS
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| Command : report_drc -file Pipeline_drc_routed.rpt -pb Pipeline_drc_routed.pb -rpx Pipeline_drc_routed.rpx
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| Design : Pipeline
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| Device : xc7a35tcpg236-1
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| Speed File : -1
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| Design State : Routed
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: netlist
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max violations: <unlimited>
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Violations found: 5
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+----------+----------+-----------------------------------------------------+------------+
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| Rule | Severity | Description | Violations |
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+----------+----------+-----------------------------------------------------+------------+
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| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
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| LUTLP-2 | Warning | Combinatorial Loop Allowed | 2 |
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| NSTD-1 | Warning | Unspecified I/O Standard | 1 |
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| UCIO-1 | Warning | Unconstrained Logical Port | 1 |
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+----------+----------+-----------------------------------------------------+------------+
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2. REPORT DETAILS
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-----------------
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CFGBVS-1#1 Warning
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Missing CFGBVS and CONFIG_VOLTAGE Design Properties
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Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
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set_property CFGBVS value1 [current_design]
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#where value1 is either VCCO or GND
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set_property CONFIG_VOLTAGE value2 [current_design]
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#where value2 is the voltage provided to configuration bank 0
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Refer to the device configuration user guide for more information.
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Related violations: <none>
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LUTLP-2#1 Warning
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Combinatorial Loop Allowed
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1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2.
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Related violations: <none>
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LUTLP-2#2 Warning
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Combinatorial Loop Allowed
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3 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. This loop has been identified in the constraints as being known and understood by use of the ALLOW_COMBINATORIAL_LOOPS property on a net in the loop. The cells in the loop are: Stage2/Out_Op[5]_i_2, Stage2/Out_Op[5]_i_3, Stage2/aux[7]_i_7.
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Related violations: <none>
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NSTD-1#1 Warning
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Unspecified I/O Standard
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1 out of 13 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
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Related violations: <none>
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UCIO-1#1 Warning
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Unconstrained Logical Port
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1 out of 13 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Clk.
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Related violations: <none>
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