WIP tried stuff

Merge remote-tracking branch 'origin/master'
# Conflicts: # VHDL/ALU/ALU.cache/wt/project.wpc # VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb # VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log # VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh # VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh # VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb # VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
2023-05-29 21:57:46 +02:00 · 2023-05-29 21:42:46 +02:00 · 2023-05-29 21:37:49 +02:00
--- a/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
+++ b/VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
@ -1,47 +1,49 @@
 version:1
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--- a/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
+++ b/VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
@ -1,15 +1,17 @@
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 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:32:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:33:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e696d706c656d656e746174696f6e:33:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:72756e73796e746865736973:36:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:34:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:33:00:00
-70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3633:00:00
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3638:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c65766965776e6176696761746f72:31:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:35:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:757064617465736f7572636566696c6573:35:00:00
 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
-eof:1280488146
+eof:2032391319
--- a/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
+++ b/VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Mon May 29 21:38:21 2023">
+<application name="pa" timeStamp="Mon May 29 21:42:56 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
 <property name="ProjectIteration" value="4" type="ProjectIteration"/>
@ -17,16 +17,18 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
 </item>
 <item name="Java Command Handlers">
-<property name="AddSources" value="15" type="JavaHandler"/>
+<property name="AddSources" value="16" type="JavaHandler"/>
 <property name="CloseProject" value="2" type="JavaHandler"/>
 <property name="EditDelete" value="2" type="JavaHandler"/>
 <property name="EditUndo" value="1" type="JavaHandler"/>
 <property name="NewProject" value="1" type="JavaHandler"/>
-<property name="OpenProject" value="2" type="JavaHandler"/>
+<property name="OpenProject" value="3" type="JavaHandler"/>
 <property name="RunImplementation" value="3" type="JavaHandler"/>
 <property name="RunSynthesis" value="6" type="JavaHandler"/>
 <property name="ShowView" value="4" type="JavaHandler"/>
 <property name="SimulationRelaunch" value="3" type="JavaHandler"/>
-<property name="SimulationRun" value="63" type="JavaHandler"/>
+<property name="SimulationRun" value="68" type="JavaHandler"/>
 <property name="ToggleViewNavigator" value="1" type="JavaHandler"/>
 <property name="ToolsSettings" value="5" type="JavaHandler"/>
 <property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
 <property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
@ -34,47 +36,49 @@ This means code written to parse this file will need to be revisited each subseq
 <item name="Gui Handlers">
 <property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
 <property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
 <property name="AddSrcWizard_SPECIFY_OR_CREATE_CONSTRAINT_FILES" value="1" type="GuiHandlerData"/>
 <property name="AddSrcWizard_SPECIFY_SIMULATION_SPECIFIC_HDL_FILES" value="1" type="GuiHandlerData"/>
 <property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="50" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="52" type="GuiHandlerData"/>
 <property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
-<property name="CmdMsgDialog_OK" value="19" type="GuiHandlerData"/>
+<property name="CmdMsgDialog_OK" value="22" type="GuiHandlerData"/>
 <property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
-<property name="CreateSrcFileDialog_FILE_NAME" value="13" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_NAME" value="14" type="GuiHandlerData"/>
 <property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
 <property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
 <property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="239" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="265" type="GuiHandlerData"/>
 <property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
-<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="77" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="86" type="GuiHandlerData"/>
 <property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
-<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="GettingStartedView_OPEN_PROJECT" value="3" type="GuiHandlerData"/>
 <property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
 <property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/>
 <property name="GraphicalView_ZOOM_OUT" value="26" type="GuiHandlerData"/>
 <property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
-<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/>
+<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="3" type="GuiHandlerData"/>
 <property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
 <property name="LogMonitor_MONITOR" value="1" type="GuiHandlerData"/>
 <property name="LogPanel_COPY" value="1" type="GuiHandlerData"/>
 <property name="LogPanel_FIND" value="1" type="GuiHandlerData"/>
 <property name="LogPanel_PAUSE_OUTPUT" value="2" type="GuiHandlerData"/>
 <property name="LogPanel_TOGGLE_COLUMN_SELECTION_MODE" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_CHECKPOINT" value="16" type="GuiHandlerData"/>
+<property name="MainMenuMgr_CHECKPOINT" value="18" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="64" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="66" type="GuiHandlerData"/>
 <property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
-<property name="MainMenuMgr_IP" value="9" type="GuiHandlerData"/>
+<property name="MainMenuMgr_IP" value="12" type="GuiHandlerData"/>
 <property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="22" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="43" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="45" type="GuiHandlerData"/>
 <property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
 <property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/>
+<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="14" type="GuiHandlerData"/>
-<property name="MainMenuMgr_TEXT_EDITOR" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TEXT_EDITOR" value="10" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TOOLS" value="10" type="GuiHandlerData"/>
 <property name="MainMenuMgr_VIEW" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_WINDOW" value="6" type="GuiHandlerData"/>
-<property name="MainToolbarMgr_RUN" value="6" type="GuiHandlerData"/>
+<property name="MainToolbarMgr_RUN" value="7" type="GuiHandlerData"/>
 <property name="MainWinMenuMgr_LAYOUT" value="4" type="GuiHandlerData"/>
 <property name="MsgTreePanel_MESSAGE_VIEW_TREE" value="21" type="GuiHandlerData"/>
 <property name="OpenFileAction_CANCEL" value="1" type="GuiHandlerData"/>
@ -84,34 +88,37 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
 <property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
 <property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
-<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="64" type="GuiHandlerData"/>
+<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="69" type="GuiHandlerData"/>
 <property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
 <property name="PAViews_CODE" value="19" type="GuiHandlerData"/>
 <property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
 <property name="PAViews_PROJECT_SUMMARY" value="2" type="GuiHandlerData"/>
 <property name="PlanAheadTab_SHOW_FLOW_NAVIGATOR" value="1" type="GuiHandlerData"/>
 <property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
 <property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
 <property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
-<property name="RDIViews_WAVEFORM_VIEWER" value="110" type="GuiHandlerData"/>
+<property name="RDIViews_WAVEFORM_VIEWER" value="112" type="GuiHandlerData"/>
 <property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
-<property name="SaveProjectUtils_SAVE" value="4" type="GuiHandlerData"/>
+<property name="SaveProjectUtils_SAVE" value="9" type="GuiHandlerData"/>
 <property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
 <property name="SimulationObjectsPanel_SIMULATION_OBJECTS_TREE_TABLE" value="1" type="GuiHandlerData"/>
 <property name="SimulationScopesPanel_SIMULATE_SCOPE_TABLE" value="8" type="GuiHandlerData"/>
-<property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="16" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="2" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_ADD_OR_CREATE_SOURCE_FILE" value="18" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/>
 <property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
 <property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
 <property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
 <property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
-<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
+<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="10" type="GuiHandlerData"/>
-<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="42" type="GuiHandlerData"/>
+<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="47" type="GuiHandlerData"/>
 <property name="WaveformView_ADD_MARKER" value="4" type="GuiHandlerData"/>
 <property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="22" type="GuiMode"/>
+<property name="GuiMode" value="1" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="16" type="TclMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
 </item>
 </section>
 </application>
--- a/VHDL/ALU/ALU.runs/synth_1/gen_run.xml
+++ b/VHDL/ALU/ALU.runs/synth_1/gen_run.xml
@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
  <File Type="PA-TCL" Name="ALU.tcl"/>
  <File Type="RDS-DCP" Name="ALU.dcp"/>
  <File Type="PA-TCL" Name="ALU.tcl"/>
  <File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
  <File Type="RDS-RDS" Name="ALU.vds"/>
  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
@ -169,17 +169,43 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/
 INFO: [VRFC 10-307] analyzing entity ALU
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
-INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity ALU
-INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
-INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity IP
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity InstructionMemory
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity DataMemory
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Pipeline
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Registers
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Stage_Di_Ex
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Stage_Ex_Mem
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Stage_Li_Di
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Stage_Mem_Re
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Pipeline
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Pipeline
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Pipeline
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity ALU
-INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity ALU
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_Alu
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_total
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_total
 INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
 INFO: [VRFC 10-307] analyzing entity Test_total
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
@ -6,7 +6,7 @@
 # Simulator   : Xilinx Vivado Simulator
 # Description : Script for compiling the simulation design source files
 #
-# Generated by Vivado on Mon May 29 21:15:03 CEST 2023
+# Generated by Vivado on Mon May 29 21:56:43 CEST 2023
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 #
 # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,5 +23,5 @@ then
 exit $RETVAL
 fi
 }
-echo "xvhdl --incr --relax -prj Test_Alu_vhdl.prj"
+echo "xvhdl --incr --relax -prj Test_total_vhdl.prj"
-ExecStep xvhdl --incr --relax -prj Test_Alu_vhdl.prj 2>&1 | tee -a compile.log
+ExecStep xvhdl --incr --relax -prj Test_total_vhdl.prj 2>&1 | tee -a compile.log
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.log
@ -1,8 +1,9 @@
 Vivado Simulator 2018.2
 Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
-Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log 
+Running: /usr/local/insa/Xilinx.VIVADO/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log 
 Using 8 slave threads.
 Starting static elaboration
 WARNING: [VRFC 10-122] controlunit remains a black-box since it has no binding entity [/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd:325]
 Completed static elaboration
 Starting simulation data flow analysis
 Completed simulation data flow analysis
@ -13,6 +14,15 @@ Compiling package ieee.std_logic_1164
 Compiling package ieee.std_logic_arith
 Compiling package ieee.std_logic_unsigned
 Compiling package ieee.numeric_std
 Compiling architecture behavioral of entity xil_defaultlib.IP [ip_default]
 Compiling architecture behavioral of entity xil_defaultlib.InstructionMemory [instructionmemory_default]
 Compiling architecture behavioral of entity xil_defaultlib.Stage_Li_Di [stage_li_di_default]
 Compiling architecture behavioral of entity xil_defaultlib.Registers [registers_default]
 Compiling architecture behavioral of entity xil_defaultlib.Stage_Di_Ex [stage_di_ex_default]
 Compiling architecture behavioral of entity xil_defaultlib.ALU [alu_default]
-Compiling architecture behavioral of entity xil_defaultlib.test_alu
+Compiling architecture behavioral of entity xil_defaultlib.Stage_Ex_Mem [stage_ex_mem_default]
-Built simulation snapshot Test_Alu_behav
+Compiling architecture behavioral of entity xil_defaultlib.DataMemory [datamemory_default]
 Compiling architecture behavioral of entity xil_defaultlib.Stage_Mem_Re [stage_mem_re_default]
 Compiling architecture behavioral of entity xil_defaultlib.Pipeline [pipeline_default]
 Compiling architecture behavioral of entity xil_defaultlib.test_total
 Built simulation snapshot Test_total_behav
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
@ -6,7 +6,7 @@
 # Simulator   : Xilinx Vivado Simulator
 # Description : Script for elaborating the compiled design
 #
-# Generated by Vivado on Mon May 29 21:15:04 CEST 2023
+# Generated by Vivado on Mon May 29 21:56:45 CEST 2023
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 #
 # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
 exit $RETVAL
 fi
 }
-ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu -log elaborate.log
+ExecStep xelab -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_total_behav xil_defaultlib.Test_total -log elaborate.log
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.log
@ -1,2 +0,0 @@
 Vivado Simulator 2018.2
 Time resolution is 1 ps
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
@ -6,7 +6,7 @@
 # Simulator   : Xilinx Vivado Simulator
 # Description : Script for simulating the design by launching the simulator
 #
-# Generated by Vivado on Mon May 29 21:15:06 CEST 2023
+# Generated by Vivado on Mon May 29 21:56:47 CEST 2023
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 #
 # Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
@ -23,4 +23,4 @@ then
 exit $RETVAL
 fi
 }
-ExecStep xsim Test_Alu_behav -key {Behavioral:sim_1:Functional:Test_Alu} -tclbatch Test_Alu.tcl -view /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log
+ExecStep xsim Test_total_behav -key {Behavioral:sim_1:Functional:Test_total} -tclbatch Test_total.tcl -view /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/Test_Alu_behav.wcfg -log simulate.log
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
@ -2,11 +2,11 @@
 # Webtalk v2018.2 (64-bit)
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
-# Start of session at: Mon May 29 19:45:48 2023
+# Start of session at: Mon May 29 21:55:04 2023
-# Process ID: 341146
+# Process ID: 509586
-# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
+# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
-# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
+# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
-# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
+# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
-# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
+# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
 #-----------------------------------------------------------
-source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
+source /home/rlacroix/Bureau/4ir/syst -notrace
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
@ -2,12 +2,13 @@
 # Webtalk v2018.2 (64-bit)
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
-# Start of session at: Mon May 29 19:45:48 2023
+# Start of session at: Mon May 29 21:55:04 2023
-# Process ID: 341146
+# Process ID: 509586
-# Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
+# Current directory: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
-# Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
+# Command line: wbtcv -mode batch -source /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_total_behav/webtalk/xsim_webtalk.tcl -notrace
-# Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
+# Log file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
-# Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
+# Journal file: /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
 #-----------------------------------------------------------
-source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
+source /home/rlacroix/Bureau/4ir/syst -notrace
-INFO: [Common 17-206] Exiting Webtalk at Mon May 29 19:45:49 2023...
+couldn't read file "/home/rlacroix/Bureau/4ir/syst": no such file or directory
 INFO: [Common 17-206] Exiting Webtalk at Mon May 29 21:55:04 2023...
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.jou
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.jou
@ -1,12 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.2 (64-bit)
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
 # Start of session at: Sun May 14 22:27:26 2023
 # Process ID: 831441
 # Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
 # Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
 # Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
 #-----------------------------------------------------------
 source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk_831441.backup.log
@ -1,13 +0,0 @@
 #-----------------------------------------------------------
 # Webtalk v2018.2 (64-bit)
 # SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
 # IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
 # Start of session at: Sun May 14 22:27:26 2023
 # Process ID: 831441
 # Current directory: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim
 # Command line: wbtcv -mode batch -source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
 # Log file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.log
 # Journal file: /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/webtalk.jou
 #-----------------------------------------------------------
 source /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl -notrace
 INFO: [Common 17-206] Exiting Webtalk at Sun May 14 22:27:27 2023...
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xelab.pb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
@ -1,5 +1,5 @@
 1685381189
 1685382347
-79
+77
 1
 aef36ef3a0d94dac9e6058b656907afd
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
@ -1,6 +1,6 @@
-webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
+webtalk_init -webtalk_dir /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
 webtalk_register_client -client project
-webtalk_add_data -client project -key date_generated -value "Mon May 29 21:38:21 2023" -context "software_version_and_target_device"
+webtalk_add_data -client project -key date_generated -value "Mon May 29 21:48:24 2023" -context "software_version_and_target_device"
 webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
 webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -12,21 +12,31 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con
 webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device"
 webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device"
 webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
-webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device"
+webtalk_add_data -client project -key random_id -value "6ef722b6-53ec-42dc-bc5c-9d79054a9923" -context "software_version_and_target_device"
 webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
-webtalk_add_data -client project -key project_iteration -value "78" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_iteration -value "76" -context "software_version_and_target_device"
 webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
 webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
 webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
-webtalk_add_data -client project -key cpu_speed -value "900.000 MHz" -context "user_environment"
+webtalk_add_data -client project -key cpu_speed -value "1000.000 MHz" -context "user_environment"
 webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
 webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
 webtalk_register_client -client xsim
-webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key File_Counter -value "10" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
+webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Simulation_Time -value "0.04_sec" -context "xsim\\usage"
+webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Simulation_Memory -value "122616_KB" -context "xsim\\usage"
+webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
-webtalk_transmit -clientid 3933579741 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
+webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
 webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
 webtalk_add_data -client xsim -key Simulation_Image_Code -value "47 KB" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Simulation_Image_Data -value "2 KB" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Total_Processes -value "5" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Total_Instances -value "8" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip " -context "xsim\\usage"
 webtalk_add_data -client xsim -key Compiler_Time -value "1.16_sec" -context "xsim\\usage"
 webtalk_add_data -client xsim -key Compiler_Memory -value "200496_KB" -context "xsim\\usage"
 webtalk_transmit -clientid 3254441618 -regid "" -xml /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
 webtalk_terminate
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
@ -1,6 +1,6 @@
 { 
-    crc :  5457071051479180310  , 
+    crc :  3751694400990100050  , 
    ccp_crc :  0  , 
    cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" , 
    buildDate : "Jun 14 2018" , 
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
@ -1,7 +1,4 @@
-Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 55247
+Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 49525
 Design successfully loaded
 Design Loading Memory Usage: 32680 KB (Peak: 32740 KB)
-Design Loading CPU Usage: 30 ms
+Design Loading CPU Usage: 20 ms
 Simulation completed
 Simulation Memory Usage: 122616 KB (Peak: 179952 KB)
 Simulation CPU Usage: 40 ms
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/datamemory.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/instructionmemory.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ip.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pipeline.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/registers.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_di_ex.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_ex_mem.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_li_di.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/stage_mem_re.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@ -2,5 +2,15 @@
 2018.2
 Jun 14 2018
 20:07:38
-/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685387697,vhdl,,,,test_alu,,,,,,,,
+/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685389246,vhdl,,,,test_alu,,,,,,,,
-/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685387202,vhdl,,,,alu,,,,,,,,
+/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd,1685390194,vhdl,,,,test_total,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685389246,vhdl,,,,alu,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/IP.vhd,1685386043,vhdl,,,,ip,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/InstructionMemory.vhd,1685386043,vhdl,,,,instructionmemory,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Memory.vhd,1685386043,vhdl,,,,datamemory,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd,1685388854,vhdl,,,,pipeline,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Registers.vhd,1685386043,vhdl,,,,registers,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Di_Ex.vhd,1685386043,vhdl,,,,stage_di_ex,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Ex_Mem.vhd,1685386043,vhdl,,,,stage_ex_mem,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Li_Di.vhd,1685386043,vhdl,,,,stage_li_di,,,,,,,,
 /home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/Stage_Mem_Re.vhd,1685386043,vhdl,,,,stage_mem_re,,,,,,,,
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.log
@ -1,2 +1,2 @@
-INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib
-INFO: [VRFC 10-307] analyzing entity Test_Alu
+INFO: [VRFC 10-307] analyzing entity Test_total
--- a/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb
+++ b/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xvhdl.pb
--- a/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd
+++ b/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd
@ -0,0 +1,64 @@
 ----------------------------------------------------------------------------------
 -- Company: 
 -- Engineer: 
 -- 
 -- Create Date: 12.05.2023 17:40:52
 -- Design Name: 
 -- Module Name: Test_Alu - Behavioral
 -- Project Name: 
 -- Target Devices: 
 -- Tool Versions: 
 -- Description: 
 -- 
 -- Dependencies: 
 -- 
 -- Revision:
 -- Revision 0.01 - File Created
 -- Additional Comments:
 -- 
 ----------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 -- Uncomment the following library declaration if using
 -- arithmetic functions with Signed or Unsigned values
 --use IEEE.NUMERIC_STD.ALL;
 -- Uncomment the following library declaration if instantiating
 -- any Xilinx leaf cells in this code.
 --library UNISIM;
 --use UNISIM.VComponents.all;
 entity Test_total is
 --  Port ( );
 end Test_total;
 architecture Behavioral of test_total is
    component Pipeline
    Port ( Clk : in STD_LOGIC);
    end component;
    constant clock_period : time := 10 ns;
    signal clock : Std_logic := '0';
    signal A : Std_logic := '0';
 begin
 -- instantiate 
 Pl : Pipeline PORT MAP (
    Clk => clock
 );
 Clock_process : process
 begin
    clock <= not(clock);
    wait for 100ns;
 end process;
 A <= not A;
 end Behavioral;
--- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
+++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
@ -38,7 +38,7 @@ end Pipeline;
 architecture Behavioral of Pipeline is
    component IP is
-    port ( CK : in STD_LOGIC;
+    port ( CLK : in STD_LOGIC;
           RST : in STD_LOGIC; -- rst when 0
           LOAD : in STD_LOGIC;
           EN : in STD_LOGIC; -- enable when 1
@ -106,7 +106,7 @@ architecture Behavioral of Pipeline is
    component ALU
    Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
           B : in STD_LOGIC_VECTOR (7 downto 0);
-           Ctrl_Alu : in STD_LOGIC_VECTOR (2 downto 0); -- 000 + / 001 - / 010 * / 100 Div 
+           Ctrl_Alu : in STD_LOGIC_VECTOR (7 downto 0);
           S : out STD_LOGIC_VECTOR (7 downto 0);
           N : out STD_LOGIC;
           O : out STD_LOGIC;
@ -166,10 +166,11 @@ architecture Behavioral of Pipeline is
    signal Re_W : STD_LOGIC;
    -- to control jumping and where to jump
-    signal addr_to_jump : STD_LOGIC;
+    signal addr_to_jump : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
    signal jump : STD_LOGIC;
    signal nop_Cntrl : STD_LOGIC;
    signal OP_LI_DI : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
 begin
 -- instructionPointer
@ -177,7 +178,7 @@ inst_point : IP port map (
    CLK=> clk, 
    Dout=> IP_out, 
    Din => addr_to_jump, 
-    RST => "1", 
+    RST => '1', 
    EN => nop_Cntrl, 
    LOAD => jump);
@ -202,9 +203,9 @@ Stage1 : Stage_Li_Di PORT MAP (
 -- Registers
 StageRegisters : Registers PORT MAP (
-    Addr_A => Di_B,
+    Addr_A => Di_B(3 downto 0), -- becquse the registers are on 4 bits
-    Addr_B => Di_C,
+    Addr_B => Di_C(3 downto 0),
-    Addr_W => Re_A,
+    Addr_W => Re_A(3 downto 0),
    W => Re_W,
    Data => Re_B,
    Rst => Rst,
@ -296,11 +297,8 @@ Ex_FinalB <= Ex_B when
    else Ex_Res_Alu;
 -- LC pre ALU
-Ex_Ctrl_ALu <= "000" when Ex_Op = x"01" --ADD
+Ex_Ctrl_ALu <= x"00" when Ex_Op = x"05" or Ex_Op = x"06" or Ex_Op = x"07" or Ex_Op = x"08" --(not using ALU)
-    else "001" when Ex_Op = x"03" -- SUB
+    else Ex_Op;
    else "010" when Ex_Op = x"02" -- MUL
    else "100" when Ex_Op = x"04" -- DIV
    else "111"; --ERROR
 -- Mux post data memory
 Mem_FinalB <= Mem_B when 
@ -325,13 +323,13 @@ Re_W <= '0' when Re_Op = x"08" --STORE
    else '1'; 
 CU : ControlUnit port map (
-    Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op;
+    Op_DI => Li(31 downto 24), Op_EX => Di_Op, Op_Mem => Ex_Op,
-    A_EX =< Di_A, A_Mem => Ex_A;
+    A_EX => Di_A, A_Mem => Ex_A,
-    B_DI => Li(15 downto 8);
+    B_DI => Li(15 downto 8),
-    C_DI => Li(7 downto 0);
+    C_DI => Li(7 downto 0),
    CNTRL => nop_Cntrl);
 end Behavioral;
 -- in case of alea : replace li(31 downto 24) by NOP
- OP_LI_DI<= X"ff" when nop_Cntrl='1' else li(31 downto 24);
+ OP_LI_DI <= X"ff" when nop_Cntrl='1' else Li(31 downto 24);
 end Behavioral;
--- a/VHDL/ALU/ALU.xpr
+++ b/VHDL/ALU/ALU.xpr
@ -3,7 +3,7 @@
 <!--                                                         -->
 <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
-<Project Version="7" Minor="38" Path="/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr">
+<Project Version="7" Minor="38" Path="/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.xpr">
  <DefaultLaunch Dir="$PRUNDIR"/>
  <Configuration>
    <Option Name="Id" Val="aef36ef3a0d94dac9e6058b656907afd"/>
@ -33,7 +33,7 @@
    <Option Name="DSAVendor" Val="xilinx"/>
    <Option Name="DSABoardId" Val="basys3"/>
    <Option Name="DSANumComputeUnits" Val="60"/>
-    <Option Name="WTXSimLaunchSim" Val="67"/>
+    <Option Name="WTXSimLaunchSim" Val="73"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>
@ -135,8 +135,15 @@
    </FileSet>
    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
      <Filter Type="Srcs"/>
      <File Path="$PSRCDIR/sim_1/new/test_total.vhd">
        <FileInfo>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
      </File>
      <File Path="$PSRCDIR/sim_1/new/VHDL.vhd">
        <FileInfo>
          <Attr Name="AutoDisabled" Val="1"/>
          <Attr Name="UsedIn" Val="synthesis"/>
          <Attr Name="UsedIn" Val="simulation"/>
        </FileInfo>
@ -148,9 +155,8 @@
      </File>
      <Config>
        <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="Test_Alu"/>
+        <Option Name="TopModule" Val="Test_total"/>
        <Option Name="TopLib" Val="xil_defaultlib"/>
        <Option Name="TopAutoSet" Val="TRUE"/>
        <Option Name="TransportPathDelay" Val="0"/>
        <Option Name="TransportIntDelay" Val="0"/>
        <Option Name="SrcSet" Val="sources_1"/>
@ -185,7 +191,9 @@
  <Runs Version="1" Minor="10">
    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
          <Desc>Vivado Synthesis Defaults</Desc>
        </StratHandle>
        <Step Id="synth_design"/>
      </Strategy>
      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@ -194,7 +202,9 @@
    </Run>
    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
      <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
          <Desc>Default settings for Implementation.</Desc>
        </StratHandle>
        <Step Id="init_design"/>
        <Step Id="opt_design"/>
        <Step Id="power_opt_design"/>
		`@ -1,2 +0,0 @@`
			`Vivado Simulator 2018.2`
			`Time resolution is 1 ps`
`@ -1,2 +1,2 @@`
	`INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib`	`INFO: [VRFC 10-163] Analyzing VHDL file "/home/rlacroix/Bureau/4ir/syst info/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/test_total.vhd" into library xil_defaultlib`
	`INFO: [VRFC 10-307] analyzing entity Test_Alu`	`INFO: [VRFC 10-307] analyzing entity Test_total`