updated opcodes

2023-05-29 23:43:05 +02:00 · 2023-05-29 23:43:05 +02:00 · 8f5be60008
--- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
+++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
@ -279,6 +279,8 @@ Stage4 : Stage_Mem_Re PORT MAP (
    -- NOT    x"0C"
    -- AND    x"0D"
    -- OR     x"0E"
+    -- JMP    x"0F"
+    -- JMF    x"10"
    -- NOP    x"FF"