added more operand (again)

2023-05-29 23:45:26 +02:00 · 2023-05-29 23:45:26 +02:00 · 3885da0ea5
commit 3885da0ea5
parent e621b754bf
1 changed files with 3 additions and 1 deletions
--- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
+++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
@ -281,9 +281,11 @@ Stage4 : Stage_Mem_Re PORT MAP (
    -- OR     x"0E"
    -- JMP    x"0F"
    -- JMF    x"10"
+    -- CAL    x"11"
+    -- RET    x"12"
+    -- PRI    x"13"
    -- NOP    x"FF"
    
-    
 -- Mux post registers 
 Di_FinalB <= Di_B when 
    Di_OP = x"06" -- AFC