From 3885da0ea54a85177f27ddb15fdbb445ba81c96f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rapha=C3=ABl=20LACROIX?= Date: Mon, 29 May 2023 23:45:26 +0200 Subject: [PATCH] added more operand (again) --- VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd index 8e9d5fd..39c1a46 100644 --- a/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd +++ b/VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd @@ -281,9 +281,11 @@ Stage4 : Stage_Mem_Re PORT MAP ( -- OR x"0E" -- JMP x"0F" -- JMF x"10" + -- CAL x"11" + -- RET x"12" + -- PRI x"13" -- NOP x"FF" - -- Mux post registers Di_FinalB <= Di_B when Di_OP = x"06" -- AFC