rlacroix/Projet-Systemes-Informatiques
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

added more operand (again)

Browse source
This commit is contained in:
Raphaël LACROIX 2023-05-29 23:45:26 +02:00
parent e621b754bf
commit 3885da0ea5
1 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
VHDL/ALU/ALU.srcs/sources_1/new/Pipeline.vhd
View file

@ -281,9 +281,11 @@ Stage4 : Stage_Mem_Re PORT MAP (
-- OR x"0E" -- OR x"0E"
-- JMP x"0F" -- JMP x"0F"
-- JMF x"10" -- JMF x"10"
-- CAL x"11"
-- RET x"12"
-- PRI x"13"
-- NOP x"FF" -- NOP x"FF"
-- Mux post registers -- Mux post registers
Di_FinalB <= Di_B when Di_FinalB <= Di_B when
Di_OP = x"06" -- AFC Di_OP = x"06" -- AFC