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alejeune 2023-05-29 21:39:05 +02:00
parent 873502243b
commit 134db4c2c9
30 changed files with 120 additions and 74 deletions
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26
VHDL/ALU/ALU.cache/wt/gui_handlers.wdf
View file

@ -2,7 +2,7 @@ version:1
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@ -10,14 +10,14 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:323133:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3333:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3235:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:3436:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f6f7574:3236:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:31:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68706f7075707469746c655f636c6f7365:31:00:00
@ -27,13 +27,13 @@ version:1
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6c6f6770616e656c5f70617573655f6f7574707574:32:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:3134:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f65646974:3136:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:37:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3630:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3634:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f666c6f77:38:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:39:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73657474696e6773:32:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:3132:00:00
@ -51,7 +51,7 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:33:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3539:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:3634:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7372635f7265706c6163655f66696c65:35:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f646576696365:31:00:00
@ -59,7 +59,7 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7361766570726f6a6563747574696c735f73617665:34:00:00
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@ -68,10 +68,10 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73746174656d6f6e69746f725f72657365745f72756e:31:00:00
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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:34:00:00
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636173746174656d6f6e69746f725f63616e63656c:31:00:00
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eof:1336689854
eof:805443714

6
VHDL/ALU/ALU.cache/wt/java_command_handlers.wdf
View file

@ -1,6 +1,6 @@
version:1
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@ -8,8 +8,8 @@ version:1
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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:33:00:00
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:3538:00:00
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70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
eof:2907318966
eof:1280488146

2
VHDL/ALU/ALU.cache/wt/project.wpc
View file

@ -1,3 +1,3 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:16
6d6f64655f636f756e7465727c4755494d6f6465:18
eof:

34
VHDL/ALU/ALU.cache/wt/webtalk_pa.xml
View file

@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon May 29 20:28:54 2023">
<application name="pa" timeStamp="Mon May 29 21:38:21 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="489b0519ba8b4bcea2b75f67f8ebbc30" type="ProjectID"/>
<property name="ProjectIteration" value="4" type="ProjectIteration"/>
@ -18,7 +18,7 @@ This means code written to parse this file will need to be revisited each subseq
</item>
<item name="Java Command Handlers">
<property name="AddSources" value="15" type="JavaHandler"/>
<property name="CloseProject" value="1" type="JavaHandler"/>
<property name="CloseProject" value="2" type="JavaHandler"/>
<property name="EditDelete" value="2" type="JavaHandler"/>
<property name="NewProject" value="1" type="JavaHandler"/>
<property name="OpenProject" value="2" type="JavaHandler"/>
@ -26,7 +26,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="RunSynthesis" value="6" type="JavaHandler"/>
<property name="ShowView" value="4" type="JavaHandler"/>
<property name="SimulationRelaunch" value="3" type="JavaHandler"/>
<property name="SimulationRun" value="58" type="JavaHandler"/>
<property name="SimulationRun" value="63" type="JavaHandler"/>
<property name="ToolsSettings" value="5" type="JavaHandler"/>
<property name="UpdateSourceFiles" value="5" type="JavaHandler"/>
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
@ -35,7 +35,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="AbstractCombinedPanel_ADD_ELEMENT" value="36" type="GuiHandlerData"/>
<property name="AbstractCombinedPanel_REMOVE_SELECTED_ELEMENTS" value="13" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="47" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="50" type="GuiHandlerData"/>
<property name="CmdMsgDialog_MESSAGES" value="4" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="19" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OPEN_MESSAGES_VIEW" value="1" type="GuiHandlerData"/>
@ -43,14 +43,14 @@ This means code written to parse this file will need to be revisited each subseq
<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="148" type="GuiHandlerData"/>
<property name="DefineModulesDialog_ENTITY_NAME" value="3" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="213" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="239" type="GuiHandlerData"/>
<property name="FileSetPanel_MESSAGES" value="1" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="72" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="77" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_FIT" value="2" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="33" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="25" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_IN" value="46" type="GuiHandlerData"/>
<property name="GraphicalView_ZOOM_OUT" value="26" type="GuiHandlerData"/>
<property name="HCodeEditor_CLOSE" value="2" type="GuiHandlerData"/>
<property name="HCodeEditor_SEARCH_TEXT_COMBO_BOX" value="1" type="GuiHandlerData"/>
<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>
@ -60,13 +60,13 @@ This means code written to parse this file will need to be revisited each subseq
<property name="LogPanel_PAUSE_OUTPUT" value="2" type="GuiHandlerData"/>
<property name="LogPanel_TOGGLE_COLUMN_SELECTION_MODE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_CHECKPOINT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="14" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="16" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="7" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="60" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="64" type="GuiHandlerData"/>
<property name="MainMenuMgr_FLOW" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="9" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="20" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="40" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="22" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="43" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_SIMULATION_WAVEFORM" value="12" type="GuiHandlerData"/>
@ -84,7 +84,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PACommandNames_LOG_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RUN_SYNTHESIS" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RELAUNCH" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="59" type="GuiHandlerData"/>
<property name="PACommandNames_SIMULATION_RUN_BEHAVIORAL" value="64" type="GuiHandlerData"/>
<property name="PACommandNames_SRC_REPLACE_FILE" value="5" type="GuiHandlerData"/>
<property name="PAViews_CODE" value="19" type="GuiHandlerData"/>
<property name="PAViews_DEVICE" value="1" type="GuiHandlerData"/>
@ -92,7 +92,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ProjectSettingsGadget_EDIT_PROJECT_SETTINGS" value="2" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="2" type="GuiHandlerData"/>
<property name="RDICommands_SAVE_FILE" value="10" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="100" type="GuiHandlerData"/>
<property name="RDIViews_WAVEFORM_VIEWER" value="110" type="GuiHandlerData"/>
<property name="RTLOptionsPanel_SELECT_TOP_MODULE_OF_YOUR_DESIGN" value="2" type="GuiHandlerData"/>
<property name="SaveProjectUtils_SAVE" value="4" type="GuiHandlerData"/>
<property name="SettingsDialog_PROJECT_TREE" value="1" type="GuiHandlerData"/>
@ -101,7 +101,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SrcChooserPanel_CREATE_FILE" value="13" type="GuiHandlerData"/>
<property name="SrcMenu_IP_HIERARCHY" value="2" type="GuiHandlerData"/>
<property name="StateMonitor_RESET_RUN" value="1" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="3" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="4" type="GuiHandlerData"/>
<property name="SyntheticaStateMonitor_CANCEL" value="1" type="GuiHandlerData"/>
<property name="TclConsoleView_TCL_CONSOLE_CODE_EDITOR" value="1" type="GuiHandlerData"/>
<property name="WaveformNameTree_WAVEFORM_NAME_TREE" value="42" type="GuiHandlerData"/>
@ -109,9 +109,9 @@ This means code written to parse this file will need to be revisited each subseq
<property name="WaveformView_NEXT_MARKER" value="2" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="21" type="GuiMode"/>
<property name="GuiMode" value="22" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="15" type="TclMode"/>
<property name="TclMode" value="16" type="TclMode"/>
</item>
</section>
</application>

2
VHDL/ALU/ALU.runs/synth_1/gen_run.xml
View file

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1684097307">
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="PA-TCL" Name="ALU.tcl"/>
<File Type="RDS-DCP" Name="ALU.dcp"/>
<File Type="REPORTS-TCL" Name="ALU_reports.tcl"/>
<File Type="RDS-RDS" Name="ALU.vds"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/Test_Alu_behav.wdb
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14
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.log
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@ -169,3 +169,17 @@ INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity ALU
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu
INFO: [VRFC 10-163] Analyzing VHDL file "/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd" into library xil_defaultlib
INFO: [VRFC 10-307] analyzing entity Test_Alu

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/compile.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Mon May 29 20:22:53 CEST 2023
# Generated by Vivado on Mon May 29 21:15:03 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/elaborate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Mon May 29 20:22:55 CEST 2023
# Generated by Vivado on Mon May 29 21:15:04 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/simulate.sh
View file

@ -6,7 +6,7 @@
# Simulator : Xilinx Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Mon May 29 20:22:56 CEST 2023
# Generated by Vivado on Mon May 29 21:15:06 CEST 2023
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
#
# Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_0.lnx64.o
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4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.c
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@ -55,8 +55,8 @@ const int NumRelocateId= 6;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/Test_Alu_behav/xsim.reloc", (void **)funcTab, 6);
iki_vhdl_file_variable_register(dp + 3800);
iki_vhdl_file_variable_register(dp + 3856);
iki_vhdl_file_variable_register(dp + 3576);
iki_vhdl_file_variable_register(dp + 3632);
/*Populate the transaction function pointer field in the whole net structure */

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/obj/xsim_1.lnx64.o
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2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/.xsim_webtallk.info
View file

@ -1,5 +1,5 @@
1685381189
1685382347
69
79
1
aef36ef3a0d94dac9e6058b656907afd

12
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/xsim_webtalk.tcl
View file

@ -1,6 +1,6 @@
webtalk_init -webtalk_dir /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/
webtalk_register_client -client project
webtalk_add_data -client project -key date_generated -value "Mon May 29 20:28:58 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key date_generated -value "Mon May 29 21:38:21 2023" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.2 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2258646" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "LIN64" -context "software_version_and_target_device"
@ -14,11 +14,11 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "48ade6b1-45bb-42c1-b620-33b3e004d501" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "aef36ef3a0d94dac9e6058b656907afd" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "68" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_iteration -value "78" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Ubuntu" -context "user_environment"
webtalk_add_data -client project -key os_release -value "Ubuntu 20.04.6 LTS" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) Silver 4216 CPU @ 2.10GHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "800.000 MHz" -context "user_environment"
webtalk_add_data -client project -key cpu_speed -value "900.000 MHz" -context "user_environment"
webtalk_add_data -client project -key total_processors -value "2" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "134.000 GB" -context "user_environment"
webtalk_register_client -client xsim
@ -26,7 +26,7 @@ webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command
webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
webtalk_add_data -client xsim -key runtime -value "1 us" -context "xsim\\usage"
webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Time -value "0.03_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "122620_KB" -context "xsim\\usage"
webtalk_transmit -clientid 1496851547 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_add_data -client xsim -key Simulation_Time -value "0.04_sec" -context "xsim\\usage"
webtalk_add_data -client xsim -key Simulation_Memory -value "122616_KB" -context "xsim\\usage"
webtalk_transmit -clientid 3933579741 -regid "" -xml /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.xml -html /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.html -wdm /home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "<H3>XSIM Usage Report</H3><BR>"
webtalk_terminate

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.dbg
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.mem
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.reloc
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2
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rlx
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@ -1,6 +1,6 @@
{
crc : 5165304247125619484 ,
crc : 5457071051479180310 ,
ccp_crc : 0 ,
cmdline : " -wto aef36ef3a0d94dac9e6058b656907afd --incr --debug typical --relax --mt 8 -L xil_defaultlib -L secureip --snapshot Test_Alu_behav xil_defaultlib.Test_Alu" ,
buildDate : "Jun 14 2018" ,

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.rtti
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.type
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsim.xdbg
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimk
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10
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/Test_Alu_behav/xsimkernel.log
View file

@ -1,7 +1,7 @@
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 59047
Running: xsim.dir/Test_Alu_behav/xsimk -simmode gui -wdb Test_Alu_behav.wdb -simrunnum 0 -socket 55247
Design successfully loaded
Design Loading Memory Usage: 32684 KB (Peak: 32736 KB)
Design Loading CPU Usage: 20 ms
Design Loading Memory Usage: 32680 KB (Peak: 32740 KB)
Design Loading CPU Usage: 30 ms
Simulation completed
Simulation Memory Usage: 122620 KB (Peak: 179956 KB)
Simulation CPU Usage: 30 ms
Simulation Memory Usage: 122616 KB (Peak: 179952 KB)
Simulation CPU Usage: 40 ms

BIN
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.vdb
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VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/test_alu.vdb
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4
VHDL/ALU/ALU.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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@ -2,5 +2,5 @@
2018.2
Jun 14 2018
20:07:38
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685384562,vhdl,,,,test_alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685384160,vhdl,,,,alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd,1685387697,vhdl,,,,test_alu,,,,,,,,
/home/alejeune/Documents/4ir/S2/Projet/Projet-Systemes-Informatiques/VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd,1685387202,vhdl,,,,alu,,,,,,,,

49
VHDL/ALU/ALU.srcs/sim_1/new/VHDL.vhd
View file

@ -80,7 +80,14 @@ instance : ALU PORT MAP (
local_Ctrl_Alu <= x"01", -- ADD
x"02" after 40 ns, -- MUL
x"03" after 60 ns, -- SUB
x"04" after 90 ns; -- DIV
x"04" after 90 ns, -- DIV
x"09" after 120 ns, -- INF
x"0A" after 140 ns, -- SUP
x"0B" after 160 ns, -- EQ
x"0C" after 180 ns, -- NOT
x"0D" after 210 ns, -- XOR
x"0E" after 240 ns, -- OR
x"0F" after 270 ns; -- XOR
local_A <= x"00",
x"00" after 10 ns,
@ -91,8 +98,23 @@ local_A <= x"00",
x"0B" after 60 ns,
x"0F" after 70 ns,
x"19" after 80 ns,
x"18" after 90 ns,
x"19" after 100 ns;
x"12" after 90 ns,
x"18" after 100 ns,
x"19" after 110 ns,
x"10" after 120 ns,
x"20" after 130 ns,
x"10" after 150 ns,
x"0A" after 160 ns,
x"0B" after 170 ns,
x"01" after 180 ns,
x"25" after 190 ns,
x"00" after 200 ns,
x"0A" after 210 ns,
x"00" after 230 ns,
x"0A" after 240 ns,
x"00" after 260 ns,
x"0A" after 270 ns,
x"00" after 290 ns;
local_B <= x"00",
x"00" after 10 ns,
@ -103,10 +125,21 @@ local_B <= x"00",
x"0B" after 60 ns,
x"12" after 70 ns,
x"0B" after 80 ns,
x"06" after 90 ns,
x"07" after 100 ns;
x"00" after 90 ns,
x"06" after 100 ns,
x"07" after 110 ns,
x"20" after 120 ns,
x"10" after 130 ns,
x"20" after 150 ns,
x"0A" after 160 ns,
x"02" after 170 ns,
x"00" after 190 ns,
x"0B" after 210 ns,
x"00" after 220 ns,
x"0B" after 240 ns,
x"00" after 250 ns,
x"0B" after 270 ns,
x"00" after 280 ns;
end Behavioral;

6
VHDL/ALU/ALU.srcs/sources_1/new/ALU.vhd
View file

@ -77,9 +77,9 @@ begin
when x"0A" => if A > B then res <= x"0001"; else res <= x"0000"; end if;
when x"0B" => if A = B then res <= x"0001"; else res <= x"0000"; end if;
when x"0C" => if A > 0 then res <= x"0000"; else res <= x"0001"; end if;
when x"0D" => res <= A or B;
when x"0E" => res <= A and B;
when x"0F" => res <= A xor B;
when x"0D" => if (A > 0 and B > 0) then res <= x"0001" ; else res <= x"0000"; end if;
when x"0E" => if (A > 0 or B > 0) then res <= x"0001" ; else res <= x"0000"; end if;
when x"0F" => if ((A > 0 and B = 0) or (A = 0 and B >0)) then res <= x"0001" ; else res <= x"0000"; end if;
when others => res <= x"0000";
end case;
end process;

15
VHDL/ALU/ALU.xpr
View file

@ -33,7 +33,7 @@
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="basys3"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="62"/>
<Option Name="WTXSimLaunchSim" Val="67"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@ -67,6 +67,12 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/InstructionMemory.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
@ -115,13 +121,6 @@
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/IP.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="Pipeline"/>