Initial commit

.gitignore

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+gradlew
+gradlew.bat
+gradle/*
+build/*
+.gradle/*

.idea/.gitignore

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+# Default ignored files
+/shelf/
+/workspace.xml

.idea/compiler.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="CompilerConfiguration">
+    <bytecodeTargetLevel target="11" />
+  </component>
+</project>

.idea/gradle.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="GradleMigrationSettings" migrationVersion="1" />
+  <component name="GradleSettings">
+    <option name="linkedExternalProjectsSettings">
+      <GradleProjectSettings>
+        <option name="distributionType" value="DEFAULT_WRAPPED" />
+        <option name="externalProjectPath" value="$PROJECT_DIR$" />
+        <option name="modules">
+          <set>
+            <option value="$PROJECT_DIR$" />
+          </set>
+        </option>
+        <option name="useQualifiedModuleNames" value="true" />
+      </GradleProjectSettings>
+    </option>
+  </component>
+</project>

.idea/jarRepositories.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="RemoteRepositoriesConfiguration">
+    <remote-repository>
+      <option name="id" value="central" />
+      <option name="name" value="Maven Central repository" />
+      <option name="url" value="https://repo1.maven.org/maven2" />
+    </remote-repository>
+    <remote-repository>
+      <option name="id" value="jboss.community" />
+      <option name="name" value="JBoss Community repository" />
+      <option name="url" value="https://repository.jboss.org/nexus/content/repositories/public/" />
+    </remote-repository>
+    <remote-repository>
+      <option name="id" value="MavenRepo" />
+      <option name="name" value="MavenRepo" />
+      <option name="url" value="https://repo.maven.apache.org/maven2/" />
+    </remote-repository>
+  </component>
+</project>

.idea/misc.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="ExternalStorageConfigurationManager" enabled="true" />
+  <component name="ProjectRootManager" version="2" languageLevel="JDK_11" default="true" project-jdk-name="11" project-jdk-type="JavaSDK">
+    <output url="file://$PROJECT_DIR$/out" />
+  </component>
+</project>

.idea/vcs.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<project version="4">
+  <component name="VcsDirectoryMappings">
+    <mapping directory="$PROJECT_DIR$" vcs="Git" />
+  </component>
+</project>

System.vhd

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+----------------------------------------------------------------------------------
+-- Company:  INSA-Toulouse
+-- Engineer: Paul Faure
+-- 
+-- Create Date: 13.04.2021 10:19:15
+-- Module Name: System - Behavioral
+-- Project Name: Processeur sécurisé
+-- Target Devices: Basys 3 ARTIX7
+-- Tool Versions: Vivado 2016.4
+-- Description: Environnement du processeur, mapping entre le processeur et les periphériques, affectation des ports la carte
+-- 
+-- Dependencies: 
+--    - Clock_Divider
+--    - Pipeline
+--    - Pipeline_NS
+--    - PeripheriqueEcran
+--    - PeripheriqueClavier
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Lien avec le fichier de contraintes 
+--   Récupération du VGA
+--   Récupération du PS2
+--   Récupération d'un bouton pour RST
+--   Récupération de la clock
+entity System is
+    Port ( vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
+           btnC : in STD_LOGIC;
+           CLK : in STD_LOGIC);
+end System;
+
+architecture Structural of System is
+
+    component Pipeline is
+    Generic (Nb_bits : Natural := 8;
+             Instruction_En_Memoire_Size : Natural := 29;
+             Addr_Memoire_Instruction_Size : Natural := 3;
+             Memoire_Instruction_Size : Natural := 8;
+             Instruction_Bus_Size : Natural := 5;
+             Nb_Instructions : Natural := 32;
+             Nb_Registres : Natural := 16;
+             Addr_registres_size : Natural := 4;
+             Memoire_Size : Natural := 32;
+             Adresse_mem_size : Natural := 5;
+             Memoire_Adresses_Retour_Size : Natural := 16;
+             Adresse_Memoire_Adresses_Retour_Size : Natural := 4);
+    Port (CLK : in STD_LOGIC;
+          RST : in STD_LOGIC;
+          STD_IN          : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_IN_Av       : in STD_LOGIC;
+          STD_IN_Request  : out STD_LOGIC;
+          STD_OUT         : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_OUT_Av      : out STD_LOGIC;
+          STD_OUT_Int     : out STD_LOGIC);
+    end component;
+
+    component Pipeline_NS is
+    Generic (Nb_bits : Natural := 8;
+             Instruction_En_Memoire_Size : Natural := 29;
+             Addr_Memoire_Instruction_Size : Natural := 3;
+             Memoire_Instruction_Size : Natural := 8;
+             Instruction_Bus_Size : Natural := 5;
+             Nb_Instructions : Natural := 32;
+             Nb_Registres : Natural := 16;
+             Addr_registres_size : Natural := 4;
+             Memoire_Size : Natural := 32;
+             Adresse_mem_size : Natural := 5);
+    Port (CLK : STD_LOGIC;
+          RST : STD_LOGIC;
+          STD_IN      : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_IN_Av   : in STD_LOGIC;
+          STD_IN_Request  : out STD_LOGIC;
+          STD_OUT     : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); 
+          STD_OUT_Av  : out STD_LOGIC;
+          STD_OUT_Int : out STD_LOGIC);
+    end component;
+    
+    component PeripheriqueEcran 
+    Generic ( Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           CLK_VGA : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           
+           vgaRed   : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaBlue  : out STD_LOGIC_VECTOR (3 downto 0);
+           vgaGreen : out STD_LOGIC_VECTOR (3 downto 0);
+           Hsync    : out STD_LOGIC;
+           Vsync    : out STD_LOGIC;
+                     
+           STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : in STD_LOGIC;
+           STD_OUT_Int : in STD_LOGIC);
+    end component;
+    
+    component PeripheriqueClavier 
+    Generic (Nb_Bits : Natural);
+    Port ( CLK : in STD_LOGIC;
+           RST : in STD_LOGIC;
+           PS2Clk : in STD_LOGIC;
+           PS2Data : in STD_LOGIC;
+           STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_IN_Av : out STD_LOGIC;
+           STD_IN_Request : in STD_LOGIC;
+           STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0);
+           STD_OUT_Av : out STD_LOGIC);
+    end component;
+    
+    component Clock_Divider is
+        Port ( CLK_IN : in STD_LOGIC;
+               CLK_OUT : out STD_LOGIC);
+    end component;
+    
+    -- signaux auxiliaires
+    signal my_RST : STD_LOGIC; -- Signal de RST (inversion par rapport au btnC)
+    signal my_CLK : STD_LOGIC; -- Signal de clock (divisée par rapport CLK)
+    -- signaux de gestion de l'entrée
+    signal STD_IN      : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');  -- Entrée
+    signal STD_IN_Av   : STD_LOGIC := '0';                                   -- Entrée disponible en lecture sur le clavier
+    signal STD_IN_Request  : STD_LOGIC := '0';                               -- Demande d'une entrée au clavier
+    -- signaux de gestion de la sortie
+    signal STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');               -- Sortie vers l'écran                                  
+    signal STD_OUT_Av  : STD_LOGIC := '0';                                                -- Sortie disponible pour l'écran
+    signal STD_OUT_Int : STD_LOGIC := '0';                                                -- Type de la sortie (entier ou ASCII) pour l'écran          
+    signal pipeline_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');      -- Sortie depuis le Pipeline                                    
+    signal pipeline_STD_OUT_Av  : STD_LOGIC := '0';                                       -- Sortie disponible depuis le Pipeline
+    signal pipeline_STD_OUT_Int : STD_LOGIC := '0';                                       -- Type de la sortie (entier ou ASCII) depuis le pipeline          
+    signal clavier_STD_OUT     : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');       -- Sortie depuis le Clavier                              
+    signal clavier_STD_OUT_Av  : STD_LOGIC := '0';                                        -- Sortie disponible depuis le Clavier                   
+    signal clavier_STD_OUT_Int : STD_LOGIC := '0';                                        -- Type de la sortie (entier ou ASCII) depuis le Clavier 
+    
+    constant SECURISED : boolean := false;  -- Booléen de sélection entre la version sécurisée et non sécurisée
+        
+begin    
+           
+    -- Diviseur de clock
+    clk_div : Clock_Divider
+    port map (CLK_IN => CLK,
+              CLK_OUT => my_CLK);
+              
+              
+    -- Generation du pipeline en fonction de la condition sécurisé ou non       
+    instance: if (SECURISED) generate
+        instance_securisee : entity work.Pipeline
+            generic map (Nb_bits => 16,
+                         Instruction_En_Memoire_Size => 53,
+                         Addr_Memoire_Instruction_Size => 9,
+                         Memoire_Instruction_Size => 512,
+                         Instruction_Bus_Size => 5,
+                         Nb_Instructions => 32,
+                         Nb_Registres => 16,
+                         Addr_registres_size => 4,
+                         Memoire_Size => 64,
+                         Adresse_mem_size => 6,
+                         Memoire_Adresses_Retour_Size => 4,
+                         Adresse_Memoire_Adresses_Retour_Size => 2)
+            port map (CLK => my_CLK,
+                      RST => my_RST,
+                      STD_IN      => STD_IN,
+                      STD_IN_Av   => STD_IN_Av,
+                      STD_IN_Request => STD_IN_Request,
+                      STD_OUT     => pipeline_STD_OUT,
+                      STD_OUT_Av  => pipeline_STD_OUT_Av,
+                      STD_OUT_Int => pipeline_STD_OUT_Int);
+    else generate
+        instance_non_securisee : entity work.Pipeline_NS
+            generic map (Nb_bits => 16,
+                         Instruction_En_Memoire_Size => 53,
+                         Addr_Memoire_Instruction_Size => 9,
+                         Memoire_Instruction_Size => 512,
+                         Instruction_Bus_Size => 5,
+                         Nb_Instructions => 32,
+                         Nb_Registres => 16,
+                         Addr_registres_size => 4,
+                         Memoire_Size => 64,
+                         Adresse_mem_size => 6)
+            port map (CLK => my_CLK,
+                      RST => my_RST,
+                      STD_IN      => STD_IN,
+                      STD_IN_Av   => STD_IN_Av,
+                      STD_IN_Request => STD_IN_Request,
+                      STD_OUT     => pipeline_STD_OUT,
+                      STD_OUT_Av  => pipeline_STD_OUT_Av,
+                      STD_OUT_Int => pipeline_STD_OUT_Int);
+    end generate;  
+    
+    instance_perif_ecran : PeripheriqueEcran 
+    generic map ( Nb_Bits => 16)
+    port map ( CLK => my_CLK,
+               CLK_VGA => CLK,
+               RST => my_RST,
+               
+               vgaRed   => vgaRed,
+               vgaBlue  => vgaBlue,
+               vgaGreen => vgaGreen,
+               Hsync    => Hsync,
+               Vsync    => Vsync,
+                         
+               STD_OUT =>     STD_OUT,
+               STD_OUT_Av =>  STD_OUT_Av,
+               STD_OUT_Int => STD_OUT_Int);
+               
+    instance_perif_clavier : PeripheriqueClavier 
+    generic map (Nb_Bits => 16)
+    port map ( CLK => my_CLK,
+               RST => my_RST,
+               PS2Clk => PS2Clk,
+               PS2Data => PS2Data,
+               STD_IN => STD_IN,
+               STD_IN_Av => STD_IN_Av,
+               STD_IN_Request => STD_IN_Request,
+               STD_OUT =>    clavier_STD_OUT,
+               STD_OUT_Av => clavier_STD_OUT_Av);
+          
+              
+    -- Gestion du RST (inversion d'état)
+    my_RST <= '1' when btnC = '0' else
+              '0';
+              
+    
+    -- Gestion de l'affichage sur l'écran lors d'une demande d'entrée le clavier affiche sur l'écran
+    STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT;
+    STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av;
+    STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int;
+    
+end Structural;
+

build.gradle

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+plugins {
+    id 'java'
+}
+
+group 'org.example'
+version '1.0-SNAPSHOT'
+
+repositories {
+    mavenCentral()
+}
+
+dependencies {
+    testCompile group: 'junit', name: 'junit', version: '4.12'
+}

settings.gradle

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+rootProject.name = 'ParserVHDL'
+

src/main/java/Affectation.java

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+public class Affectation {
+    private Signal signal1;
+    private Signal signal2;
+
+    public Affectation(Signal signal1, Signal signal2) {
+        this.signal1 = signal1;
+        this.signal2 = signal2;
+    }
+
+    public Signal getSignal1() {
+        return signal1;
+    }
+
+    public Signal getSignal2() {
+        return signal2;
+    }
+}

src/main/java/Component.java

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+import java.util.ArrayList;
+
+public class Component {
+    private Entity entity;
+    private ArrayList<Affectation> affectations;
+    private Entity entity2;
+    private ArrayList<Affectation> affectations2;
+    private Signal condition;
+    private boolean conditionnelle;
+
+    public Component(String entity, String affectations) {
+        this.entity = Entities.getEntity(entity);
+        // TODO Créer les affectations
+        this.conditionnelle = false;
+    }
+}

src/main/java/Entities.java

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+import java.util.ArrayList;
+
+public class Entities {
+    private static ArrayList<Entity> entities = new ArrayList<>();
+    private static ArrayList<String> entitiesNames = new ArrayList<>();
+
+    public static Entity getEntity(String name) {
+        if (! entitiesNames.contains(name)) {
+            entities.add(new Entity(name));
+            entitiesNames.add(name);
+        }
+        return entities.get(entitiesNames.indexOf(name));
+    }
+}

src/main/java/Entity.java

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+import java.io.File;
+import java.io.IOException;
+import java.util.ArrayList;
+import java.util.Arrays;
+import java.util.stream.Collectors;
+
+public class Entity {
+    private String name;
+    private ArrayList<Signal> portsIn;
+    private ArrayList<Signal> portsOut;
+    private ArrayList<Component> components;
+    private ArrayList<Signal> signaux;
+    private ArrayList<String> processes;
+
+    public Entity(String name) {
+        this.name = name;
+        this.portsIn = new ArrayList<>();
+        this.portsOut = new ArrayList<>();
+        this.components = new ArrayList<>();
+        this.signaux = new ArrayList<>();
+        this.processes = new ArrayList<>();
+
+
+        File f = new File(name + ".vhd");
+        String text = new String();
+        try {
+            text = IO.loadFile(f);
+        } catch (IOException e) {
+            System.out.println("Impossible de charger l'entité " + name);
+            System.exit(1);
+        }
+        // Nettoyage du texte
+        text = text.replaceAll("(--|library|use)[^\n]*", "");
+        text = text.replaceAll(" +", " ");
+        text = text.replaceAll(" ;", ";");
+        text = text.replaceAll("\n ", "\n");
+        text = text.replaceAll("(\t|\n)+", "\n");
+        text = text.replaceAll("\\( ", "(");
+        text = text.replaceAll("\nentity", "entity");
+
+        // Récupération de la definition de l'entité
+        String[] tab = text.split("end " + name + ";");
+        String entity = tab[0];
+        text = tab[1];
+        entity = entity.replaceFirst("entity " + name + " is\nPort \\(", "");
+        ArrayList<String> ports = new ArrayList<>();
+        ports.addAll(Arrays.asList(entity.split("\n")));
+        ports.forEach(port ->
+            { if (port.contains("in")) {
+                this.portsIn.add(new Signal(port.split(" ")[0]));
+              } else if (port.contains("out")) {
+                this.portsOut.add(new Signal(port.split(" ")[0]));
+              } else {
+                System.out.println("WARNING : Port illisible");
+              }
+            });
+
+        // Récupération des composants -> inutile, on travaille sur les instances
+        text = text.replaceFirst("[^\n]*\n", "");
+        text = text.replaceFirst("[^\n]*\n", "");
+        tab = text.split("end component;\n");
+        text = tab[tab.length - 1];
+
+        // Récupération des signaux
+
+        System.out.println(text);
+    }
+
+    public ArrayList<Signal> getPortsIn() {
+        return portsIn;
+    }
+
+    public ArrayList<Signal> getPortsOut() {
+        return portsOut;
+    }
+
+    @Override
+    public String toString() {
+        return "Entity{" +
+                "name='" + name + '\'' +
+                ", portsIn=" + portsIn +
+                ", portsOut=" + portsOut +
+                ", components=" + components +
+                ", signaux=" + signaux +
+                ", processes=" + processes +
+                '}';
+    }
+
+    public void writeScheme() {
+        //TODO
+    }
+}

src/main/java/IO.java

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+import java.io.*;
+
+public class IO {
+    public static String loadFile(File f) throws IOException {
+        BufferedInputStream in = new BufferedInputStream(new FileInputStream(f));
+        StringWriter out = new StringWriter();
+        int b;
+        while ((b=in.read()) != -1)
+            out.write(b);
+        out.flush();
+        out.close();
+        in.close();
+        return out.toString();
+    }
+
+    public static void writeFile(String string, String name) throws IOException {
+        File f = new File(name);
+        BufferedOutputStream out = new BufferedOutputStream(new FileOutputStream(f));
+        StringReader in = new StringReader(string);
+        int b;
+        while ((b=in.read()) != -1)
+            out.write(b);
+        out.flush();
+        out.close();
+        in.close();
+        f.createNewFile();
+    }
+}

src/main/java/Main.java

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+public class Main {
+    public static void main(String[] args) {
+        Entities.getEntity("System");
+    }
+}

src/main/java/Signal.java

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+public class Signal {
+    private String name;
+
+    public Signal(String name) {
+        this.name = name;
+    }
+
+    public String getName() {
+        return name;
+    }
+
+    @Override
+    public String toString() {
+        return "Signal{" +
+                "name='" + name + '\'' +
+                '}';
+    }
+}