commit fa13faf6672ec75122d7f75e278303d039bef901 Author: Faure Paul Date: Fri Jul 30 17:15:26 2021 +0200 Initial commit diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..9660109 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +gradlew +gradlew.bat +gradle/* +build/* +.gradle/* \ No newline at end of file diff --git a/.idea/.gitignore b/.idea/.gitignore new file mode 100644 index 0000000..26d3352 --- /dev/null +++ b/.idea/.gitignore @@ -0,0 +1,3 @@ +# Default ignored files +/shelf/ +/workspace.xml diff --git a/.idea/compiler.xml b/.idea/compiler.xml new file mode 100644 index 0000000..fb7f4a8 --- /dev/null +++ b/.idea/compiler.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/.idea/gradle.xml b/.idea/gradle.xml new file mode 100644 index 0000000..13a8247 --- /dev/null +++ b/.idea/gradle.xml @@ -0,0 +1,18 @@ + + + + + + + \ No newline at end of file diff --git a/.idea/jarRepositories.xml b/.idea/jarRepositories.xml new file mode 100644 index 0000000..fdc392f --- /dev/null +++ b/.idea/jarRepositories.xml @@ -0,0 +1,20 @@ + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/misc.xml b/.idea/misc.xml new file mode 100644 index 0000000..62269df --- /dev/null +++ b/.idea/misc.xml @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/.idea/vcs.xml b/.idea/vcs.xml new file mode 100644 index 0000000..94a25f7 --- /dev/null +++ b/.idea/vcs.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/System.vhd b/System.vhd new file mode 100644 index 0000000..7ef2510 --- /dev/null +++ b/System.vhd @@ -0,0 +1,235 @@ +---------------------------------------------------------------------------------- +-- Company: INSA-Toulouse +-- Engineer: Paul Faure +-- +-- Create Date: 13.04.2021 10:19:15 +-- Module Name: System - Behavioral +-- Project Name: Processeur sécurisé +-- Target Devices: Basys 3 ARTIX7 +-- Tool Versions: Vivado 2016.4 +-- Description: Environnement du processeur, mapping entre le processeur et les periphériques, affectation des ports la carte +-- +-- Dependencies: +-- - Clock_Divider +-- - Pipeline +-- - Pipeline_NS +-- - PeripheriqueEcran +-- - PeripheriqueClavier +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Lien avec le fichier de contraintes +-- Récupération du VGA +-- Récupération du PS2 +-- Récupération d'un bouton pour RST +-- Récupération de la clock +entity System is + Port ( vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + btnC : in STD_LOGIC; + CLK : in STD_LOGIC); +end System; + +architecture Structural of System is + + component Pipeline is + Generic (Nb_bits : Natural := 8; + Instruction_En_Memoire_Size : Natural := 29; + Addr_Memoire_Instruction_Size : Natural := 3; + Memoire_Instruction_Size : Natural := 8; + Instruction_Bus_Size : Natural := 5; + Nb_Instructions : Natural := 32; + Nb_Registres : Natural := 16; + Addr_registres_size : Natural := 4; + Memoire_Size : Natural := 32; + Adresse_mem_size : Natural := 5; + Memoire_Adresses_Retour_Size : Natural := 16; + Adresse_Memoire_Adresses_Retour_Size : Natural := 4); + Port (CLK : in STD_LOGIC; + RST : in STD_LOGIC; + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); + end component; + + component Pipeline_NS is + Generic (Nb_bits : Natural := 8; + Instruction_En_Memoire_Size : Natural := 29; + Addr_Memoire_Instruction_Size : Natural := 3; + Memoire_Instruction_Size : Natural := 8; + Instruction_Bus_Size : Natural := 5; + Nb_Instructions : Natural := 32; + Nb_Registres : Natural := 16; + Addr_registres_size : Natural := 4; + Memoire_Size : Natural := 32; + Adresse_mem_size : Natural := 5); + Port (CLK : STD_LOGIC; + RST : STD_LOGIC; + STD_IN : in STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_IN_Av : in STD_LOGIC; + STD_IN_Request : out STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC; + STD_OUT_Int : out STD_LOGIC); + end component; + + component PeripheriqueEcran + Generic ( Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + CLK_VGA : in STD_LOGIC; + RST : in STD_LOGIC; + + vgaRed : out STD_LOGIC_VECTOR (3 downto 0); + vgaBlue : out STD_LOGIC_VECTOR (3 downto 0); + vgaGreen : out STD_LOGIC_VECTOR (3 downto 0); + Hsync : out STD_LOGIC; + Vsync : out STD_LOGIC; + + STD_OUT : in STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : in STD_LOGIC; + STD_OUT_Int : in STD_LOGIC); + end component; + + component PeripheriqueClavier + Generic (Nb_Bits : Natural); + Port ( CLK : in STD_LOGIC; + RST : in STD_LOGIC; + PS2Clk : in STD_LOGIC; + PS2Data : in STD_LOGIC; + STD_IN : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_IN_Av : out STD_LOGIC; + STD_IN_Request : in STD_LOGIC; + STD_OUT : out STD_LOGIC_VECTOR (Nb_Bits - 1 downto 0); + STD_OUT_Av : out STD_LOGIC); + end component; + + component Clock_Divider is + Port ( CLK_IN : in STD_LOGIC; + CLK_OUT : out STD_LOGIC); + end component; + + -- signaux auxiliaires + signal my_RST : STD_LOGIC; -- Signal de RST (inversion par rapport au btnC) + signal my_CLK : STD_LOGIC; -- Signal de clock (divisée par rapport CLK) + -- signaux de gestion de l'entrée + signal STD_IN : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Entrée + signal STD_IN_Av : STD_LOGIC := '0'; -- Entrée disponible en lecture sur le clavier + signal STD_IN_Request : STD_LOGIC := '0'; -- Demande d'une entrée au clavier + -- signaux de gestion de la sortie + signal STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie vers l'écran + signal STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible pour l'écran + signal STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) pour l'écran + signal pipeline_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Pipeline + signal pipeline_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Pipeline + signal pipeline_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le pipeline + signal clavier_STD_OUT : STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); -- Sortie depuis le Clavier + signal clavier_STD_OUT_Av : STD_LOGIC := '0'; -- Sortie disponible depuis le Clavier + signal clavier_STD_OUT_Int : STD_LOGIC := '0'; -- Type de la sortie (entier ou ASCII) depuis le Clavier + + constant SECURISED : boolean := false; -- Booléen de sélection entre la version sécurisée et non sécurisée + +begin + + -- Diviseur de clock + clk_div : Clock_Divider + port map (CLK_IN => CLK, + CLK_OUT => my_CLK); + + + -- Generation du pipeline en fonction de la condition sécurisé ou non + instance: if (SECURISED) generate + instance_securisee : entity work.Pipeline + generic map (Nb_bits => 16, + Instruction_En_Memoire_Size => 53, + Addr_Memoire_Instruction_Size => 9, + Memoire_Instruction_Size => 512, + Instruction_Bus_Size => 5, + Nb_Instructions => 32, + Nb_Registres => 16, + Addr_registres_size => 4, + Memoire_Size => 64, + Adresse_mem_size => 6, + Memoire_Adresses_Retour_Size => 4, + Adresse_Memoire_Adresses_Retour_Size => 2) + port map (CLK => my_CLK, + RST => my_RST, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => pipeline_STD_OUT, + STD_OUT_Av => pipeline_STD_OUT_Av, + STD_OUT_Int => pipeline_STD_OUT_Int); + else generate + instance_non_securisee : entity work.Pipeline_NS + generic map (Nb_bits => 16, + Instruction_En_Memoire_Size => 53, + Addr_Memoire_Instruction_Size => 9, + Memoire_Instruction_Size => 512, + Instruction_Bus_Size => 5, + Nb_Instructions => 32, + Nb_Registres => 16, + Addr_registres_size => 4, + Memoire_Size => 64, + Adresse_mem_size => 6) + port map (CLK => my_CLK, + RST => my_RST, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => pipeline_STD_OUT, + STD_OUT_Av => pipeline_STD_OUT_Av, + STD_OUT_Int => pipeline_STD_OUT_Int); + end generate; + + instance_perif_ecran : PeripheriqueEcran + generic map ( Nb_Bits => 16) + port map ( CLK => my_CLK, + CLK_VGA => CLK, + RST => my_RST, + + vgaRed => vgaRed, + vgaBlue => vgaBlue, + vgaGreen => vgaGreen, + Hsync => Hsync, + Vsync => Vsync, + + STD_OUT => STD_OUT, + STD_OUT_Av => STD_OUT_Av, + STD_OUT_Int => STD_OUT_Int); + + instance_perif_clavier : PeripheriqueClavier + generic map (Nb_Bits => 16) + port map ( CLK => my_CLK, + RST => my_RST, + PS2Clk => PS2Clk, + PS2Data => PS2Data, + STD_IN => STD_IN, + STD_IN_Av => STD_IN_Av, + STD_IN_Request => STD_IN_Request, + STD_OUT => clavier_STD_OUT, + STD_OUT_Av => clavier_STD_OUT_Av); + + + -- Gestion du RST (inversion d'état) + my_RST <= '1' when btnC = '0' else + '0'; + + + -- Gestion de l'affichage sur l'écran lors d'une demande d'entrée le clavier affiche sur l'écran + STD_OUT <= clavier_STD_OUT when STD_IN_Request = '1' else pipeline_STD_OUT; + STD_OUT_Av <= clavier_STD_OUT_Av when STD_IN_Request = '1' else pipeline_STD_OUT_Av; + STD_OUT_Int <= clavier_STD_OUT_Int when STD_IN_Request = '1' else pipeline_STD_OUT_Int; + +end Structural; + diff --git a/build.gradle b/build.gradle new file mode 100644 index 0000000..95df5f5 --- /dev/null +++ b/build.gradle @@ -0,0 +1,14 @@ +plugins { + id 'java' +} + +group 'org.example' +version '1.0-SNAPSHOT' + +repositories { + mavenCentral() +} + +dependencies { + testCompile group: 'junit', name: 'junit', version: '4.12' +} diff --git a/settings.gradle b/settings.gradle new file mode 100644 index 0000000..562f22d --- /dev/null +++ b/settings.gradle @@ -0,0 +1,2 @@ +rootProject.name = 'ParserVHDL' + diff --git a/src/main/java/Affectation.java b/src/main/java/Affectation.java new file mode 100644 index 0000000..433319e --- /dev/null +++ b/src/main/java/Affectation.java @@ -0,0 +1,17 @@ +public class Affectation { + private Signal signal1; + private Signal signal2; + + public Affectation(Signal signal1, Signal signal2) { + this.signal1 = signal1; + this.signal2 = signal2; + } + + public Signal getSignal1() { + return signal1; + } + + public Signal getSignal2() { + return signal2; + } +} diff --git a/src/main/java/Component.java b/src/main/java/Component.java new file mode 100644 index 0000000..facf3c2 --- /dev/null +++ b/src/main/java/Component.java @@ -0,0 +1,16 @@ +import java.util.ArrayList; + +public class Component { + private Entity entity; + private ArrayList affectations; + private Entity entity2; + private ArrayList affectations2; + private Signal condition; + private boolean conditionnelle; + + public Component(String entity, String affectations) { + this.entity = Entities.getEntity(entity); + // TODO Créer les affectations + this.conditionnelle = false; + } +} diff --git a/src/main/java/Entities.java b/src/main/java/Entities.java new file mode 100644 index 0000000..fce78c1 --- /dev/null +++ b/src/main/java/Entities.java @@ -0,0 +1,14 @@ +import java.util.ArrayList; + +public class Entities { + private static ArrayList entities = new ArrayList<>(); + private static ArrayList entitiesNames = new ArrayList<>(); + + public static Entity getEntity(String name) { + if (! entitiesNames.contains(name)) { + entities.add(new Entity(name)); + entitiesNames.add(name); + } + return entities.get(entitiesNames.indexOf(name)); + } +} diff --git a/src/main/java/Entity.java b/src/main/java/Entity.java new file mode 100644 index 0000000..2175a12 --- /dev/null +++ b/src/main/java/Entity.java @@ -0,0 +1,92 @@ +import java.io.File; +import java.io.IOException; +import java.util.ArrayList; +import java.util.Arrays; +import java.util.stream.Collectors; + +public class Entity { + private String name; + private ArrayList portsIn; + private ArrayList portsOut; + private ArrayList components; + private ArrayList signaux; + private ArrayList processes; + + public Entity(String name) { + this.name = name; + this.portsIn = new ArrayList<>(); + this.portsOut = new ArrayList<>(); + this.components = new ArrayList<>(); + this.signaux = new ArrayList<>(); + this.processes = new ArrayList<>(); + + + File f = new File(name + ".vhd"); + String text = new String(); + try { + text = IO.loadFile(f); + } catch (IOException e) { + System.out.println("Impossible de charger l'entité " + name); + System.exit(1); + } + // Nettoyage du texte + text = text.replaceAll("(--|library|use)[^\n]*", ""); + text = text.replaceAll(" +", " "); + text = text.replaceAll(" ;", ";"); + text = text.replaceAll("\n ", "\n"); + text = text.replaceAll("(\t|\n)+", "\n"); + text = text.replaceAll("\\( ", "("); + text = text.replaceAll("\nentity", "entity"); + + // Récupération de la definition de l'entité + String[] tab = text.split("end " + name + ";"); + String entity = tab[0]; + text = tab[1]; + entity = entity.replaceFirst("entity " + name + " is\nPort \\(", ""); + ArrayList ports = new ArrayList<>(); + ports.addAll(Arrays.asList(entity.split("\n"))); + ports.forEach(port -> + { if (port.contains("in")) { + this.portsIn.add(new Signal(port.split(" ")[0])); + } else if (port.contains("out")) { + this.portsOut.add(new Signal(port.split(" ")[0])); + } else { + System.out.println("WARNING : Port illisible"); + } + }); + + // Récupération des composants -> inutile, on travaille sur les instances + text = text.replaceFirst("[^\n]*\n", ""); + text = text.replaceFirst("[^\n]*\n", ""); + tab = text.split("end component;\n"); + text = tab[tab.length - 1]; + + // Récupération des signaux + + System.out.println(text); + } + + public ArrayList getPortsIn() { + return portsIn; + } + + public ArrayList getPortsOut() { + return portsOut; + } + + @Override + public String toString() { + return "Entity{" + + "name='" + name + '\'' + + ", portsIn=" + portsIn + + ", portsOut=" + portsOut + + ", components=" + components + + ", signaux=" + signaux + + ", processes=" + processes + + '}'; + } + + public void writeScheme() { + //TODO + } +} diff --git a/src/main/java/IO.java b/src/main/java/IO.java new file mode 100644 index 0000000..78afad7 --- /dev/null +++ b/src/main/java/IO.java @@ -0,0 +1,28 @@ +import java.io.*; + +public class IO { + public static String loadFile(File f) throws IOException { + BufferedInputStream in = new BufferedInputStream(new FileInputStream(f)); + StringWriter out = new StringWriter(); + int b; + while ((b=in.read()) != -1) + out.write(b); + out.flush(); + out.close(); + in.close(); + return out.toString(); + } + + public static void writeFile(String string, String name) throws IOException { + File f = new File(name); + BufferedOutputStream out = new BufferedOutputStream(new FileOutputStream(f)); + StringReader in = new StringReader(string); + int b; + while ((b=in.read()) != -1) + out.write(b); + out.flush(); + out.close(); + in.close(); + f.createNewFile(); + } +} diff --git a/src/main/java/Main.java b/src/main/java/Main.java new file mode 100644 index 0000000..4879dda --- /dev/null +++ b/src/main/java/Main.java @@ -0,0 +1,5 @@ +public class Main { + public static void main(String[] args) { + Entities.getEntity("System"); + } +} diff --git a/src/main/java/Signal.java b/src/main/java/Signal.java new file mode 100644 index 0000000..ee5589a --- /dev/null +++ b/src/main/java/Signal.java @@ -0,0 +1,18 @@ +public class Signal { + private String name; + + public Signal(String name) { + this.name = name; + } + + public String getName() { + return name; + } + + @Override + public String toString() { + return "Signal{" + + "name='" + name + '\'' + + '}'; + } +}